CN101299657B - Symbol timing synchronizing apparatus for complete digital receiver - Google Patents
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Abstract
A complete digital receiver symbol timing synchronizing apparatus of the digital communication technique domain, includes an interpolator, a sampling clock frequency error estimation module, a loop filter, an interpolation controller, a sampling clock phase error calculation module and a sampling phase selection controller, wherein, the sample value of the system over-sampling is taken as the input of the interpolator; the sample value result after the regulation of the interpolator output is taken as the input of the sampling clock frequency error estimation module, for finding the correct sampling point position; the sampling phase selection controller sends out commands to control a lower sampling device, thereby making the lower sampling device complete sampling in the optimum time; the output result of the lower sampling device is taken as the input of the sampling clock frequency error estimation module, for calculating the sampling clock frequency bias; the interpolation controller controls the work process of the interpolator according to the sampling clock frequency bias fed in from the loop filter, for implementing the exactness correction to the sampling values. The loop circuit structure of the invention is quite simple, and is realized by hardware in the digital domain.
Description
Technical field
The present invention relates to a kind of synchronizer of digital communication technology field, what be specifically related to is a kind of symbol timing synchronizing apparatus for complete digital receiver.
Background technology
Along with the development of Digital Signal Processing and the reduction of device cost, the transceiver of digital communication system develops to the direction of total digitalization, software implementation (software radio architecture).Symbol regularly is the key technology of all-digital receiver, is the basis of correct sampling judgement, and system's quality regularly will directly influence its performance.This also is the most challenging part of all-digital receiver.Because the clock skew that Channel Transmission time-delay and oscillator job insecurity cause all can make the sampling clock frequency of transmitting-receiving two-end incomplete same, thereby there is a little deviation in the sample value of transmitting terminal and receiving terminal between the duration, this little deviation is accumulated to and to a certain degree will has more a sample value or omit a sample value, finally cause receiver can't correctly receive N sampling point, sampling can't be carried out in the best time, thereby can not correctly recover original data, therefore need estimate and compensate this sampling clock frequency difference, the time interval with assurance transmitting-receiving two-end sampled point is consistent, and guarantees simultaneously to sample on the time point of signal to noise ratio maximum.
For carrier wave communication system, the existence of timing phase error makes sampling time not on the sampled point of signal to noise ratio maximum, causes planisphere to disperse, and worsens error performance; And for multi-carrier communications systems, the transmitting-receiving two-end sample clock frequency deviation disturbs (ISI) except between the meeting created symbol, also can cause phase place rotation, amplitude fading, and introducing inter-carrier interference (ICI), destroy the orthogonality between subcarrier, and its accumulation results can cause the symbol timing wander, thereby worsen the result of frame synchronization, thereby multicarrier system is more more responsive than single-carrier modulated to timing error and frequency shift (FS), and the requirement of its synchronization accuracy is higher than single-carrier modulated.In sum, though a kind of high-precision symbol timing synchronizing apparatus that is easy to realize for single-carrier system or multicarrier system all has significant values.
Literature search through prior art is found, Floyd M.Gardner is at " IEEE TRANSACTIONS ONCOMMUNICATIONS " NO.6,1993, the last proposition of Pages:998-1008 " Interpolation inDigital Modems---Part II:Implementation and Performance " (interpolation in the digital modems is handled---second portion: realize and performance, Floyd M.Gardner, ieee communication journal in 1993, the 998-1008 page or leaf), this article has proposed a kind ofly to utilize interpolation filter to finish the synchronous implementation structure of sampling clock at numeric field, mainly by interpolater, the sampling clock error estimator, loop filter, digital controlled oscillator and sampling decision device are formed.Studies show that: low, the easy realization of synchronizer cost that recovers sampled value by digital interpolation, and to adopt the quantity of the required multiplier of polynomial interopolation filter that the Farrow structure realizes only be about half of conventional filter.But because this sign synchronization device has been finished sample value interpolation and two processing of down-sampling simultaneously, therefore can't select the sample point of over-sampling, thereby can't guarantee that final output result is the optimum value that obtains under the signal to noise ratio maximum case, especially disturb under the modulation system exponent number condition with higher of comparatively serious or system's employing at interchannel noise, will cause the operation of receiver performance decrease.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, from the angle of digital communication system receiver physical layer a kind of symbol timing synchronizing apparatus for complete digital receiver has been proposed, the influence of this device energy compensate for channel transmission delay and transceiver two ends clock skew, guarantee to sample and constantly carry out in the best extraction, thereby the intersymbol interference in the elimination system makes minimum bit-error rate.This device ring line structure is simpler, is easy to be realized by hardware on numeric field.
The present invention is achieved by the following technical solutions, the present invention includes: interpolater, frequency errors of sampling clock estimation module, loop filter, interpolation controller, sampling clock phase error calculating module, sampling phase selection control, wherein:
Interpolater is used for sampled value being revised by interpolation filter at numeric field, makes the transmitting-receiving two-end clock frequency equate;
The frequency errors of sampling clock estimation module is used to extract transmitting-receiving two-end frequency deviation of clock value;
Loop filter is used for tracking sampling frequency deviation of clock value;
The interpolation controller is used for the interpolation parameter of calculating filter, the control interpolater course of work;
Down-sampler is used for the oversampled signals sample value is extracted;
The sampling clock phase error calculating module is used to estimate the optimum sampling point position;
The sampling phase selection control is used to guarantee sample and carries out in the best time, makes error rate minimum;
Signal transitive relation between above-mentioned each module is: the sample value of system's over-sampling is as the input of interpolater; The adjusted sample value result of interpolater output is as the input of sampling clock phase error calculating module, in order to find correct sampling point position; The sampling phase selection control sends the commands for controlling down-sampler, makes it finish sampling in the best time; The result of down-sampler output is as the input of frequency errors of sampling clock estimation module, in order to the calculating sampling clock frequency deviation; The interpolation controller is realized the correct correction to sampled value according to the course of work of the sampling clock frequency deviation value control interpolater of loop filter feed-in.
In the above-mentioned synchronizer of the present invention, sample clock frequency deviation compensation and timing phase deviation compensation two aspects have been comprised.Wherein, interpolater, frequency errors of sampling clock estimation module, loop filter and interpolation controller are formed sampling clock compensate of frequency deviation device, and the effect of sampling clock compensate of frequency deviation device is to make it to equate with the clock originator frequency as far as possible by the sampling clock frequency that the mode of time domain interpolation is adjusted receiving end.When receiving end sampling clock frequency when making a start the sampling clock frequency, can interpolation go out to estimate sample value; When the sampling clock frequency of making a start during greater than receiving end sampling clock frequency, can discard the estimation sample value, send into other follow-up modules of system to guarantee receiver with the sample value after will compensating near the sampling rate of making a start.
Described interpolater is used for the over-sampling value that receives is revised, and adopts the digital interpolation filter of Farrow structure, and receiving sample value with each is basic point, according to the parameter μ of interpolation controller feed-in
k---be the normalization distance between the receiving end actual samples moment and the correct sampling instant, thereby come the approximate optimum sampling sample value constantly that recovers with limited actual samples point.In order to finish the operation of losing a little or inserting point, interpolater is made up of the interpolation filter of two identical Farrow structures, be called main Farrow filter and from the Farrow filter, the Farrow structure can be divided into parallelism wave filter group and two modules of multiplicaton addition unit, because master and slave Farrow Filter Structures is identical, get final product so only need to realize a cover parallelism wave filter group in this device, but multiplicaton addition unit need be realized respectively to receive different interpolation parameters.
Described frequency errors of sampling clock estimation module is used to extract transmitting-receiving two-end frequency deviation of clock value, generally with fs
Receiving end/ fs
Make a startCharacterize---be the ratio of the receiving end sampling clock frequency and the sampling clock frequency of making a start.For single-carrier system, frequency offset estimating algorithm commonly used has: early-late door algorithm, Mueller and Muller algorithm and Gardner algorithm; For multicarrier system, the sampling clock frequency offset estimating algorithm based on pilot tone commonly used.
Described loop filter is used for tracking sampling frequency deviation of clock value, can adopt second order filter to realize, comprises proportional path and path of integration.
The sampling clock frequency deviation value that described interpolation controller provides according to loop filter, calculate the interpolation parameter of master and slave Farrow filter respectively, and control interpolation result's output procedure---determine promptly that under current state principal and subordinate Farrow filter result should be simultaneously effectively or for invalid or have only main Farrow filter result effective simultaneously.
In the above-mentioned synchronizer of the present invention, sampling clock phase error calculating module, sampling phase selection control and down-sampler are formed the timing phase offset compensation device, the timing phase offset compensation device is used for finding from the sample value of over-sampling the sampled point of signal to noise ratio maximum, and it is extracted, to guarantee the sampled signal quality, reduce the error rate.
Described sampling clock phase error calculating module is used for searching the sample value of all oversampled points energy maximums.What characterize owing to each oversampled points in the symbol period is actual is the sample value of respectively dividing equally the phase place place in this symbol period, therefore choose one section and receive data, calculate the energy of each sampled point, and ask the energy sum respectively by affiliated out of phase, find the wherein phase position of gross energy maximum, and its sequence lower label is exported as the phase estimation result.
Described sampling phase selection control is controlled the sampling point selection course of down-sampler according to the sampling phase estimated result.
Described down-sampler extracts the revised over-sampling sample value of interpolater output, the final realization near the sampling rate of making a start the sample value of optimum sampling position is sent into other follow-up modules of system.
Compare with symbol timing synchronizing apparatus in the existing all-digital receiver, device of the present invention has the following advantages:
(1) with frequency errors of sampling clock compensation and phase error compensation separate processes.Compensation to frequency errors of sampling clock can guarantee transmitting-receiving two-end sample frequency unanimity, can guarantee to export the result to the compensation of sampling clock phase error and be always the best sample value that obtains under the signal to noise ratio maximum case, thereby can promote the precision of exporting sampled point, under the overall performance of raising system, especially comparatively serious or modulation system exponent number condition with higher that system adopts at interchannel noise.
(2) interpolater all carries out interpolation processing to each oversampled points, and establishes master and slave filter sample value is accepted or rejected, thereby improves computational accuracy.
(3) the Farrow filter construction that is adopted makes filter parameter minimum, thereby reduces the multiplier number, and the result is exported in recycling when realizing, simplifies the multiplier redundancy, improves operation efficiency.
(4) the sampling clock phase error calculating module draws the sampling phase that select, thereby can remove the single estimation error by to the calculating of over-sampling sample value energy in one period long period relatively, improves the accuracy that phase place is selected.
Description of drawings
Fig. 1 is a general construction block diagram according to the preferred embodiment of the invention;
Fig. 2 is a Farrow filter block diagram according to the preferred embodiment of the invention;
Fig. 3 is a sample clock frequency deviation compensation arrangement block diagram according to the preferred embodiment of the invention;
Fig. 4 is that the timing phase deviation compensation is adjusted block diagram according to the preferred embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
Fig. 1 shows the general structure block diagram of the symbol timing synchronizing apparatus for complete digital receiver of the preferred embodiment of the present invention.
With reference to Fig. 1, this timing synchronization device comprises: interpolater 100, frequency errors of sampling clock estimation module 200, loop filter 300, interpolation controller 400, down-sampler 500, sampling clock phase error calculating module 600, sampling phase selection control 700.Annexation between these parts is: system's over-sampling output is connected with the input of interpolater 100, the output of interpolater 100 is connected with the input of down-sampler 500 and the input of sampling clock phase error calculating module 600 simultaneously, the output of sampling clock phase error calculating module 600 is connected with the input of sampling phase selection control 700, the output of sampling phase selection control 700 is connected with the input of down-sampler 500, the output of down-sampler 500 is connected with the input of frequency errors of sampling clock estimation module 200, the output of frequency errors of sampling clock estimation module 200 is connected with the input of loop filter 300 and the input of follow-up baseband processing module simultaneously, the output of loop filter 300 is connected with the input of interpolation controller 400, and the output of interpolation controller 400 is connected with the input of interpolater.
Signal transitive relation between above-mentioned each module is: system is with the input as interpolater 100 of the sample value of 12 times of over-samplings, the revised sample value result of interpolater 100 outputs sends into sampling clock phase error calculating module 600, sampling phase selection control 700 is according to the correct sampling point position that sampling clock phase error calculating module 600 calculates, and sends commands for controlling down-sampler 500 and finishes sampling in the best time; Frequency errors of sampling clock estimation module 200 uses the specific frequency offset estimating algorithm computation based on pilot tone to draw the sampling clock frequency deviation, interpolation controller 400 is realized the correct correction to sampled value according to the course of work of the sampling clock frequency deviation value control interpolater 100 of loop filter 300 feed-ins.
Interpolater 100 is used for the over-sampling value that receives is revised, and comes the approximate optimum sampling sample value constantly that recovers with limited actual samples point.
Frequency errors of sampling clock estimation module 200 is used to extract transmitting-receiving two-end frequency deviation of clock value, generally characterizes with fs '/fs, i.e. the ratio of the receiving end sampling clock frequency and the sampling clock frequency of making a start.
Loop filter 300 is used for tracking sampling frequency deviation of clock value.
Interpolation controller 400 calculates the interpolation parameter of master and slave Farrow filter respectively according to the sampling clock frequency deviation value, and control interpolation result's output procedure.
Sampling clock phase error calculating module 600 is used for searching the sample value of all oversampled points energy maximums.
Sampling phase selection control 700 is used to control the sampling point selection course of down-sampler 500.
The over-sampling sample value of 500 pairs of interpolaters of down-sampler, 100 outputs extracts, the final realization near the sampling rate of making a start the sample value of optimum sampling position is sent into other follow-up modules of system.
Fig. 2 shows the Farrow filter block diagram of the symbol timing synchronizing apparatus of the preferred embodiment of the present invention.The Farrow filter construction can be divided into parallelism wave filter group and two modules of multiplicaton addition unit, list entries { x
InBe 12 times of over-sampling sample values of A/D converter, interpolation parameter μ
InBe the normalization distance between the receiving end actual samples moment and the correct sampling instant, the output { y of filter
OutTo be with a certain sampled point be benchmark, skew μ
InThe interpolation sample value at place, thus the farrow filter has been realized with the approximate target that recovers optimum sampling sample value constantly of limited actual samples point.Consider that FPGA realizes complexity and the resource that takies, in the preferred embodiment of the present invention, each Farrow filter adopts 48 parallel tap FIR filters to constitute.4 filters H M0～HM3 parameters of interpolater are:
{0，0，0，1.00000，0，0，0，0}
{-0.02971，0.18292，-0.74618，-0.13816，1.00942，-0.38219，0.12601，-0.02321}
{0.03621，-0.23982，1.11018，-1.71425，0.84299，0.01819，-0.06911，0.01670}
{-0.00650，0.05691，-0.36399，0.85241，-0.85241，0.36399，-0.05690，0.00650}
Fig. 3 shows the sample clock frequency deviation compensation arrangement block diagram of the symbol timing synchronizing apparatus of the preferred embodiment of the present invention.
Interpolation controller 400 is used to calculate the interpolation parameter μ of master and slave Farrow filter
kAnd ν
kIn the ordinary course of things, system is to main Farrow filter feed-in interpolation parameter μ
k, calculate next interpolation parameter μ constantly simultaneously
K+1, and whether next constantly needed to lose a little or insert to put and predict that prediction type is as follows:
θ
k+1＝μ
k+1+Δu＝μ
k+2Δu-int(μ
k+Δu)
As 0＜θ
K+1＜1 o'clock, the expression next one treated that estimation point still drops on this receiving cycle T
The s receiving endIn, need starting and to insert out a bit from the Farrow filter, next is constantly to from Farrow filter feed-in interpolation parameter ν
K+1=θ
K+1
As 1＜θ
K+1＜2 o'clock, the expression next one treated that estimation point has dropped on next cycle T
The s receiving endIn, not needing to insert some this moment does not need to lose a little yet;
Work as θ
K+1＞2 o'clock, the expression next one treated that estimation point has dropped on second period T behind this receiving cycle
The s receiving endIn, in this case, main Farrow does not just need output at next cycle, promptly abandons a point, and main Farrow resumes work in the next cycle again, and input parameter is θ
K+1Fractional part.
Fig. 4 shows the timing phase deviation compensation of the symbol timing synchronizing apparatus of the preferred embodiment of the present invention and adjusts block diagram.
Write down the phase value of each sampled point in the sampling clock phase error calculating module 600 by mould 12 counters, set 12 energy accumulation registers simultaneously, the energy addition of each phase place place sampled point is stored in the corresponding registers, find wherein that register of numerical value maximum by sort algorithm then, thereby obtained the sampling point position of gross energy maximum, and its sequence lower label has been exported as the phase estimation result.
Sampling phase selection control 700 is according to the sampling phase estimated result, the control down-sampler extracts the revised over-sampling sample value of interpolater output, the final realization near the sampling rate of making a start the sample value of optimum sampling position is sent into other follow-up modules of system.
In the present embodiment,, guarantee to export the best sample value of result, under the modulation system of 4QAM, can make systematic function obtain the above gain of 3dB for obtaining under the signal to noise ratio maximum case with frequency errors of sampling clock compensation and phase error compensation separate processes.
In the present embodiment, master and slave filter calculates simultaneously, and each oversampled points is all carried out interpolation processing, and sample value is accepted or rejected, and compares with the timing synchronization device that only adopts a filter, can improve computational accuracy.
In the present embodiment, sampling clock phase error calculating module 600 is to after the data computation in a period of time, just provide the phase place selective value, this is equivalent to operation result has been done average treatment, thereby can remove the single estimation error, prevent the shake in the phase place adjustment process, improve the accuracy that sampled point is selected.
Claims (8)
1. a symbol timing synchronizing apparatus for complete digital receiver is characterized in that, comprises interpolater, frequency errors of sampling clock estimation module, loop filter, interpolation controller, sampling clock phase error calculating module, sampling phase selection control, wherein:
Interpolater is used for sampled value being revised by interpolation at numeric field, makes the transmitting-receiving two-end clock frequency equate;
The frequency errors of sampling clock estimation module is used to extract transmitting-receiving two-end frequency deviation of clock value;
Loop filter is used for tracking sampling frequency deviation of clock value;
The interpolation controller is used to calculate the interpolation parameter of interpolater, the control interpolater course of work;
Down-sampler is used for the oversampled signals sample value is extracted;
The sampling clock phase error calculating module is used for searching the sample value position of all oversampled points energy maximums, and its sequence lower label is exported as the phase estimation result;
The sampling phase selection control is used to control the sampling point selection course of down-sampler, makes error rate minimum;
Signal transitive relation between above-mentioned each module is: system's over-sampling output is connected with the input of interpolater, the output of interpolater is connected with the input of down-sampler and the input of sampling clock phase error calculating module simultaneously, the output of sampling clock phase error calculating module is connected with the input of sampling phase selection control, the output of sampling phase selection control is connected with the input of down-sampler, the output of down-sampler is connected with the input of frequency errors of sampling clock estimation module, the output of frequency errors of sampling clock estimation module is connected with the input of loop filter and the input of follow-up baseband processing module simultaneously, the output of loop filter is connected with the input of interpolation controller, and the output of interpolation controller is connected with the input of interpolater;
The sample value of system's over-sampling is as the input of interpolater; The adjusted sample value result of interpolater output is as the input of sampling clock phase error calculating module, in order to find correct sampling point position; The sampling phase selection control sends the sampling point selection course of commands for controlling down-sampler; The adjusted sample value of interpolater output is also simultaneously as the input of down-sampler; The result of down-sampler output is as the input of frequency errors of sampling clock estimation module, in order to the calculating sampling clock frequency deviation; The interpolation controller is realized the correct correction to sampled value according to the course of work of the sampling clock frequency deviation value control interpolater of loop filter feed-in.
2. symbol timing synchronizing apparatus for complete digital receiver as claimed in claim 1, it is characterized in that, described interpolater, frequency errors of sampling clock estimation module, loop filter and interpolation controller are formed sampling clock compensate of frequency deviation device, the sampling clock frequency that this device is adjusted receiving end by the mode of time domain interpolation makes it to equate with the sampling clock frequency of making a start as far as possible, when making a start the sampling clock frequency, interpolation goes out to estimate sample value in receiving end sampling clock frequency; During greater than receiving end sampling clock frequency, discard the estimation sample value in the sampling clock frequency of making a start, to guarantee that receiver is to send sample value into the follow-up module of system near the sampling rate of making a start.
3. symbol timing synchronizing apparatus for complete digital receiver as claimed in claim 1 or 2 is characterized in that, described frequency errors of sampling clock estimation module is used to extract transmitting-receiving two-end frequency deviation of clock value, with fs
Receiving end/ fs
Make a startCharacterize---be the ratio of the receiving end sampling clock frequency and the sampling clock frequency of making a start.
4. symbol timing synchronizing apparatus for complete digital receiver as claimed in claim 1 or 2 is characterized in that, described loop filter is used for tracking sampling frequency deviation of clock value, adopts second order filter to realize, comprises proportional path and path of integration.
5. symbol timing synchronizing apparatus for complete digital receiver as claimed in claim 1 or 2, it is characterized in that, the sampling clock frequency deviation value that described interpolation controller provides according to loop filter, calculate the interpolation parameter of master and slave Farrow filter respectively, and control interpolation result's output procedure, determine promptly that under current state principal and subordinate Farrow filter result is for simultaneously effectively or for invalid or have only main Farrow filter result effective simultaneously; Described interpolater is made up of the interpolation filter of two identical Farrow structures, is called main Farrow filter and from the Farrow filter.
6. symbol timing synchronizing apparatus for complete digital receiver as claimed in claim 1, it is characterized in that, described sampling clock phase error calculating module, sampling phase selection control and down-sampler are formed the timing phase offset compensation device, this device is used for finding from the sample value of over-sampling the sampled point of signal to noise ratio maximum, and it is extracted, to reduce the error rate.
7. as claim 1 or 6 described symbol timing synchronizing apparatus for complete digital receiver, it is characterized in that described sampling phase selection control is controlled the sampling point selection course of down-sampler according to the sampling phase estimated result.
8. as claim 1 or 6 described symbol timing synchronizing apparatus for complete digital receiver, it is characterized in that, described down-sampler extracts the over-sampling sample value of interpolater output, the final realization near the sampling rate of making a start the sample value of energy maximum in all oversampled points is sent into the follow-up module of system.
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| EP1059759A2 (en) * | 1999-06-10 | 2000-12-13 | Lucent Technologies Inc. | Sample timing control for demodulation of phase-modulated signals |
| EP1267535B1 (en) * | 2001-06-11 | 2007-04-11 | SAMSUNG ELECTRONICS Co. Ltd. | Method and apparatus for symbol synchronisation in a multicarrier receiver |
| CN101207406A (en) * | 2006-12-20 | 2008-06-25 | 索尼株式会社 | Wireless communication apparatus and wireless communication method |
| CN201063650Y (en) * | 2007-02-28 | 2008-05-21 | 华南理工大学 | World microwave interoperability transmitting and receiving system |
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