CN101295674A - Fabricating method for semiconductor device - Google Patents
Fabricating method for semiconductor device Download PDFInfo
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- CN101295674A CN101295674A CNA2007100398767A CN200710039876A CN101295674A CN 101295674 A CN101295674 A CN 101295674A CN A2007100398767 A CNA2007100398767 A CN A2007100398767A CN 200710039876 A CN200710039876 A CN 200710039876A CN 101295674 A CN101295674 A CN 101295674A
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Abstract
A manufacture method for a semiconductor apparatus includes the following steps of: providing a semiconductor underlay with a first area and a second area; forming polysilicon layers on the semiconductor underlay; reducing the thickness of the polysilicon layer of the second area to lead the thickness of the polysilicon layer of the second area to be less than that of the first area; patterning the polysilicon layers of the first area and the second area; forming a first grid in the first area and forming a second grid in the second area. The technique of manufacturing the grids with different thicknesses of the method is simpler.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of semiconductor device.
Background technology
(Complementary Metal-Oxide-Semiconductor, CMOS) device is because characteristics such as its low-power consumption, the high speed of response are widely used in fields such as storage, communication, computer to complementary metal oxide semiconductors (CMOS).Include nmos pass transistor and PMOS transistor in the cmos device, the transistorized grid material of nmos pass transistor and PMOS is generally the polysilicon that the N type mixes or the P type mixes.Fig. 1 to Fig. 4 is the generalized section of each step corresponding structure of the manufacture method of existing a kind of cmos device.
As shown in Figure 1, in Semiconductor substrate 10, form shallow trench isolation from 11, P trap 12a and N trap 12b, described P trap is used to form the conducting channel of nmos pass transistor, described N trap is used to form the transistorized conducting channel of PMOS; Described shallow channel isolation area 11 is used to isolate described P trap 12a and N trap 12b; On described Semiconductor substrate 10, form oxide layer 14; Deposit spathic silicon layer 16 on described oxide layer 14.
As shown in Figure 2, spin coating photoresist on described polysilicon layer 16, and the described photoresist layer of patterning forms the gate pattern 18a and the transistorized gate pattern 18b of PMOS of nmos pass transistor.
As shown in Figure 3, etching by the polysilicon layer 16 of described gate pattern 18a and 18b covering, does not form nmos pass transistor grid 16a and the transistorized grid 16b of PMOS, and described grid 16a has identical thickness with 16b; Continuing etching removes not by the oxide layer 14 of described grid 16a and 16b covering.
As shown in Figure 4, remove described gate pattern 18a and 18b, form side wall 20a, form side wall 20b in the both sides of described grid 16b in the both sides of described grid 16a; Be infused in source electrode 22a and the drain electrode 22b that forms nmos pass transistor among the P trap 12a by ion, in described N trap 12b, form transistorized source electrode 24a of PMOS and drain electrode 24b.
Nmos pass transistor among the CMOS can also have different thickness with the transistorized grid of PMOS, and for example, the thickness of the polysilicon in the PMOS transistor is less than the thickness of polysilicon in the nmos pass transistor.Adopt the grid polycrystalline silicon of pair pmos transistor to return the method at quarter in existing a kind of method and reduce the transistorized gate of PMOS, as Fig. 5 to generalized section shown in Figure 7.
At first form the cmos device of grid as shown in Figure 4, and at the source electrode 22a of nmos pass transistor and the 22b that drains, transistorized source electrode 24a of PMOS and drain electrode 24b go up and form the metal silicide contact layer (not shown) with equal height;
Then as shown in Figure 5, on described Semiconductor substrate 10 with cmos device, form silicon oxide layer 28, the top of described grid 16a and 16b is exposed by cmp;
Then, as shown in Figure 6, cover photoresist layer 26 on nmos pass transistor, the transistorized polysilicon gate 16b of etching PMOS reduces its thickness;
As shown in Figure 7, remove described photoresist layer 26.
Further can be on described polysilicon gate 16a and 16b plated metal titanium or nickel (not shown), and form metal silicide by annealing.
It is comparatively complicated that the thickness that the method that above-mentioned polysilicon returns quarter reduces the PMOS grid forms different-thickness grid method manufacturing process.
In the patent No. is in the United States Patent (USP) of US7192822B2 and 6166413, can also find more information relevant with technique scheme.
Summary of the invention
The invention provides a kind of manufacture method of semiconductor device, the technology of the grid of this method manufacturing different-thickness is comparatively simple.
The manufacture method of a kind of semiconductor device provided by the invention comprises:
Semiconductor substrate with first area and second area is provided;
On described Semiconductor substrate, form polysilicon layer;
Reduce the polysilicon layer thickness of second area, make the polysilicon layer thickness of the polysilicon layer thickness of described second area less than described first area;
The polysilicon layer of graphical described first area and second area forms first grid in described first area, forms second grid at described second area.
Optionally, the described polysilicon layer thickness that reduces second area, the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area:
On the polysilicon layer of described first area, form cover layer;
As the barrier layer, the polysilicon layer of the described second area of etching makes the polysilicon layer thickness of its thickness less than described first area with described cover layer;
Remove described cover layer.
Optionally, the described polysilicon layer thickness that reduces second area, the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area:
On the polysilicon layer of described first area, form cover layer;
As the barrier layer, the polysilicon layer doping to described second area forms the doped polysilicon layer faster than polysilicon layer etch rate with described cover layer;
Remove described cover layer;
Etching is removed the doped polysilicon layer of second area.
Optionally, the described polysilicon layer thickness that reduces second area, the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area:
On the polysilicon layer of described first area, form cover layer;
As the barrier layer, the polysilicon layer doping to described second area forms the doped polysilicon layer faster than polysilicon layer etch rate with described cover layer;
Etching is removed the doped polysilicon layer of second area;
Remove described cover layer.
Optionally, described cover layer is a photoresist.
Optionally, the impurity that mixes of described doping is a kind of in phosphorus, the arsenic.
Optionally, the energy of described doping is 1 to 8KeV.
Optionally, the dosage of described doping is 2 * 10
15To 4 * 10
15Cm
-2
Optionally, the polysilicon layer of graphical described first area and second area forms first grid in described first area, and the step that forms second grid at described second area comprises:
On the polysilicon layer of described first area and second area, form anti-reflecting layer;
Spin coating photoresist layer on described anti-reflecting layer;
Graphical described photoresist layer forms the first grid pattern in the first area, forms the second grid pattern at second area;
Etching is removed not by the anti-reflecting layer and the polysilicon layer of described first grid pattern and second grid pattern covers;
Remove described first grid pattern, second grid pattern and anti-reflecting layer.
Optionally, the polysilicon layer of graphical described first area and second area forms first grid in described first area, and the step that forms second grid at described second area comprises:
On the polysilicon layer of described first area and second area, form metal level;
The described metal level of planarization;
Spin coating photoresist layer on described metal level;
Graphical described photoresist layer forms the first grid pattern in the first area, forms the second grid pattern at second area;
Etching is removed not by the metal level and the polysilicon layer of described first grid pattern and second grid pattern covers;
Remove described first grid pattern and second grid pattern.
Optionally, this method further comprises: before spin coating photoresist layer on the described metal level, form anti-reflecting layer earlier on described metal level; And after removing described first grid pattern and second grid pattern, remove described anti-reflecting layer.
Optionally, this method further comprises: after removing described first grid pattern and second grid pattern, described Semiconductor substrate is annealed.
Optionally, the metal material of described metal level comprises a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, titanium, vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum.
Compared with prior art, the present invention has the following advantages:
The thickness of the polysilicon layer by reducing second area make the polysilicon layer of first area and the polysilicon layer of second area produce thickness difference (being difference in height), and then the grid that makes first area and second area form semiconductor device has difference in height; Processing step is comparatively simple; In addition, when the thickness of the polysilicon layer that reduces described second area, can not impact other parts on the Semiconductor substrate.
Reduce the thickness of the polysilicon layer of second area by photoetching process and etching technics, processing step is comparatively simple: can adopt and form the same mask plate of N-well process in the second area in the photoetching process, lower to the requirement of aiming at (Overlay) technology in this photoetching process, process window is bigger; Etching technics is lower to live width and side wall profile requirement, thereby etching technics has bigger process window; In addition, only be that polysilicon layer and cover layer are exposed in the plasma environment in etching process, can not cause damage to the other parts on the Semiconductor substrate.
By the formation doped polysilicon layer that in the polysilicon layer of described second area, mixes, utilize described doped polysilicon layer to have then than the polysilicon layer of the first area characteristics of etch rate faster, the simultaneously polysilicon layer of the described first area of etching and the doped polysilicon layer of second area make the thickness of the remaining polysilicon layer of described second area less than the thickness of the remaining polysilicon layer in described first area; And then the thickness of polysilicon gate that makes the semiconductor device that forms at second area is less than the thickness of the polysilicon gate of the semiconductor device that forms in the first area; Because doped polysilicon layer has different etch rates with the polycrystalline silicon material of its bottom, can comparatively accurately judge etching terminal, the thickness of described doped polysilicon layer can be controlled by doping process, thereby, thickness in conjunction with the polysilicon layer that deposits in the depositing operation, can be controlled at the thickness of the remaining polysilicon layer of second area comparatively accurately, and then can comparatively accurately control the height of the polysilicon gate of the semiconductor device that generates in the second area, help to form and satisfy electrically and the semiconductor device of stability requirement.
By on the polysilicon layer of first area and second area, forming anti-reflecting layer, the difference in height (this difference in height is caused by thickness difference) that reduces or eliminate the polysilicon layer top of first area and second area helps to form the side wall profile first photoresist pattern and the second photoresist pattern preferably to the influence of photoresist layer on the one hand; On the other hand, form the sacrifice layer of first polysilicon gate and second polysilicon gate as etching, the etching that make to form described first polysilicon gate and second polysilicon gate can be finished substantially simultaneously, reduces or eliminates this etching gate dielectric layer or Semiconductor substrate are caused over etching.
By on the polysilicon layer of first area and second area, forming metal level, the difference in height (this difference in height is caused by thickness difference) that reduces or eliminate the polysilicon layer top of first area and second area helps to form the side wall profile first photoresist pattern and the second photoresist pattern preferably to the influence of photoresist layer on the one hand; On the other hand, metal level that forms and the metal material that can be used as formation metal silicide on first polysilicon gate and second polysilicon gate, can be directly after annealed with first polysilicon gate and second polysilicon gate in the polysilicon reaction generate metal silicide, simplify processing step, reduced cost.
Description of drawings
Fig. 1 to Fig. 4 is the generalized section of each step corresponding construction of manufacture method of a kind of cmos device of prior art;
Fig. 5 to Fig. 7 is the generalized section of each step corresponding construction of manufacture method of the another kind of cmos device of prior art;
Fig. 8 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention;
Fig. 9 be a kind of Semiconductor substrate and on the generalized section of gate dielectric layer;
Figure 10 is the generalized section that forms polysilicon layer on gate dielectric layer;
Figure 11 to Figure 13 for a kind of polysilicon layer thickness that reduces second area, make the generalized section of the polysilicon layer thickness of second area less than each step corresponding construction of embodiment of the method for the polysilicon layer thickness of first area;
Figure 14 to Figure 17 for the another kind of polysilicon layer thickness that reduces second area, make the generalized section of the polysilicon layer thickness of second area less than each step corresponding construction of the embodiment of the method for the polysilicon layer thickness of first area;
Figure 18 to Figure 21 is the polysilicon layer of a kind of graphical first area and second area, is forming first grid on the first area, forms the generalized section of each step corresponding construction of the embodiment of second grid on second area;
Figure 22 to 25 is the polysilicon layer of another kind of graphical first area and second area, is forming first grid on the first area, forms the generalized section of each step corresponding construction of the embodiment of second grid on second area.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 8 is the flow chart of embodiment of the manufacture method of semiconductor device of the present invention.
Flow chart as shown in Figure 8, step S100 provides the Semiconductor substrate with first area and second area.
Generalized section as shown in Figure 9 provides Semiconductor substrate 30, and described Semiconductor substrate 30 has first area 30a and second area 30b.Described Semiconductor substrate 30 materials can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, the material of described Semiconductor substrate 30 also can be a silicon Germanium compound, described Semiconductor substrate 30 can also be (Silicon OnInsulator, SOI) epitaxial layer structure on structure or the silicon of silicon on the insulating barrier.In the first area of described Semiconductor substrate 30 30a and second area 30b, can mix N type impurity or p type impurity and form N trap or P trap (not shown).Among the embodiment therein, in described first area 30a, mix p type impurity and form the P trap, be used to form the conducting channel of NMOS; In described second area 30b, mix N type impurity and form the N trap, be used to form the conducting channel of PMOS.
Described Semiconductor substrate 30 has gate dielectric layer 32, and described gate dielectric layer 32 covers described first area 30a and second area 30b at least.Described gate dielectric layer 32 is a kind of or combination in silica, the silicon oxynitride.The method that forms silica is that high temperature furnace pipe oxidation, rapid thermal annealing oxidation or original position steam produce oxidation (In-Situ Stream Generation, ISSG) a kind of in, silica is carried out nitrogen treatment can form silicon oxynitride, described nitrogenize can be a kind of in high temperature furnace pipe nitrogenize, rapid thermal annealing nitrogenize and the pecvd nitride.
Step S110, flow chart as shown in Figure 8 forms polysilicon layer on described Semiconductor substrate.
Generalized section as shown in figure 10 forms polysilicon layer 34 on described gate dielectric layer 32, described polysilicon layer 34 covers described first area 30a and second area 30b at least.
The method that forms described polysilicon layer 34 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Step S120, flow chart as shown in Figure 8 reduces the polysilicon layer thickness of second area, makes the polysilicon layer thickness of the polysilicon layer thickness of described second area less than described first area.
Among the embodiment therein, reduce the polysilicon layer thickness of second area, the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area: form cover layer on the polysilicon layer of described first area; As the barrier layer, the polysilicon layer of the described second area of etching makes the polysilicon layer thickness of its thickness less than described first area with described cover layer; Remove described cover layer.
Generalized section as shown in figure 11 forms cover layer 36a on the polysilicon layer 34 of described first area 30a.Among the embodiment therein, described cover layer 36a is a photoresist; The step of cover layer 36a that forms described photoresist is as follows: spin coating photoresist on the polysilicon layer 34 of described first area 30a and second area 30b, remove the photoresist on the polysilicon layer 34 of described second area 30b by exposure imaging; Described exposure technology can adopt with described second area 30b in form the identical mask plate of photoetching process of N trap.
Generalized section as shown in figure 12, with described cover layer 36a as the barrier layer, the polysilicon layer 34 of the described second area 30b of etching makes its thickness be decreased to described second area 30b and goes up the thickness of the thickness of remaining polysilicon layer 34a less than the polysilicon layer 34 on the described first area 30a; Among the embodiment therein, described etching is the plasma dry etching, and the etching gas of described plasma dry etching is fluorine-containing gas, for example can be CF
4, CF
4And O
2, SF
6, C
2F
2And O
2, NF
3In a kind of.
Generalized section is as shown in figure 13 removed described cover layer 36a.Among the embodiment therein, described cover layer 36a is a photoresist, and the method for removing the cover layer 36a of described photoresist is the wet-cleaned of oxygen gas plasma ashing and sulfuric acid, hydrogen peroxide mixed solution.
The polysilicon layer 34 of this first area 30a and the polysilicon layer 34a of second area 30b are used to generate the grid of semiconductor device; After removing described cover layer 36a, the polysilicon layer 34a top of the polysilicon layer 34 of described first area 30a and second area 30b has produced difference in height, and this difference in height is the difference in height of polysilicon gate of the semiconductor device of formation.
The technology of thickness of polysilicon layer 34 that reduces described second area 30b by photoetching, etching technics is comparatively simple: can adopt in the photoetching process with form second area 30b in the identical mask plate of N-well process, requirement to Alignment Process in this photoetching process is lower, and process window is bigger; Etching technics is lower to live width and side wall profile requirement, makes etching have bigger process window; In addition, only be that polysilicon layer 34 and cover layer 36a are exposed in the plasma environment in etching process, can not cause damage to the other parts on the Semiconductor substrate 30.
In a further embodiment, reduce the polysilicon layer thickness of second area, the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area: form cover layer on the polysilicon layer of described first area; As the barrier layer, the polysilicon layer doping to described second area forms the doped polysilicon layer faster than polysilicon layer etch rate with described cover layer; Remove described cover layer; Etching is removed the doped polysilicon layer of second area.
Generalized section as shown in figure 14 forms cover layer 36b on the polysilicon layer 34 of described first area 30a.Among the embodiment therein, described cover layer 36b is a photoresist; The step of cover layer 36b that forms described photoresist is as follows: spin coating photoresist on the polysilicon layer 34 of described first area 30a and second area 30b, remove the photoresist on the polysilicon layer 34 of described second area 30b by exposure imaging; Described exposure technology can adopt with described second area 30b in form the identical mask plate of photoetching process of N trap.
Generalized section as shown in figure 15, is mixed to the polysilicon layer 34 of described second area 30b as the barrier layer with described cover layer 36b, forms doped polysilicon layer 35, and the technology of described doping can be ion implantation technology; The doped polysilicon layer 35 that the impurity that the technology of described doping is mixed make to form has than polysilicon layer 34 etch rate faster.In doping process, the thickness and the concentration of the doped polysilicon layer 35 that can control formation by the energy and the dosage of controlled doping.Among the embodiment therein, the impurity that described doping is mixed is a kind of in phosphorus, the arsenic, and the energy of doping is 1 to 8KeV, and the dosage of doping is 2 * 10
15To 4 * 10
15Cm
-2
By in the polysilicon layer 34 of described second area 30b, mixing, form doped polysilicon layer 35, make the polysilicon layer 34 of described first area 30a and the doped polysilicon layer 35 of second area 30b have different etch rates, wherein, the doped polysilicon layer 35 that is mixed with impurity such as phosphorus, arsenic has etch rate faster, also promptly when the doped polysilicon layer 35 of the polysilicon layer 34 of first area 30a and second area 30b is etched simultaneously, described doped polysilicon layer 35 speed of removing that is etched is faster.
Generalized section as shown in figure 16, remove described cover layer 36b, among the embodiment therein, described cover layer 36b is a photoresist, and the method for removing the cover layer 36b of described photoresist is the wet-cleaned of oxygen gas plasma ashing and sulfuric acid, hydrogen peroxide mixed solution.
Generalized section as shown in figure 17, after removing described cover layer 36b, the polysilicon layer 34 of described first area 30a and the doped polysilicon layer 35 of second area 30b are carried out etching simultaneously, described etching stopping when the doped polysilicon layer 35 of described second area 30b is removed till, because described doped polysilicon layer 35 has than described polysilicon layer 34 etch rate faster, thereby after etching was finished, the thickness of the remaining polysilicon layer 34b of described second area 30b was less than the thickness of the remaining polysilicon layer 34c of described first area 30a.Among the embodiment therein, described etching is the plasma dry etching, and the etching gas of described plasma dry etching is fluorine-containing gas, for example can be CF
4, CF
4And O
2, SF
6, C
2F
2And O
2, NF
3In a kind of.
Form doped polysilicon layer 35 by in the polysilicon layer 34 of described second area 30b, mixing, utilize described doped polysilicon layer 35 to have then than the polysilicon layer 34 of the first area 30a characteristics of etch rate faster, the polysilicon layer 34a of the described first area 30a of while etching and the doped polysilicon layer 35 of second area 30b, after etching is finished, make the thickness of the remaining polysilicon layer 34b of described second area 30b less than the thickness of the remaining polysilicon layer 34c of described first area 30a; The polysilicon layer 34c of described first area 30a and the polysilicon layer 34b of second area 30b are used to generate the grid of semiconductor device; Thereby the thickness of the polysilicon gate of the semiconductor device that forms at second area 30b is also less than the thickness of the polysilicon gate of the semiconductor device that forms at second area 30a.
In the technology of thickness of the polysilicon layer 34b that makes second area 30b less than the thickness of the polysilicon layer 34c of first area 30a, technology is comparatively simple: the photoetching process that forms cover layer 36b can adopt with form second area 30b in the identical mask plate of N-well process, and this photoetching is lower to the requirement of aiming at (Overlay) technology, and process window is bigger; Etching technics is lower to live width and side wall profile requirement, thereby etching has bigger process window.
In addition, because described doped polysilicon layer 35 has different etch rates with the polycrystalline silicon material of its bottom, can comparatively accurately judge etching terminal, the thickness of described doped polysilicon layer 35 can be controlled by doping process, thereby, thickness in conjunction with the polysilicon layer 34 that deposits in the depositing operation, can be controlled at the thickness of the remaining polysilicon layer 34b of described second area 30b comparatively accurately, and then can comparatively accurately control the height of the polysilicon gate of the semiconductor device that generates among the described second area 30b, help to form and satisfy electrically and the semiconductor device of stability requirement.
In addition, only be that polysilicon layer 34 and doped polysilicon layer 35 are exposed in the plasma environment in etching process, can not cause damage to the other parts on the Semiconductor substrate 30.
In other embodiments, reduce the polysilicon layer thickness of second area, the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area: form cover layer on the polysilicon layer of described first area; As the barrier layer, the polysilicon layer doping to described second area forms the doped polysilicon layer faster than polysilicon layer etch rate with described cover layer; Etching is removed the doped polysilicon layer of second area; Remove described cover layer.Behind the doped polysilicon layer of removing described second area, remove cover layer again among this embodiment.
After the technology of polysilicon layer thickness that finish the polysilicon layer thickness that reduces second area, makes described second area less than the polysilicon layer thickness of described first area, can mix to the polysilicon layer of described first area and second area, with the resistivity of the polysilicon gate that reduces follow-up formation for example, can mix phosphorus or arsenic as in the polysilicon of N type metal oxide semiconductor transistor gate, in being used as the polysilicon of P-type mos transistor gate, can mix the compound of boron or boron.
Among the embodiment therein, in the polysilicon layer 34c of first area 30a, mix phosphorus or arsenic, in the polysilicon layer 34b of second area 30b, mix the compound of boron or boron.
Step S130, flow chart as shown in Figure 8, the polysilicon layer of graphical described first area and second area forms first grid in described first area, forms second grid at described second area.
Among the embodiment therein, the polysilicon layer of graphical described first area and second area, on described first area, form first grid, comprise in the step that forms second grid on the described second area: on the polysilicon layer of described first area and second area, form anti-reflecting layer; Spin coating photoresist layer on described anti-reflecting layer; Graphical described photoresist layer forms the first grid pattern in the first area, forms the second grid pattern at second area; Etching is removed not by the anti-reflecting layer and the polysilicon layer of described first grid pattern and second grid pattern covers; Remove described first grid pattern, second grid pattern and anti-reflecting layer.
Generalized section as shown in figure 18 forms anti-reflecting layer 38 on the polysilicon layer 34b of the polysilicon layer 34c of described first area 30a and second area 30b, the method that forms described anti-reflecting layer 38 can be a spin-coating method; In a further embodiment, also can on the polysilicon layer 34a of the polysilicon layer 34 of first area 30a shown in Figure 13 and second area, form anti-reflecting layer 38.
Spin coating photoresist layer 40 on described anti-reflecting layer 38.
Generalized section as shown in figure 19, graphical described photoresist layer 40, form first grid pattern 40a at first area 30a, form second grid pattern 40b at second area, described first grid pattern 40a is used for defining at first area 30a the position and the size of first polysilicon gate of follow-up formation; Described second grid pattern 40b is used for defining at second area 30b the position and the size of second polysilicon gate of follow-up formation.
As shown in figure 20, remove not by anti-reflecting layer 38, polysilicon layer 34c and the 34b of described first grid pattern 40a and second grid pattern 40b covering by etching, form the first polysilicon gate 34e at first area 30a, form the second polysilicon gate 34d at second area 30b, the described first polysilicon gate 34e has different thickness (or height) with the second polysilicon gate 34d.
As shown in figure 21, remove described first grid pattern 40a, second grid pattern 40b and anti-reflecting layer 38.
By on polysilicon layer 34c and 34b, forming anti-reflecting layer 38, one side reduces or eliminates the influence of the difference in height at described polysilicon layer 34c top and 34b top to described photoresist layer 40, helps to form the side wall profile first photoresist pattern 40a and the second photoresist pattern 40b preferably; On the other hand, form the sacrifice layer of the first polysilicon gate 34e and the second polysilicon gate 34d as etching, the etching that make to form the described first polysilicon gate 34e and the second polysilicon gate 34d can be finished substantially simultaneously, reduces or eliminates this etching described gate dielectric layer 32 or Semiconductor substrate 30 are caused over etching.
In other embodiments, the polysilicon layer of graphical described first area and second area, form first polysilicon gate in described first area, the step that forms second polysilicon gate at described second area comprises: form metal level on the polysilicon layer of described first area and second area; The described metal level of planarization; Spin coating photoresist layer on described metal level; Graphical described photoresist layer forms the first grid pattern in the first area, forms the second grid pattern at second area; Etching is removed not by the metal level and the polysilicon layer of described first grid pattern and second grid pattern covers; Remove described first grid pattern and second grid pattern.
Generalized section as shown in figure 22 form metal level 42 on the polysilicon layer 34b of the polysilicon layer 34c of described first area 30a and second area 30b, and the described metal level 42 of planarization makes its surface comparatively smooth; Among the embodiment therein, described metal level 42 can be a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, titanium, vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum; Spin coating photoresist layer 44 on described metal level 42.In a further embodiment, also can on the polysilicon layer 34a of the polysilicon layer 34 of first area 30a shown in Figure 13 and second area, form anti-metal level 42.
In other embodiments, before the described photoresist layer 44 of spin coating, can form the anti-reflecting layer (not shown) earlier, and then on described anti-reflecting layer spin coating photoresist layer 44.
Generalized section as shown in figure 23, graphical described photoresist layer 44, form first grid pattern 44a at first area 30a, form second grid pattern 44b at second area, described first grid pattern 44a is used for defining at first area 30a the position and the size of the first grid of follow-up formation; Described second grid pattern 44b is used for defining at second area 30b the position and the size of the second grid of follow-up formation.
As shown in figure 24, remove not the metal level 42, polysilicon layer 34c and the 34b that are covered by described first grid pattern 44a and second grid pattern 44b (if on described metal level 42, be formed with anti-reflecting layer by etching, comprise that then removal is not by the anti-reflecting layer of described first grid pattern 44a and second grid pattern 44b covering), form the first polysilicon gate 34g at first area 30a, form the second polysilicon gate 34f at second area 30b, the described first polysilicon gate 34e has different thickness (or height) with the second polysilicon gate 34d; In addition, this is etched in the described first polysilicon gate 34g and goes up formation metal level 42a, forms metal level 42b on the described second polysilicon gate 34f.
As shown in figure 25, remove described first grid pattern 40a, second grid pattern 40b (, then comprise and remove described anti-reflecting layer) if having anti-reflecting layer on the described metal level 42.
Further, Semiconductor substrate 30 with the described first polysilicon gate 34g and second polysilicon gate 34f is annealed, described metal level 42a can generate the metal silicide (not shown) with the polysilicon reaction at the first polysilicon gate 34g top, and metal level 42a can generate metal silicide with the polysilicon reaction at the second polysilicon gate 34f top.
By on polysilicon layer 34c and 34b, forming metal level 42, one side reduces or eliminates the influence of the difference in height at described polysilicon layer 34c top and 34b top to described photoresist layer 44, helps to form the side wall profile first photoresist pattern 44a and the second photoresist pattern 44b preferably; On the other hand, metal level 42a that forms and 42b can be used as the metal material that forms metal silicide on the described first polysilicon gate 34g and the second polysilicon gate 34f, can generate metal silicide with the polysilicon reaction among the first polysilicon gate 34g and the second polysilicon gate 34f after annealed, simplify processing step, reduced cost.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (13)
1, a kind of manufacture method of semiconductor device is characterized in that, comprising:
Semiconductor substrate with first area and second area is provided;
On described Semiconductor substrate, form polysilicon layer;
Reduce the polysilicon layer thickness of second area, make the polysilicon layer thickness of the polysilicon layer thickness of described second area less than described first area;
The polysilicon layer of graphical described first area and second area forms first grid in described first area, forms second grid at described second area.
2, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, reduces the polysilicon layer thickness of second area, and the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area:
On the polysilicon layer of described first area, form cover layer;
As the barrier layer, the polysilicon layer of the described second area of etching makes the polysilicon layer thickness of its thickness less than described first area with described cover layer;
Remove described cover layer.
3, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, reduces the polysilicon layer thickness of second area, and the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area:
On the polysilicon layer of described first area, form cover layer;
As the barrier layer, the polysilicon layer doping to described second area forms the doped polysilicon layer faster than polysilicon layer etch rate with described cover layer;
Remove described cover layer;
Etching is removed the doped polysilicon layer of second area.
4, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, reduces the polysilicon layer thickness of second area, and the polysilicon layer thickness that makes described second area comprises less than the step of the polysilicon layer thickness of described first area:
On the polysilicon layer of described first area, form cover layer;
As the barrier layer, the polysilicon layer doping to described second area forms the doped polysilicon layer faster than polysilicon layer etch rate with described cover layer;
Etching is removed the doped polysilicon layer of second area;
Remove described cover layer.
5, as the manufacture method of claim 2 or 3 or 4 described semiconductor device, it is characterized in that: described cover layer is a photoresist.
6, as the manufacture method of claim 3 or 4 described semiconductor device, it is characterized in that: the impurity that described doping is mixed is a kind of in phosphorus, the arsenic.
7, the manufacture method of semiconductor device as claimed in claim 6 is characterized in that: the energy of described doping is 1 to 8KeV.
8, the manufacture method of semiconductor device as claimed in claim 6 is characterized in that: the dosage of described doping is 2 * 10
15To 4 * 10
15Cm
-2
9, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the polysilicon layer of graphical described first area and second area forms first grid in described first area, and the step that forms second grid at described second area comprises:
On the polysilicon layer of described first area and second area, form anti-reflecting layer;
Spin coating photoresist layer on described anti-reflecting layer;
Graphical described photoresist layer forms the first grid pattern in the first area, forms the second grid pattern at second area;
Etching is removed not by the anti-reflecting layer and the polysilicon layer of described first grid pattern and second grid pattern covers;
Remove described first grid pattern, second grid pattern and anti-reflecting layer.
10, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the polysilicon layer of graphical described first area and second area forms first grid in described first area, and the step that forms second grid at described second area comprises:
On the polysilicon layer of described first area and second area, form metal level;
The described metal level of planarization;
Spin coating photoresist layer on described metal level;
Graphical described photoresist layer forms the first grid pattern in the first area, forms the second grid pattern at second area;
Etching is removed not by the metal level and the polysilicon layer of described first grid pattern and second grid pattern covers;
Remove described first grid pattern and second grid pattern.
11, the manufacture method of semiconductor device as claimed in claim 10 is characterized in that, this method further comprises: before spin coating photoresist layer on the described metal level, form anti-reflecting layer earlier on described metal level; And after removing described first grid pattern and second grid pattern, remove described anti-reflecting layer.
12, the manufacture method of semiconductor device as claimed in claim 10 is characterized in that, this method further comprises: after removing described first grid pattern and second grid pattern, described Semiconductor substrate is annealed.
13, as the manufacture method of claim 10 or 11 or 12 described semiconductor device, it is characterized in that: the metal material of described metal level comprises a kind of in aluminium, tantalum, molybdenum, zirconium, hafnium, titanium, vanadium, cobalt, palladium, nickel, rhenium, ruthenium, the platinum.
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| CN100576513C CN100576513C (en) | 2009-12-30 |
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| CN102270575A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102456562A (en) * | 2011-09-08 | 2012-05-16 | 上海华力微电子有限公司 | Method for preparing polycrystalline silicon gate with a plurality of thicknesses |
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| CN106233438A (en) * | 2014-04-25 | 2016-12-14 | 丰田自动车株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN108231686A (en) * | 2018-01-10 | 2018-06-29 | 德淮半导体有限公司 | Semiconductor devices and its manufacturing method |
| CN110148560A (en) * | 2019-05-09 | 2019-08-20 | 上海华力微电子有限公司 | A kind of production method of gate structure |
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| CN102270575A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102456562A (en) * | 2011-09-08 | 2012-05-16 | 上海华力微电子有限公司 | Method for preparing polycrystalline silicon gate with a plurality of thicknesses |
| CN106233438A (en) * | 2014-04-25 | 2016-12-14 | 丰田自动车株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN106233438B (en) * | 2014-04-25 | 2019-05-03 | 丰田自动车株式会社 | The manufacturing method and semiconductor device of semiconductor device |
| US10319831B2 (en) | 2014-04-25 | 2019-06-11 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device with a gate electrode positioned in a semiconductor substrate |
| CN105097584A (en) * | 2014-05-15 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Detection method for ion implantation dosage |
| CN105226021A (en) * | 2014-06-26 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108231686A (en) * | 2018-01-10 | 2018-06-29 | 德淮半导体有限公司 | Semiconductor devices and its manufacturing method |
| CN110148560A (en) * | 2019-05-09 | 2019-08-20 | 上海华力微电子有限公司 | A kind of production method of gate structure |
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| Publication number | Publication date |
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