CN101290759B - Method for detecting DVI off-line mode and associated dvi receiver - Google Patents
Method for detecting DVI off-line mode and associated dvi receiver Download PDFInfo
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- CN101290759B CN101290759B CN200810096795.5A CN200810096795A CN101290759B CN 101290759 B CN101290759 B CN 101290759B CN 200810096795 A CN200810096795 A CN 200810096795A CN 101290759 B CN101290759 B CN 101290759B
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Abstract
The invention provides a method of detecting the DVI off-line mode and a related DVI receiver. The DVI receiver comprises a plurality of receiving channels, a clock signal receiving channel and an off-line mode detector. The off-line mode detector further comprises a mode detecting unit, a clock signal detecting unit and a power-off control unit. The clock signal detecting unit is used for detecting if a clock signal is effective, so as to determine if at least one receiving channel need to be turned on in a first predetermined period. The power-off control unit uses the mode detecting unit to judge an operation mode of a video signal. If the operation mode is a non effective mode, the power-off control unit closes all decoders and channels in a second predetermined period. The second predetermined period is much longer than the first predetermined period.
Description
The application is dividing an application of name from June 1st, 2005 to State Intellectual Property Office that propose the application for a patent for invention that is called " digital visual interface off-line mode method for detecting and relevant video frequency interface receiver " application number 200510075751.0.
[technical field]
The present invention relates to a kind of digital visual interface (Digital Visual Interface, DVI), espespecially a kind of digital visual interface off-line mode method for detecting and relevant video frequency interface receiver.
[background technology]
Digital video display device refers to and can receive analog video signal or digital video signal from a signal source (as the video card of computer), and finally convert digital video signal to and be shown in the equipment on screen, liquid crystal display (Liquid Crystal Display, LCD) is exactly a kind of traditional digital video display device.Corresponding with digital video display device is the analog video display device, and cathode-ray tube (CRT) (Cathode Ray Tube, CRT) display is exactly a kind of traditional analog video display device.
Numeral shows work group (Digital Display Working Group, DDWG) announced a kind of being called the industrywide standard of " digital visual interface (Digital Visual Interface; DVI) ", this standard is about the two-forty digital transmission technology of video display signal.Adopt the digital visual interface of this standard to be mainly used in providing the connection with high degree of compatibility between computer (as workstation, desktop computer, notebook computer etc.) and dissimilar display device (as cathode-ray tube display, liquid crystal display, projector etc.).With digital visual interface compatible mainframe system in, both can adopt simple digital interface, also can adopt the analog-digital hybrid interface.
Traditional host computer system and liquid crystal display are digital device in itself.For liquid crystal display, it must be equipped with an analog to digital converter (Analog to Digital Converter, ADC) to convert received analog video signal to digital video signal.On the contrary, for cathode-ray tube display, its video interface must utilize a digital to analog converter (Digital to Analog Converter, DAC) to convert digital signal originally to simulating signal that the analog video display device can be identified.Yet, use digital to analog converter or on liquid crystal display, use analog to digital converter not only to increase the extra cost of equipment on cathode-ray tube display, and, through the repeatedly conversion back and forth between simulating signal and digital signal, will inevitably reduce the quality of vision signal.
Therefore, the digital visual interface that has a whole number Transmission just becomes the main flow of video connection standard.Usually, also comprise a pattern detection circuit in digital video interface system, for continuing the mode of operation of detecting received vision signal by video frequency interface receiver.In digital video interface system, synchronizing signal (Sync) all can be encoded into data crossfire (Data Stream), video frequency interface receiver needs to utilize receiver and code translator to receive respectively synchronizing signal decoding synchronizing signal, then the synchronizing signal after decoding is carried out to mode detecting.Even traditional digital visual interface is when off-line mode (Off-line mode), and only need monitor under the state of input signal without showing any image, also all digital visual interface receive channels can be opened, and the continuous received signal of decoding, then offer pattern detection circuit and go detecting.Above-mentioned traditional pattern detection circuit need to be operated and be gone continually the detection signal pattern to all receive channels, can improve like this power consumption and heat dissipation capacity in circuit.
In view of the foregoing, the invention provides a kind of not only power saving but also digital visual interface off-line mode method for detecting that can elevator system usefulness and relevant video frequency interface receiver.
[summary of the invention]
Fundamental purpose of the present invention is to provide a kind of digital visual interface off-line mode method for detecting and relevant video frequency interface receiver, effectively to reduce the power consumption of digital video interface system, and elevator system usefulness.
For achieving the above object, the present invention adopts following technical scheme: the invention provides a kind of digital visual interface off-line mode method for detecting and relevant video frequency interface receiver, video frequency interface receiver comprises a plurality of receive channels, a clock signal receiving cable and an off-line mode detector, and each receive channel has a code translator and carries out decoding in order to the signal to received from corresponding receive channel; The off-line mode detector comprises mode detecting unit, clock signal detecting unit and outage control module.The clock signal detecting unit is in order to detect the pattern of clock signal, whether to determine opening at least one receive channel in the first period interval; The outage control module can go to detect and judge via the mode detecting unit operator scheme of vision signal, and when operator scheme is detected as non-effective pattern, the outage control module can be closed all code translators and channel in second phase interval.Usually, second phase interval than first period interval much longer.
Compared with prior art, digital visual interface off-line mode method for detecting of the present invention does not need continuously to detect the pattern of vision signal, but the only detecting of settling signal pattern within a shorter detecting time, all the other times are all in off-line mode, can reduce like this running time of digital video interface system (as digital video interface chip), thereby reduce the power consumption of chip.Short and low characteristics of power consumption of running time can make the life-span of digital visual interface chip and stability significantly improve.
[accompanying drawing explanation]
Fig. 1 is the functional-block diagram of the better embodiment of digital video interface system of the present invention, and this digital video interface system comprises video frequency interface receiver, and this video frequency interface receiver comprises the off-line mode detector.
Fig. 2 is the functional-block diagram of another embodiment of digital video interface system of the present invention, and this digital video interface system comprises video frequency interface receiver.
Fig. 3 is the process flow diagram of digital visual interface off-line mode method for detecting of the present invention.
Fig. 4 is a schematic diagram, in order to the distribution condition of channel opening time and channel off time in digital visual interface off-line mode detecting process to be described.
[embodiment]
Refer to shown in Fig. 1, Fig. 1 is the functional-block diagram of digital visual interface of the present invention (Digital Visual Interface, DVI) system 1.This digital video interface system 1 comprises digital visual interface transmitter 20, video frequency interface receiver 40 and crystal oscillator (Crystal Oscillator, XTAL) 70.In better embodiment of the present invention, a plurality of different signal that video frequency interface receiver 40 sends for receiving digital video interface transmitter 20, as: horizontal-drive signal (Horizontal Synchronization signal, HSYNC signal), vertical synchronizing signal (Vertical Synchronization signal, VSYNC signal), show enable signal (Display Enablesignal, DE signal), clock signal (Clock signal, CLK signal) and pixel data signal (Pixel Data signal) etc.
Digital visual interface transmitter 20 comprises a plurality of scramblers and a plurality of transmitting channel.As shown in Figure 1, the clock signal transmitting channel is used for to video frequency interface receiver 40 tranmitting data register signals.Simultaneously, horizontal-drive signal, vertical synchronizing signal, demonstration enable signal and pixel data signal are sent through n# transmitting channel (integer that wherein, n is from 0 to 5) by digital visual interface transmitter 20.
On the other hand, video frequency interface receiver 40 comprises a plurality of receive channels, the unlike signal sent for receiving above-mentioned transmitting channel.For example, the 0# receive channel is for receiving the signal that the 0# transmitting channel sends, and the 1# receive channel is for receiving the signal that the 1# transmitting channel sends, and the clock signal receive channel is used for the clock signal that receive clock signal transmitting channel sends.Each n# receive channel includes the n# code translator of a correspondence, for the signal to received from corresponding receive channel, carries out decoding.For example, the 0# code translator carries out decoding to the signal received from the 0# receive channel, and the 1# code translator carries out decoding to the signal received from the 1# receive channel, and the rest may be inferred.The 0# code translator all can be exported horizontal-drive signal, vertical synchronizing signal, demonstration enable signal and the pixel data signal after decoding to the 5# code translator.Crystal oscillator 70 is used to provide reference clock signal.
Video frequency interface receiver 40 also comprises off-line mode detector 10, and this off-line mode detector comprises again mode detecting unit 12, clock signal detecting unit 14 and outage control module 16.At first, clock signal detecting unit 14 is from clock signal receive channel receive clock signal, then judge that whether this clock signal is effective and normal, for example, the variation that can in a predetermined period, roughly calculate clock signal, to judge that this clock signal is whether in predetermined frequency range (as: 25MHz～165MHz).If clock signal is effective and normal, the control module 16 that cuts off the power supply can be opened 0# receive channel and 0# code translator, the 0# receive channel can receive the signal transmitted from the 0# transmitting channel, then sends to the 0# code translator to carry out decoding, and therefrom decoding goes out horizontal-drive signal and vertical synchronizing signal.Otherwise, in above-mentioned detecting process, once clock signal detecting unit 14 detecting, less than normal clock signal, is cut off the power supply control module 16 will be in the one section schedule time interval " shut " mode" detecting unit 12 and all receive channels, to save power consumption.
Once the 0# receive channel is unlocked, horizontal-drive signal after decoding on the 0# receive channel that mode detecting unit 12 can detect according to it and the state of vertical synchronizing signal judge its operator scheme, so as within one very short period (as: 100 milliseconds) read level synchronizing signal and vertical synchronizing signal.If horizontal-drive signal and vertical synchronizing signal are all effective and normal, the control module 16 that cuts off the power supply can maintain the opening of 0# receive channel, and can determine whether further open other receive channel according to display mode and display frequency.Wherein, display mode can show line number or calculate display pixel and decide according to calculating.Include six transmitting channels and six receive channels in digital video interface system 1, wherein, 0# is respectively used to receive and dispatch the vision signal of three kinds of colors of red, green, blue to the 2# receive channel.In the situation that low resolution, for example resolution is less than 1280 * 1024, and display frequency is during lower than 60Hz, only need to use 0# transmits vision signal to the 2# receive channel, therefore 16 of the control modules that cut off the power supply need to open 0# and close other receive channel to the 2# receive channel, thereby reach the purpose of power saving.For example, otherwise, in the situation that high-resolution, resolution is 1600 * 1200, and display frequency is while being 70Hz, and outage control module 16 can be opened all 0# to the 5# receive channel.
If mode detecting unit 12 does not detect effective and normal horizontal-drive signal and vertical synchronizing signal, even if clock signal detecting unit 14 has detected correct clock signal, outage control module 16 still can closeall receive channel, enters one period power saving cycle.In better embodiment, mode detecting unit 12 judges that by the pattern of detecting 0# receive channel whether vision signal is effective and normal.But need to pay special attention to, mode detecting unit 12 also can remove to detect other receive channel according to top disclosed method according to actual needs, thereby judge that whether the vision signal on this channel is effective and normal herein; For instance, the demonstration enable signal on any receive channel can be detected in mode detecting unit 12, but not can only detect horizontal-drive signal and vertical synchronizing signal on the 0# receive channel.The general skill personage in this field can understand by the demonstration enable signal on any receive channel and carries out digital processing, the same with vertical synchronizing signal with the detecting horizontal-drive signal, also can obtain the information of vision signal; Mode detecting unit 12 and clock signal detecting unit 14 send to outage control module 16 by the information of the vision signal that detects, outage control module 16 sends controls respectively 0# to the 0# of 5# receive channel to the 5# control signal channel, to respond received video signal information.
Whether judgment model effectively and normally can utilize the information that will receive and the information inquiry table (not shown) of a preload to compare to learn, several relevant informations effective and normal mode have been recorded in the information inquiry table, as frequency, display resolution and the display frequency etc. of clock signal, but be not limited only to these information; And, when mode detecting unit 12 does not detect effective and normal horizontal-drive signal and vertical synchronizing signal, outage control module 16 can be closed the clock signal receive channel in above-mentioned schedule time interval.
Fig. 2 has disclosed another embodiment of digital video interface system 1 ' of the present invention, with above-mentioned better embodiment, compares, and difference is that digital video interface system 1 ' further comprises micro-control unit (Micro Controller Unit, MCU) 60 '.Micro-control unit 60 ' is in order to the running of the mode detecting unit 12 ' in control figure video interface receiver 40 ', clock signal detecting unit 14 ' and outage control module 16 '; Micro-control unit 60 ' can quit work off-line mode detector 10 ' according to user instruction, for example, if the user is provided with the standby stand-by period, when the standby stand-by period arrives, just micro-control unit 60 ' can be closed video frequency interface receiver 40 '.
In the present invention, off-line mode detector 10 ' can periodically judge by detecting horizontal-drive signal, vertical synchronizing signal, demonstration enable signal and pixel data signal the operator scheme of digital video signal.Off-line mode detector 10 ' can independently operate, and for example, after detecting the efficient clock signal that digital visual interface transmitter 20 ' sends, clock signal detecting unit 14 ' is periodically detected clock signal; Mode detecting unit 12 ' can further judge according to the detecting result of clock signal detecting unit 14 ' operator scheme of vision signal; Then, outage control module 16 ' determines whether needing to open 0# to the 5# receive channel according to the detecting result of clock signal detecting unit 14 ' and mode detecting unit 12 ' again.Therefore, the whole power consumption of digital video interface system 1 ' of the present invention in the off-line mode detecting can greatly reduce, thereby promotes life-span and the performance of digital video interface system 1 '; In addition, off-line mode detector 10 ' can be controlled by micro-control unit 60 ', thereby can meet user's particular requirement.
Fig. 3 has set forth the method for digital visual interface off-line mode detecting in better embodiment of the present invention, and the method comprises the steps:
Step 100: start the off-line mode detecting.
Step 102: validity and the frequency of detecting clock signal.If the clock signal received from the clock signal receive channel effectively and normally, flow process advances to step 104, otherwise repeating step 102.The detecting time can be 100 milliseconds, two times of the cycle that the time of preferably detecting should be greater than vertical synchronizing signal (as: 40 milliseconds).
Step 104: open the 0# receive channel.
Step 106: validity and the cycle of horizontal-drive signal, vertical synchronizing signal and demonstration enable signal on detecting 0# receive channel.If above-mentioned vision signal effectively and normally, flow process advances to step 108, otherwise advances to step 110.
Step 108: open several receive channels and make response with the display mode to correct.Flow process advances to step 112.
Step 110: close 0# to 900 milliseconds of 5# receive channels, then be back to step 100.
Step 112: finish.
Refer to shown in Fig. 1 and Fig. 4, Fig. 4 shows the unlatching of the 0# receive channel in digital visual interface off-line mode method for detecting of the present invention and the 0# situation of closing to the 5# receive channel.At first, outage control module 16 is opened the 0# receive channel so that the operator scheme of mode detecting unit 12 judgement 0# receive channel in the special time interval (as: 100 milliseconds) of a section extremely short.If the operator scheme of 0# receive channel judgment result is that effectively and normally, the control module 16 that cuts off the power supply maintains the opening of 0# receive channel, and can optionally open other receive channel.If it is invalid that the operator scheme of 0# receive channel is judged as, the control module 16 that cuts off the power supply is closed one section longer time interval (as: 900 milliseconds) by all receive channels, for reaching better power saving effect, can reduce as much as possible the time for detecting.Because the detecting time that the required detecting time of clock signal (being generally the 1-2 millisecond) is more required than the detecting vision signal is short a lot, therefore can ignore the detecting time of clock signal.
Although in above-mentioned embodiment of the present invention, the channel opening time (detecting time) is set as approximately 100 milliseconds, and the channel off time is set as approximately 900 milliseconds, above-mentioned twice all can be done to adjust according to actual conditions.Usually the detecting time should be greater than two times by the detection signal cycle.For example, the short period of vertical synchronizing signal is 40 milliseconds, and the signal mode detecting time should be greater than 80 milliseconds.
Compared with prior art, digital visual interface off-line mode method for detecting of the present invention does not need continuously to detect the pattern of vision signal, and only need be within the very short detecting time detection signal pattern, can reduce like this running time of digital video interface system (as: digital visual interface chip), thereby reduce the power consumption of chip.For example, under off-line mode, can make power consumption be reduced to original 1/30.Short and low characteristics of power consumption of running time make the life-span of digital visual interface chip and stability significantly improve.
Claims (19)
1. a digital visual interface off-line mode method for detecting, it is characterized in that: the method comprises: the validity of clock signal on detecting clock channel; If clock signal is effective, in the first period interval, opens the first channel, and judge the operator scheme of vision signal on this first channel; If, and the operator scheme of this vision signal is effective, according to the operator scheme of this vision signal, open several channels, wherein said first period interval be approximately 100 milliseconds.
2. digital visual interface off-line mode method for detecting as claimed in claim 1 is characterized in that: the step of described detecting clock signal validity be the detecting clock signal frequency whether effectively and normal.
3. digital visual interface off-line mode method for detecting as claimed in claim 1, it is characterized in that: described vision signal comprises horizontal-drive signal, vertical synchronizing signal and pixel data signal.
4. digital visual interface off-line mode method for detecting as claimed in claim 1, it is characterized in that: described vision signal comprises the demonstration enable signal.
5. digital visual interface off-line mode method for detecting as claimed in claim 1 is characterized in that: the operator scheme of described vision signal decides by the frequency of detecting horizontal-drive signal and vertical synchronizing signal.
6. digital visual interface off-line mode method for detecting as claimed in claim 1, it is characterized in that: the operator scheme of described vision signal decides by the information inquiry table of reference preload.
7. digital visual interface off-line mode method for detecting as claimed in claim 1, it is characterized in that: the operator scheme of described vision signal compares to judge with the information inquiry table respectively by the frequency of the frequency by horizontal-drive signal and vertical synchronizing signal.
8. digital visual interface off-line mode method for detecting as claimed in claim 1, it is characterized in that: the method also comprises if the operator scheme of this vision signal is invalid, enters one period power saving cycle.
9. digital visual interface off-line mode method for detecting as claimed in claim 1, it is characterized in that: the method also comprises if the operator scheme of vision signal is invalid, in second phase interval, close all channels, wherein said second phase interval is approximately 900 milliseconds.
10. a video frequency interface receiver, it is characterized in that: this video frequency interface receiver comprises a plurality of receive channels that are used for receiving video signals, each receive channel comprises a code translator, for to from corresponding receive channel, receiving the vision signal of coming, carrying out decoding; Clock signal receive channel for the receive clock signal; And the off-line mode detector that is electrically connected to clock signal receive channel and those code translators, the validity of this off-line mode detector detecting clock signal, thereby whether determine to open at least one receive channel in the first period interval, wherein said first period interval be approximately 100 milliseconds.
11. video frequency interface receiver as claimed in claim 10 is characterized in that: described off-line mode detector comprises for detecting the mode detecting unit of vision signal operator scheme; For detecting the clock signal detecting unit of clock signal validity; And the outage control module that is electrically connected to mode detecting unit and clock signal detecting unit; Wherein, the operator scheme of vision signal on the receive channel that outage control module enable mode detecting unit is unlocked with judgement, when operator scheme is judged as when invalid, the outage control module can be closed all code translators and all receive channels in second phase interval, and wherein said second phase interval is approximately 900 milliseconds.
12. video frequency interface receiver as claimed in claim 10 is characterized in that: described off-line mode detector comprises: for detecting the mode detecting unit of vision signal operator scheme; For detecting the clock signal detecting unit of clock signal validity; And the outage control module that is electrically connected to mode detecting unit and clock signal detecting unit; The off-line mode detector is electrically connected to a microcontroller, the operator scheme of the vision signal on this microprocessor controls mode detecting unit receive channel that detecting is unlocked in the first period interval, when this operator scheme is judged as when invalid, the off-line mode detector can notify the outage control module to close all code translators and all receive channels in second phase interval.
13. video frequency interface receiver as claimed in claim 10 is characterized in that: described vision signal comprises horizontal-drive signal, vertical synchronizing signal and pixel data signal.
14. video frequency interface receiver as claimed in claim 10 is characterized in that: described vision signal comprises the demonstration enable signal.
15. video frequency interface receiver as claimed in claim 10 is characterized in that: the validity of described clock signal refers to that whether the frequency of this clock signal is normal.
16. video frequency interface receiver as claimed in claim 10 is characterized in that: the operator scheme of described vision signal refers to display resolution and the display frequency of this vision signal.
17. video frequency interface receiver as claimed in claim 10 is characterized in that: described mode detecting unit judges the operator scheme of vision signal by the frequency of detecting horizontal-drive signal and vertical synchronizing signal.
18. video frequency interface receiver as claimed in claim 11 is characterized in that: described first period interval be not less than two times of vertical synchronizing signal cycle.
19. video frequency interface receiver as claimed in claim 11 is characterized in that: described mode detecting unit judges the operator scheme of vision signal by the mode of calculating pixel.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US57602504P | 2004-06-02 | 2004-06-02 | |
| US60/576,025 | 2004-06-02 | ||
| US11/055,691 | 2005-02-11 | ||
| US11/055,691 US20060190632A1 (en) | 2005-02-11 | 2005-02-11 | Method for detecting DVI off-line mode and associated DVI receiver |
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| CNB2005100757510A Division CN100399413C (en) | 2004-06-02 | 2005-06-01 | Digital video frequency interface off line mode detecting method and related digital video frequency interface receiver |
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| CN101290759A CN101290759A (en) | 2008-10-22 |
| CN101290759B true CN101290759B (en) | 2014-01-01 |
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| CN200810096795.5A Active CN101290759B (en) | 2004-06-02 | 2005-06-01 | Method for detecting DVI off-line mode and associated dvi receiver |
| CNB2005100757510A Active CN100399413C (en) | 2004-06-02 | 2005-06-01 | Digital video frequency interface off line mode detecting method and related digital video frequency interface receiver |
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| CN1304237A (en) * | 2000-01-13 | 2001-07-18 | 日本电气株式会社 | Frame synchronous testing circuit |
| CN1322979A (en) * | 2000-05-15 | 2001-11-21 | 明碁电脑股份有限公司 | Power saving method and device for screen of computer system |
| CN1523875A (en) * | 2002-12-06 | 2004-08-25 | Lg电子株式会社 | Apparatus and method for outputting video data |
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| JPH09146503A (en) * | 1992-07-29 | 1997-06-06 | Matsushita Electric Ind Co Ltd | Control method for protecting display surface of display and its device |
| JP3754635B2 (en) * | 2001-07-17 | 2006-03-15 | Ｎｅｃディスプレイソリューションズ株式会社 | Display monitor input channel switching control device and display monitor input channel switching control method |
| US7120203B2 (en) * | 2002-02-12 | 2006-10-10 | Broadcom Corporation | Dual link DVI transmitter serviced by single Phase Locked Loop |
| US7408993B2 (en) * | 2002-03-15 | 2008-08-05 | Gennum Corporation | Digital communication extender system and method |
| JPWO2004107746A1 (en) * | 2003-05-28 | 2006-07-20 | 松下電器産業株式会社 | Digital interface decoding receiver |
| JP2005109912A (en) * | 2003-09-30 | 2005-04-21 | Seiko Epson Corp | Digital broadcasting receiver |
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- 2005-06-01 CN CN200810096795.5A patent/CN101290759B/en active Active
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1304237A (en) * | 2000-01-13 | 2001-07-18 | 日本电气株式会社 | Frame synchronous testing circuit |
| CN1322979A (en) * | 2000-05-15 | 2001-11-21 | 明碁电脑股份有限公司 | Power saving method and device for screen of computer system |
| CN1523875A (en) * | 2002-12-06 | 2004-08-25 | Lg电子株式会社 | Apparatus and method for outputting video data |
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| CN1722217A (en) | 2006-01-18 |
| CN100399413C (en) | 2008-07-02 |
| CN101290759A (en) | 2008-10-22 |
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