CN101286477A - Semiconductor component and its manufacturing method - Google Patents
Semiconductor component and its manufacturing method Download PDFInfo
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- CN101286477A CN101286477A CNA2007100965122A CN200710096512A CN101286477A CN 101286477 A CN101286477 A CN 101286477A CN A2007100965122 A CNA2007100965122 A CN A2007100965122A CN 200710096512 A CN200710096512 A CN 200710096512A CN 101286477 A CN101286477 A CN 101286477A
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Abstract
The invention relates to a manufacturing method for a semiconductor element; the method comprises the following steps: firstly, a base is provided and comprises a high-voltage element region and a low-voltage element region, the high-voltage element region is provided with a source/drain predetermined region, a contact predetermined region and a channel predetermined region, and a first dielectric layer is formed on the base; then the first dielectric layer of the low-voltage element region is removed, and at the same time, the first dielectric layers of the source/drain predetermined region and the contact predetermined region of the high-voltage element region are removed together; then a second dielectric layer is formed on the low-voltage element region, wherein, the thickness of the second dielectric layer is less than that of the first dielectric layer; then a grid electrode is respectively formed on the channel predetermined region and the low-voltage element region, and then a source/drain region is formed in the base of the source/drain predetermined region.
Description
Technical field
The present invention relates to a kind of integrated circuit structure and manufacture method thereof, relate in particular to a kind of semiconductor element and manufacture method thereof.
Background technology
Along with the fast development of integrated circuit fields, high-effect, high integration, low cost, the compact design of electronic products that become are made institute's pursuing target.For present semiconductor industry,, often need on same chip, produce the element of multiple function in order to meet above-mentioned target.
High voltage device and low voltage component are incorporated on the same chip, and for example system single chip (system onchip is called for short SOC) is a kind of method that can reach above-mentioned requirements.Yet in order to bear higher puncture voltage (breakdown voltage), the thickness of gate oxide tends to far be thicker than the thickness of gate oxide in the low voltage component in the high voltage device.In such event, all difficult problems appear with making in the middle of the integrated process of high voltage device and low voltage component.
For in response to the different demand of gate oxide thickness, the general practice is to form a whole layer thickness earlier approximately greater than the high voltage grid oxidation layer of 300 dusts, utilizes the etched mode of photoetching then, removes the high voltage grid oxidation layer of low voltage component district part.Afterwards, form the low pressure gate oxide in low voltage component district again.And, because high voltage grid oxidation layer can be covered in predetermined zone of carrying out the ion injection in the high voltage device district equally, locate as source/drain regions, wellblock contact doped region etc., therefore, concentration, the degree of depth and profile for the ease of the injection of control ion, often need again to remove the high voltage grid oxidation layer on these zones with another road photoengraving carving technology.The photomask number that this kind method needs is many, not only can elongate the complexity of manufacturing process, increase technology, also can improve manufacturing cost.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of semiconductor element, utilize, when removing low voltage component district upper dielectric layer, remove in the lump in the high voltage device district, the predetermined dielectric layer that forms on source/drain regions and the wellblock contact doped region with technology.
The present invention proposes a kind of semiconductor element, in the high voltage device district, and set dielectric layer in the substrate of predetermined formation doped region, rough identical with the gate dielectric layer in the low voltage component district, the technology that helps follow-up dopant to inject.
The present invention proposes a kind of manufacture method of semiconductor element, provide substrate, substrate to comprise high voltage device district and low voltage component district earlier, and the high voltage device district has source/drain fate, contact fate and raceway groove fate.In substrate, form one deck first dielectric layer.Then, remove first dielectric layer in low voltage component district, simultaneously, remove first dielectric layer of source/drain fate, contact fate in the lump.Then, form one deck second dielectric layer in the low voltage component district to being less than, wherein the thickness of second dielectric layer is less than the thickness of first dielectric layer.Then, in raceway groove fate and low voltage component district, form grid respectively, then, in the substrate of source/drain fate, form source/drain regions.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein, second dielectric layer also comprises in the substrate that is formed at source/drain fate and contact fate.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein the formation method of second dielectric layer comprises thermal oxidation method.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein remove first dielectric layer in low voltage component district, simultaneously, the method that removes first dielectric layer of source/drain fate, contact fate in the lump for example is prior to forming one deck patterning photoresist layer on first dielectric layer, exposing first dielectric layer of low voltage component district, source/drain fate and contact fate.Remove first dielectric layer and the patterning photoresist layer that expose again.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element also is included in and removes before first dielectric layer that exposes, and carries out an ion implantation technology.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element wherein, before forming first dielectric layer, has been formed with a plurality of isolation structures in the substrate, separate high voltage device district and low voltage component district.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein, the high voltage device district comprises a N type element region and a P type element region.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein, these isolation structures are a plurality of shallow slot isolation structures, separate N type element region, P type element region and low voltage component district.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein, these isolation structures are a plurality of field oxides, separate N type element region, P type element region and low voltage component district, and these field oxides also comprise separation source/drain fate, contact fate and raceway groove fate.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein the formation method of first dielectric layer comprises thermal oxidation method.
In one embodiment of this invention, the manufacture method of above-mentioned semiconductor element, wherein, the material of grid comprises doped polycrystalline silicon.
The present invention proposes a kind of semiconductor element, has comprised substrate, high voltage transistor, high pressure wellblock, wellblock contact doped region, low voltage transistor and dielectric layer.Substrate has high voltage device district and low voltage component district.High voltage transistor is arranged in the substrate in high voltage device district, and high voltage transistor comprises a high pressure gate dielectric layer and a grid that from bottom to top piles up setting, and the source that is arranged at the grid both sides.The high pressure wellblock is arranged in the substrate in high voltage device district.Wellblock contact doped region then is arranged in the substrate of high pressure wellblock.Low voltage transistor is arranged in the substrate in low voltage component district, and low voltage transistor comprises low pressure gate dielectric layer and the grid that from bottom to top piles up setting.Dielectric layer is arranged in the substrate of source/drain regions and wellblock contact doped region, and the thickness of low pressure gate dielectric layer is less than the thickness of high pressure gate dielectric layer, and dielectric layer equates with the thickness of low pressure gate dielectric layer is rough.
In one embodiment of this invention, above-mentioned semiconductor element, wherein dielectric layer and low pressure gate dielectric layer are formed in same step.
In one embodiment of this invention, above-mentioned semiconductor element, wherein the formation method of dielectric layer and low pressure gate dielectric layer comprises thermal oxidation method.
In one embodiment of this invention, above-mentioned semiconductor element wherein is provided with a plurality of isolation structures in the substrate, separates high voltage device district and low voltage component district.
In one embodiment of this invention, above-mentioned semiconductor element, the high voltage device district comprises a N type element region and a P type element region.
In one embodiment of this invention, above-mentioned semiconductor element, wherein, these isolation structures are a plurality of shallow slot isolation structures, separate N type element region, P type element region and low voltage component district.
In one embodiment of this invention, above-mentioned semiconductor element, wherein, these isolation structures are a plurality of field oxides, separate N type element region, P type element region and low voltage component district, and these field oxides also comprise separation grid, source/drain regions and wellblock contact doped region.
Semiconductor element provided by the invention and manufacture method thereof, can reduce the required photomask number of technology, in with photomask, remove the dielectric layer in the low voltage component district in the lump, and the subregional dielectric layer in top, high voltage device district, and need not before forming doped region, utilize another road photomask again, remove the part dielectric layer in the high voltage device district.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process profile that illustrates a kind of semiconductor element of one embodiment of the invention.
The main element symbol description
100: substrate
102: the high voltage device district
104: the low voltage component district
102a: source/drain fate
102b: contact fate
102c: raceway groove fate
112a: high pressure P well
112b: high pressure N well
114a: low pressure P well
114b: low pressure N well
The progressive district of 116a:N type
116b:N type drift region
116c:N type channel doping district
The progressive district of 118a:P type
118b:P type drift region
118c:P type channel doping district
120: isolation structure
130,140b: dielectric layer
135: the high pressure gate dielectric layer
140a: dielectric layer (low pressure gate dielectric layer)
150: high voltage transistor
151,161: grid
153,163: clearance wall
155,165: source/drain regions
157: and distinguish the contact doped region
160: low voltage transistor
Embodiment
Figure 1A to Fig. 1 D is the manufacture method of a kind of semiconductor element of one embodiment of the invention.
Please refer to Figure 1A, this manufacture method for example is that substrate 100 is provided earlier, and substrate 100 includes high voltage device district 102 and low voltage component district 104, and high voltage device district 102 has source/drain fate 102a, contact fate 102b and raceway groove fate 102c.Substrate 100 for example is a silicon base, in the substrate 100 in high voltage device district 102 for example is to be formed with high pressure P well 112a and high pressure N well 112b, with the wellblock as follow-up N transistor npn npn and P transistor npn npn.The dopant of high pressure P well 112a for example is P type dopants such as boron or boron difluoride.The dopant of high pressure N well 112b for example is N type dopants such as arsenic ion or phosphonium ion.For example be to be formed with low pressure P well 114a and low pressure N well 114b equally in the substrate 100 in low voltage component district 104.
In one embodiment, also be formed with a plurality of isolation structures 120 in the substrate 100, separate high voltage device district 102 and low voltage component district 104, isolation structure 120 also is used for separating high pressure P well 112a and the high pressure N well 112b in the high voltage device district 102.Isolation structure 120 for example is shallow slot isolation structure or field oxide, and its material is an insulating material, and it for example is a silica.Known as for its formation method by being familiar with this area person, seldom give unnecessary details in this.
In the present embodiment, isolation structure 120 for example is a field oxide, and it not only is used for isolating adjacent transistors, source/drain fate 102a, contact fate 102b and the raceway groove fate 102c in high voltage device district 102 can also be kept apart.
In addition, because the transistor in the high voltage device district 102 need bear bigger voltage, for fear of electric leakage or undesired conducting because of high pressure produced, in the 102a of the source/drain fate of high pressure P well 112a, also can form N type progressive (grade) district 116a, N type drift (drift) district 116b, in the 102c of the raceway groove fate of high pressure P well 112a, form N type channel doping district 116c.In addition, in the source/drain fate 102a of high pressure N well 112b, then form P type progressive (grade) district 118a, P type drift (drift) district 118b, and in the raceway groove fate 102c of high pressure N well 112b, form P type channel doping district 118c.
Please continue with reference to Figure 1A, in substrate 100, form one dielectric layer 130.The material of dielectric layer 130 for example is a silica, and its formation method for example is thermal oxidation method or chemical vapour deposition technique.
Then, please refer to Figure 1B, remove the dielectric layer 130 in low voltage component district 104, simultaneously, remove the dielectric layer 130 of source/drain fate 102a, contact fate 102b in the lump, in the substrate 100 of raceway groove fate 102c, to define one deck high pressure gate dielectric layer 135.The method that removes these regional dielectric layers 130 for example is prior to forming one deck patterned mask layer (not illustrating) in the substrate 100, expose low voltage component district 104, source/drain fate 102a and contact fate 102b, utilize wet etching or dry-etching method to remove the dielectric layer 130 that exposes then, then delustering with wet type causes resist or dry type and delusters and cause resist and remove patterning photoresist layer.
Then, please continue with reference to Figure 1B, form one dielectric layer 140a in the low voltage component district 104 to being less than, this layer dielectric layer 140a is exactly the usefulness as the low pressure gate dielectric layer of low voltage component, and the thickness of dielectric layer 140a is less than the thickness of dielectric layer 130.In one embodiment, the thickness of dielectric layer 140a for example is 40～100 dusts.With the about 3 volts low voltage component of grid voltage, thickness commonly used for example is 65 dusts.The material of dielectric layer 140a for example is a silica, and its formation method for example is a thermal oxidation method.Because the dielectric layer 130 of source/drain fate 102a, contact fate 102b removes suddenly in previous step, expose these regional substrates 100, therefore, in the process of thermal oxidation method, also can form one dielectric layer 140b simultaneously in the substrate 100 of source/drain fate 102a and contact fate 102b.
Afterwards, please refer to Fig. 1 C, in the substrate 100 in raceway groove fate 102c and low voltage component district 104, form grid 151 and grid 161 respectively.The material of grid 151,161 for example is a doped polycrystalline silicon, its formation method for example is to form earlier the conformal doped polysilicon layer (not illustrating) of one deck, and then carries out the photoengraving carving technology to form.Wherein, doped polysilicon layer for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step with what form, and the mode that can certainly adopt original position to inject dopant forms with chemical vapour deposition technique.
After forming grid 151,161, can also form clearance wall 153,163 at grid 151,161 sidewalls, the material of clearance wall 153,163 for example is the dielectric material of silica and so on, its formation method for example is to form one deck spacer material layer (not illustrating) earlier in substrate 100, carry out isotropic etching then, remove part spacer material layer, to form the clearance wall 153,163 of gate lateral wall.In order to increase conductivity, can also form metal silicide (not illustrating) on the grid 151,161, as tungsten silicide.
Subsequent, please refer to Fig. 1 D, carry out the dopant injection technology, in the substrate 100 of source/drain regions fate 102a, to form source/drain regions 155 and wellblock contact doped region 157.Wherein, the position of source/drain regions 155 for example is to have at least and overlap with previous progressive district (116a, 118a).For example be the transistor that is formed with different conductivity types in the substrate 100 in high voltage device district 102, on high pressure P well 112a, can form the N transistor npn npn, on high pressure N well 112b, can form the P transistor npn npn.
In one embodiment, for example be to carry out P type ion implantation technology earlier one, in high pressure N well 112b, form the source/drain regions 155 of P type, in high pressure P well 112a, form the wellblock contact doped region 157 of P type.Certainly, also can form the source/drain regions 165 of P type among the low pressure N well 114b in the lump.
Carry out N type ion implantation technology afterwards one, in high pressure P well 112a, form the source/drain regions 155 of N type, in high pressure N well 112b, form the wellblock contact doped region 157 of N type.Certainly, also can form the source/drain regions 165 of N type among the low pressure P well 114a in the lump.As for the step of follow-up formation contact hole and wellblock contact (pick-up), known by knowing this skill person, do not give unnecessary details in this.
Because the dielectric layer 130 that originally is formed on source/drain fate 102a and the contact fate 102b has been removed in the dielectric layer 130 that removes low voltage component district 104, therefore, before carrying out above-mentioned ion implantation technology, needn't re-use another road photo-marsk process to open these zones.Formed doped region concentration and profile also can be subjected to good control.In other words, the manufacture method of the semiconductor element of present embodiment can be saved one photomask and be shortened manufacturing process, and reduces manufacturing cost, in addition, also helps the control of follow-up dopant injection technology.
A kind of semiconductor element of one embodiment of the invention below is described.
Please refer to Fig. 1 D, this semiconductor element comprises substrate 100, high pressure wellblock, high voltage transistor 150, wellblock contact doped region 157, low voltage transistor 160 and dielectric layer 140b.
Source/drain regions 155 for example is N type doped region or P type doped region.Source/drain regions 155 among the high pressure P well 112a is a N type doped region, and it for example is that to contain concentration be 1 * 10
15The arsenic ion of/cubic centimetre or the dopant of phosphonium ion, the high voltage transistor 150 that is arranged on the high pressure P well 112a is the transistor of N type.Source/drain regions 155 among the high pressure N well 112b is a P type doped region, and it for example is that to contain concentration be 1 * 10
15The boron ion of/cubic centimetre, the high voltage transistor 150 that is arranged on the high pressure N well 112b is the transistor of P type.
Among the high pressure wellblock (high pressure P well 112a and high pressure N well 112b), also being provided with wellblock contact doped region 157, according to different conductivity types wellblock, and is the wellblock contact doped region 157 of P type or N type.
For example be to be provided with low pressure wellblock (low pressure P well 114a and low pressure N well 114b) in the substrate 100 in low voltage component district 104.Low voltage transistor 160 is provided with in the substrate 100 of low pressure wellblock.Low voltage transistor 160 includes low pressure gate dielectric layer 140a and the grid 161 that from bottom to top piles up setting, and the source/drain regions 165 in the low pressure wellblock of grid 161 both sides.The thickness of low pressure gate dielectric layer 140a is less than the thickness of high pressure gate dielectric layer 135, and it for example is between 40～100 dusts, for example is 65 dusts.
Be provided with isolation structure 120 between high voltage device district 102 and the low voltage component district 104.Isolation structure 120 for example is field oxide or shallow slot isolation structure, and its material for example is a silica.Isolation structure 120 can also be arranged in the substrate 100 in high voltage device district 102, isolated high-voltage P well 112a and high pressure N well 112b.In one embodiment, also can be provided with the isolation structure 120 of field oxide between the source/drain regions 155 in high voltage device district 102, grid 151, the wellblock contact doped region 157.
In sum, in the foregoing description, utilize, low voltage component district 104 is removed in the lump with the source/drain fate 102a in high voltage device district 102, the dielectric layer 130 on the 102b of contact fate with photomask.Therefore, before the step of follow-up formation doped region (source/drain regions 155, wellblock contact doped region 157), need not be again with another road photomask, the source/drain fate 102a in high voltage device district 102, the dielectric layer 130 on the 102b of contact fate are removed, and can directly be carried out the step that dopant injects.Thus, not only can reduce manufacturing cost, shorten manufacturing process, also can obtain better grasp for follow-up dopant profile and concentration.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (17)
1. the manufacture method of a semiconductor element comprises:
Substrate is provided, and this substrate comprises high voltage device district and low voltage component district, and this high voltage device district comprises source/drain fate, contact fate and raceway groove fate;
In this substrate, form first dielectric layer;
Remove this first dielectric layer in this low voltage component district, simultaneously, remove this first dielectric layer of this source/drain fate, this contact fate in the lump;
Form second dielectric layer in this low voltage component district to being less than, wherein the thickness of this second dielectric layer is less than the thickness of this first dielectric layer;
In this raceway groove fate and this low voltage component district, form grid respectively; And
In this substrate of this source/drain fate, form source/drain regions.
2. the manufacture method of semiconductor element as claimed in claim 1, wherein this second dielectric layer also comprises in this substrate that is formed at this source/drain fate and this contact fate.
3. the manufacture method of semiconductor element as claimed in claim 1, wherein the formation method of this second dielectric layer comprises thermal oxidation method.
4. the manufacture method of semiconductor element as claimed in claim 1 wherein removes this first dielectric layer in this low voltage component district, and simultaneously, the method that removes this first dielectric layer of this source/drain fate, this contact fate in the lump comprises:
On this first dielectric layer, form patterning photoresist layer, expose this first dielectric layer of this low voltage component district, this source/drain fate and this contact fate;
Remove this first dielectric layer that exposes; And
Remove this patterning photoresist layer.
5. the manufacture method of semiconductor element as claimed in claim 1 also is included in and removes before this first dielectric layer that exposes, and carries out ion implantation technology.
6. the manufacture method of semiconductor element as claimed in claim 1 wherein, before forming this first dielectric layer, has been formed with a plurality of isolation structures in this substrate, separates this high voltage device district and this low voltage component district.
7. the manufacture method of semiconductor element as claimed in claim 6, wherein, this high voltage device district comprises N type element region and P type element region.
8. the manufacture method of semiconductor element as claimed in claim 7, wherein, those isolation structures are a plurality of shallow slot isolation structures, separate this N type element region, this P type element region and this low voltage component district.
9. the manufacture method of semiconductor element as claimed in claim 7, wherein, those isolation structures are a plurality of field oxides, separate this N type element region, this P type element region and this low voltage component district, and those field oxides also comprise separation this source/drain fate, this contact fate and this raceway groove fate.
10. the manufacture method of semiconductor element as claimed in claim 1, wherein the formation method of this first dielectric layer comprises thermal oxidation method.
11. a semiconductor element comprises:
Substrate, this substrate comprise high voltage device district and low voltage component district;
The high pressure wellblock is arranged in this substrate in this high voltage device district;
High voltage transistor is arranged in this substrate of this high pressure wellblock, and this high voltage transistor comprises high pressure gate dielectric layer and the grid that from bottom to top piles up setting, and is arranged at the source/drain regions in the high pressure wellblock of these grid both sides;
Wellblock contact doped region is arranged in this substrate of this high pressure wellblock;
Low voltage transistor is arranged in this substrate in this low voltage component district, and this low voltage transistor comprises the low pressure gate dielectric layer at least; And
Dielectric layer is arranged in this substrate of this source/drain regions and this wellblock contact doped region,
Wherein, the thickness of this low pressure gate dielectric layer is less than the thickness of this high pressure gate dielectric layer, and this dielectric layer equates with the thickness of this low pressure gate dielectric layer is rough.
12. semiconductor element as claimed in claim 11, wherein this dielectric layer and this low pressure gate dielectric layer are formed in same step.
13. semiconductor element as claimed in claim 11, wherein the formation method of this dielectric layer and this low pressure gate dielectric layer comprises thermal oxidation method.
14. semiconductor element as claimed in claim 11 wherein, is provided with a plurality of isolation structures in this substrate, separate this high voltage device district and this low voltage component district.
15. semiconductor element as claimed in claim 14, this high voltage device district comprises N type element region and P type element region.
16. semiconductor element as claimed in claim 15, wherein, those isolation structures are a plurality of shallow slot isolation structures, separate this N type element region, this P type element region and this low voltage component district.
17. semiconductor element as claimed in claim 15, wherein, those isolation structures are a plurality of field oxides, separate this N type element region, this P type element region and this low voltage component district, and those field oxides also comprise separation this grid, this source/drain regions and this wellblock contact doped region.
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| CNB2007100965122A CN100552920C (en) | 2007-04-11 | 2007-04-11 | Semiconductor element and manufacture method thereof |
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| CNB2007100965122A CN100552920C (en) | 2007-04-11 | 2007-04-11 | Semiconductor element and manufacture method thereof |
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| CN101286477A true CN101286477A (en) | 2008-10-15 |
| CN100552920C CN100552920C (en) | 2009-10-21 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214696A (en) * | 2011-05-27 | 2011-10-12 | 上海宏力半导体制造有限公司 | Power MOS (Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
| US10032673B1 (en) | 2017-05-30 | 2018-07-24 | Vanguard International Semiconductor Corporation | Semiconductor devices and methods for manufacturing the same |
| TWI632620B (en) * | 2017-03-20 | 2018-08-11 | 世界先進積體電路股份有限公司 | Semiconductor devices and methods for manufacturing the same |
| CN109887994A (en) * | 2017-12-06 | 2019-06-14 | 南亚科技股份有限公司 | Without junction transistor element and its manufacturing method |
| CN113745161A (en) * | 2021-09-06 | 2021-12-03 | 武汉新芯集成电路制造有限公司 | High-voltage semiconductor device and manufacturing method thereof |
-
2007
- 2007-04-11 CN CNB2007100965122A patent/CN100552920C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214696A (en) * | 2011-05-27 | 2011-10-12 | 上海宏力半导体制造有限公司 | Power MOS (Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN102214696B (en) * | 2011-05-27 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | Power MOS (Metal Oxide Semiconductor) device and power MOS (Metal Oxide Semiconductor) device manufacture method |
| CN103137622A (en) * | 2011-11-28 | 2013-06-05 | 北大方正集团有限公司 | Semiconductor device for high-voltage integrated circuit and preparation method thereof |
| CN103137622B (en) * | 2011-11-28 | 2016-04-06 | 北大方正集团有限公司 | A kind of semiconductor device for high voltage integrated circuit and manufacture method thereof |
| TWI632620B (en) * | 2017-03-20 | 2018-08-11 | 世界先進積體電路股份有限公司 | Semiconductor devices and methods for manufacturing the same |
| US10032673B1 (en) | 2017-05-30 | 2018-07-24 | Vanguard International Semiconductor Corporation | Semiconductor devices and methods for manufacturing the same |
| CN109887994A (en) * | 2017-12-06 | 2019-06-14 | 南亚科技股份有限公司 | Without junction transistor element and its manufacturing method |
| CN113745161A (en) * | 2021-09-06 | 2021-12-03 | 武汉新芯集成电路制造有限公司 | High-voltage semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100552920C (en) | 2009-10-21 |
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