CN101286307B

CN101286307B - Signal processing method

Info

Publication number: CN101286307B
Application number: CN200810096242XA
Authority: CN
Inventors: 权秀现; 李升佑
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2003-08-28
Filing date: 2004-08-30
Publication date: 2010-12-15
Anticipated expiration: 2024-08-30
Also published as: CN101373587B; CN101286308B; CN101373587A; CN101286308A; KR20050023010A; CN101286307A; KR100968568B1

Abstract

The present invention provides a method for processing data in a display device for received image data D(N) of the current Nth frame, including storing old line data D(N-2) of the (N-2)th frame before the current Nth frame in a second frame memory; storing the current first line data D(N)1 in a first line memory of a plurality of line memories; storing the current second line data D(N)2 in a second line memory of a plurality of line memories; writing the D(N)1 into a first frame memory from the first line memory, writing the D(N)2 into the first frame memory from the second line memory; reading a first line data D(N-1)1 and a second line data D(N-1)2 of the current frame (N-1)th frame from the second frame memory, and storing them in a third and a fourth memory, so as to store D(N) and D(N-1) in the first frame memory, as well as to store D(N-1) and D(N-1) in the second frame memory.

Description

Signal processing method

This case be that August 30, application number in 2004 are 200410087453.9 the applying date, denomination of invention divides an application for the application for a patent for invention of " signal handling equipment and method and the display device that comprises signal handling equipment ".

Technical field

The present invention relates to signal handling equipment and method, and the display device that comprises signal process equipment.

Background technology

LCD (LCD) comprises a pair of have panel and the liquid crystal layer with dielectric anisotropy that is arranged between two panels of generating electrode.In liquid crystal layer, form electric field by using electrode, and electric field generates desired images so that the transmittance of liquid crystal layer is passed in control by regulating.LCD equipment comprises that the plane shows (FPD) equipment, and it occurs with the form of TFT-LCD that use is used for the thin film transistor (TFT) (TFT) of pixel control often.

Mainly be used as the TFT-LCD of computer monitor in the past, becoming is used for amusement display screen such as TV screen more.Consequently, for TFT-LCD, show that the high-quality live image has become more important.Yet, because do not use TFT-LCD to show the image of rapid movement traditionally, so need make some improvement to the signal controlling technology in these equipment.At present, liquid crystal molecule can not very react to show pure rapid movement image to the electric field that applies apace.Need certain duration of cost to charge to target voltage to the liquid crystal capacitor.When the difference between target voltage and the previous voltage was big, the longer time of duration that liquid crystal capacitor may spend than expectation reached target voltage." liquid crystal capacitor " refers to the electrode of a pair of generation electric field and is placed in this to the liquid crystal layer between the electrode.

The solution of solution liquid crystal layer duration of charging than long problem is exactly dynamic capacitance compensation (DCC).The DCC method need apply the regulation voltage that is higher than target voltage to liquid crystal capacitor, so that utilize the response time to increase the fact that reduces with the liquid crystal capacitor both end voltage.

Yet, because DCC according to two or three frames relatively judge regulation voltage, so it needs at least one frame memory to come the view data of storage frame.The frame memory demand is that people are undesirable, because it has increased the area of production cost and control panel.

As possibility, can be used as frame memory to DDR (double data rate (DDR)) storer.Yet the DDR storer needs high-frequency data processing speed, and this is not to reach.Therefore, press for a kind of being used in the extra cost that does not need frame memory or image height the judge method of regulation voltage of the situation of the such restrictive condition of processing speed frequently.

Summary of the invention

The present invention includes the method that bit number and frequency by conversion image data reduce the number of required frame storer.In one aspect, the present invention is a kind of signal handling equipment that comprises the display unit of signal processor and frame memory.Signal processor receives current image date with first form and with the current image date after second form generation adjusting, described first form has first bit number and first frequency, and described second form has second form of second bit number and second frequency.Frame memory is with the second form storing image data.The present invention also comprises the display device that comprises above-mentioned signal handling equipment.

In one aspect of the method, the present invention is the method for the data in a kind of processes and displays equipment.Described method need receive the current image date with first bit number and first frequency, and, institute's rheme comes the format conversion current image date by being rearranged into second bit number, first frequency is changed into second frequency, and storage has the current image date of second bit number and second frequency in frame memory.Current image date after the adjusting utilizes current image date to generate.

In a further aspect, the present invention is a kind of signal handling equipment of display unit.Described equipment comprises: signal processor, data output unit and frame memory.Signal processor receives the view data with first data transfer rate and described view data is divided into first subclass of view data and second subclass of view data.View data after the data output unit receives first subclass and second subclass of view data and generates the reorganization with second data transfer rate.Frame memory is stored view data after the reorganization according to first clock rate.

In yet another aspect, the present invention is the signal handling equipment of display unit, and described equipment comprises double data rate (DDR) (DDR) storer, data input cell and signal processor.Described signal processor receives view data and generates first subclass of view data and second subclass of view data from the DDR storer.First subclass of view data and the data transfer rate of second subclass are half of data transfer rate of the view data that receives from storer.Signal processor receives first and second subclass of view data.

Description of drawings

Fig. 1 is the block diagram according to the LCD of the embodiment of the invention;

Fig. 2 is the equivalent circuit diagram according to the LCD pixel of the embodiment of the invention;

Fig. 3 is the block diagram according to the signal handling equipment 40 of the embodiment of the invention;

Fig. 4 is the block diagram of the signal processor of the signal handling equipment shown in Fig. 3;

Fig. 5 for example understands the example waveform of the signal of the signal processor shown in input Fig. 4;

Fig. 6 for example understands the example waveform from the output signal of data converter;

Fig. 7 for example understands the example waveform from the output signal of internal storage and data IOB;

Fig. 8 is the block diagram of signal handling equipment in accordance with another embodiment of the present invention;

Fig. 9 and 10 for example understands the example waveform of the input/output signal of the signal processor shown in Fig. 8 respectively;

Figure 11 for example understands example waveform that read from frame memory or that be written to the view data the frame memory;

Figure 12 and 13 for example understands respectively in the operation example of importing the signal processor shown in N and (N+1) image duration, Fig. 8;

Figure 14 and 15 for example understands another example in the operation of importing the signal processor shown in N and (N+1) image duration, Fig. 8 respectively;

Figure 16 is the block diagram according to the signal handling equipment that comprises the data output unit of an embodiment;

Figure 17 is the signal timing diagram of the element of the signal handling equipment shown in Figure 16;

Figure 18 is the block diagram according to the signal handling equipment that comprises data input cell of embodiment;

Figure 19 is the signal timing diagram of the element of the signal handling equipment shown in Figure 18;

Figure 20 is the block diagram according to the signal handling equipment that comprises the data output unit of other embodiment;

Figure 21 is the signal timing diagram of the element of the signal handling equipment shown in Figure 20;

Figure 22 is the block diagram according to the signal handling equipment that comprises data input cell of other embodiment; With

Figure 23 is the signal timing diagram of the element of the signal handling equipment shown in Figure 22.

Embodiment

Now, describe the present invention with reference to the accompanying drawings in more detail, described accompanying drawing shows the preferred embodiments of the present invention.Yet, can specialize the present invention with many different forms, and should not be interpreted as the embodiment that is limited to here to be set forth to the present invention.

Now, describe signal handling equipment and method with reference to the accompanying drawings in detail according to the embodiment of the invention, and the display device that comprises signal handling equipment.

With reference to the LCD of Fig. 1 and 2 detailed description according to the embodiment of the invention.

Fig. 1 is the block diagram according to the LCD equipment of the embodiment of the invention, and Fig. 2 is the figure of the pixel in the LCD equipment of Fig. 1.

The LCD equipment of Fig. 1 comprises: LC panel assembly 300, and gate drivers (the gate driver) 400 and the data driver 500 that are connected in LC panel assembly 300.The grey voltage generator is connected in data driver 500.Gate drivers 400 and data driver 500 are subjected to the control of signal controller 600.LC panel assembly 300 comprises a plurality of display signal lines that define pixel.Display signal line comprises gate lines G ₁-G _nWith data line D ₁-D _mBasically, pixel is arranged with matrix form.

Gate lines G ₁-G _nSend gating signal (gate signal) (being also referred to as " sweep signal "), and data line D ₁-D _mSend data-signal.Gate lines G ₁-G _nBasically extend parallel to each other.Data line D ₁-D _mBasically extend parallel to each other, and be substantially perpendicular to gate lines G ₁-G _nThe direction of extending is extended.

Each pixel all comprises: be connected in signal wire G ₁-G _nAnd D ₁-D _mOn-off element Q, LC capacitor C _LCWith holding capacitor C _STLC capacitor C _LCWith holding capacitor C _STAll be connected in on-off element Q.In certain embodiments, holding capacitor CST can omit.

Fig. 2 shows below and on-off element Q is provided and has three terminals on the plate 100: be connected in wherein gate lines G ₁-G _nControl terminal, be connected in wherein data line D ₁-D _mInput terminal and be connected in LC capacitor C _LCWith holding capacitor C _STBoth lead-out terminals.

LC capacitor C _LCThe ordinary electrode 270 that the pixel electrode 190 that provides on the lower panel 100 is provided and provides on the plate 200 in the above is with as two terminals.Be placed in 3 Jie LC of the LC layer capacitor C between two

electrodes

190 and 270 _LCThe effect of insulating material.Pixel electrode 190 is connected in on-off element Q, and ordinary electrode 270 is connected in common voltage V _Com, and the whole surface of covering top panel 200.Provide ordinary electrode 270 on the plate 100 below, and

electrode

190 and 270 boths can have the shape of bar shaped or speckle.

Holding capacitor C _STBe LC capacitor C _LCAuxiliary capacitor.Holding capacitor C _STPixel electrode 190 and the independent signal line (not shown) that provides on the plate 100 below are provided.The independent signal line covers above the pixel electrode 190 via insulator, and predetermined voltage such as common voltage Vcom is provided for described independent signal line.As selection, holding capacitor C _ST Comprise pixel electrode 190 and the adjoins gate line (for example, previous gate line) that covers above the pixel electrode 190, and sandwich insulation course between them.

For color display apparatus, each pixel can both be represented a kind of color by one of them that comprises redness, green and blue color filter 230.Color filter 230 is positioned on the pixel electrode 190.Color filter 230 shown in Fig. 2 is provided in the zone of plate 200 in the above.In optional embodiment, color filter 230 be positioned at above the pixel electrode 190 or below, and be the part of lower panel 100.

Although not shown, one or more polarizers (polarizer) are attached at least one panel 100,200.

Return Fig. 1 now, grey voltage generator 800 generates two groups of a plurality of grey voltages relevant with the transmittance of pixel.Grey voltage in one group is with respect to common voltage V _ComHave positive polarity, and the grey voltage in another group is with respect to V _ComHas negative polarity.

Gate drivers 400 is connected in the gate lines G of panel assembly 300 ₁-G _nAnd synthetic gate-on voltage Von and grid cut-off voltage V from external unit _OffBe applied to gate lines G with generation ₁-G _nGating signal.Data driver 500 is connected in the data line D of panel assembly 300 ₁-D _m, and will from the grey voltage that grey voltage generator 800 produces, select data voltage and be applied to data line D ₁-D _m

Signal controller 600 control gate drivers 400 and data driver 500.Signal controller 600 receives received image signal R, G and B and from the control signal of its demonstration of graphics controller (not shown) input control, such as picture vertical synchronizing signal Vsync, horizontal-drive signal Hsync, major clock MCLK and data enable signal DE.After generating gate control signal CONT1 and data controlling signal CONT2 and handling picture signal R, the G and B that is suitable for guidance panel assembly 300 according to input control signal and received image signal R, G and B, signal controller 600 provides gate control signal CONT1 to gate drivers 400, and sends picture signal R ', G ' and B ' and the data controlling signal CONT2 that has handled to data driver 500.At this moment, the image type detecting device 620 of signal controller 600 is judged the type of image according to the difference in the grey of the view data R between previous frame and the present frame, G and B, and for example it is rest image or moving image.Thereafter, signal controller 600 is regulated view data according to image type.

Gate control signal CONT1 comprises: be used to inform that the vertical synchronization start signal STV of the startup of frame, the gated clock signal CPV and being used to that is used to control the output time of gate-on voltage Von define the output enable signal OE of the duration of gate-on voltage Von.

Data controlling signal CONT2 comprises: be used to inform the startup of horizontal cycle horizontal synchronization start signal STH, be used for indication to data line D ₁-D _mApply data voltage load signal LOAD, be used for (with respect to common voltage V _Com) polarity of data voltage is carried out anti-phase anti-phase control signal RVS and data clock signal HCLK.

Data driver 500 receives view data R ', the G ' of pixel column and the grouping of B ' from signal controller 600 theres, and, view data R ', G ' and B ' are converted to the analog data voltage of selecting from the grey voltage that comes from grey voltage generator 800 in response to data controlling signal CONT2 from signal controller 600.Thereafter, data driver 500 is applied to data line D with data voltage ₁-D _m

In response to the gate control signal CONT1 from signal controller 600, gate drivers 400 is applied to gate lines G with gate-on voltage Von ₁-G _n, the on-off element Q that is attached thereto of conducting whereby.To be applied to data line D ₁-D _mOn data voltage after activating on-off element Q and offer pixel.

With data voltage and common voltage V _ComBetween difference be expressed as LC capacitor C _LCTwo ends between voltage, this voltage is sometimes referred to as " pixel voltage ".LC capacitor C _LCIn the LC molecule have the directivity that depends on pixel voltage numerical value, and molecular orientation determines to pass the light polarization of LC the 3rd layer (referring to Fig. 2).Polarizer converts light polarization to the transmittance of certain one-level.

In an image duration, repeat said process by unit (it is represented with 1H, and equals the one-period of horizontal-drive signal Hsync, data enable signal DE and gated clock signal) by horizontal cycle, come sequentially to give all gate lines G ₁-G _nGate-on voltage Von is provided.Therefore, in an image duration data voltage is applied to all pixels whereby.Between frame, control is applied to the anti-phase control signal RVS of data driver 500, so that with the polarity of data voltage anti-phase (this is called " frame is anti-phase ").Also can control anti-phase control signal RVS so that in a frame, will flow into the polarity of the data voltage in the data line anti-phase (this is called " line is anti-phase "), perhaps in a grouping with the polarity of data voltage anti-phase (this is called " dot matrix is anti-phase ").

Now, the signal handling equipment that can use with above-mentioned LCD will be described in detail.

Fig. 3 is the block diagram according to the signal handling equipment 40 of the embodiment of the invention, and Fig. 4 is the block diagram of the signal processor of the signal handling equipment shown in Fig. 3.

As shown in Figure 3, the signal handling equipment 40 according to the embodiment of the invention comprises: signal processor 42 and the frame memory 44 that is attached thereto.The input and output of signal handling equipment 40 are served as in the input and output of signal processor 42.

Signal processor 42 comprises: data converter 46, be connected in data converter 46 internal storage 47, be connected in the data IOB 48 of internal storage 47 and be connected in data IOB 48 and have the data-conditioner 49 that serves as signal handling equipment 40 output.

Data converter 46 receives 24 bit image data R, G and B from external unit, and 24 bit image data (R, G and B) are converted to 32 Bit datas that are suitable for frame memory 44.Described 24 bit input image datas comprise the red subdata R of 8 bits, the green subdata G of 8 bits and the blue subdata B of 8 bits, and send described 24 input image datas with the first predetermined clock frequency (for example 108 megahertzes), and also send conversion back 32 Bit datas with the first predetermined clock frequency.

32 Bit datas from data converter 46 are stored in the scratchpad memory such as internal storage 47.Internal storage 47 has input terminal separated from one another and lead-out terminal, so that output frequency is different with incoming frequency.For example, provide for the input terminal of internal storage 47 and (for example have first preset frequency, 108 megahertzes) clock signal, and the lead-out terminal of giving internal storage 47 provides and (for example has second preset frequency, 81 megahertzes) clock signal, described second preset frequency are 3/4ths of first preset frequency.Internal storage 47 can comprise FIFO (first in first out) storer or two-port RAM.

Data IOB 48 is read 32 Bit datas in the storer 47 internally, and writes data in the frame memory 44 with second preset frequency.

Now, describe the frequency of the view data in the signal processor 42 and the conversion of bit number in detail.

Fig. 5 for example understands the example waveform of the input signal of the signal processor shown in input Fig. 4, Fig. 6 for example understands the example waveform from the output signal of data converter, and Fig. 7 for example understands the example waveform from the output signal of internal storage and data IOB.

Fig. 5 show comprise three 8 seat data (data[23:16], data[15:8] and data[7:0]) 24 input image data R, G of input signal processor 42 and each among the B.Reference character shown in Fig. 5 " T " expression and corresponding cycle of first preset frequency.

Fig. 6 show by 32 Bit datas of data converter 46 conversion (data[31:24], data[23:16], data[15:8] and data[7:0]).At length say, data converter 46 makes with three input data R1, G1 of first input clock input and B1 synchronous with the input subdata R2 that imports with second input clock, so that generate first 32 bit image data that comprise four subdata RI, G1, B1 and R2, and data converter 46 is exported first 32 bit image data with the first output clock.Equally, data converter 46 makes with two input subdata G2 of second input clock input and B2 synchronous with two subdata R3 and G3 with the input of the 3rd input clock synchronously, so that generate second 32 bit image data that comprise four subdata G2, B2, R3 and G3, and data converter 46 is with second 32 bit image data of the second output clock output.Equally, make with the input subdata B3 of the 3rd input clock input and synchronous, so that form (promptly with the 3rd output clock output) the 3rd the 32 bit image data that comprise four subdata B3, R4, G4 and B4 with three subdata R4, G4 and the B4 of the input of the 4th input clock.Data converter 46 is exported the 3rd 32 bit image data B3, R4, G4 and B4 with the 4th output clock once more.During four clocks (or 4T), equal to be input to the number of 24 input image data R1-B4 the data converter 46 then from the number of 32 output image data R1-B4 of data converter 46 output.

As mentioned above, the output clock frequency of internal storage 47 (i.e. the second predetermined clock frequency) equal internal storage 47 input clock frequency (i.e. the first predetermined clock frequency) 3/4ths.In other words, the output clock period (4T/3) of internal storage 47 equal internal storage 47 input clock cycle (T) 4/3rds.Fig. 7 shows three 32 bit image data R1-B4 of storer 47 outputs internally during three outputs clock period (4T).Therefore, during designated period (4T), the number of output data equals to import the number of data.

To sum up, convert 24 input image datas to 32 output image datas and input clock frequency conversion output clock frequency equaled 24/32 times of input clock frequency, promptly 3/4 times, described input clock frequency makes the number of input image data equate with the number of output image data in designated period.In other words, when the bit number of input image data multiply by bit number that input clock frequency equals output image data and multiply by the output clock frequency, the number of input image data was identical with the number of output image data in designated period.

Above-mentioned signal processor 42 converts 24 Bit datas to 32 Bit datas, can use its memory space fully so that can store the frame memory 44 of 32 bit image data.

For example, because pixel needs 24 view data, thereby SXGA (graphic array after the especially big extension) display device with 1280 * 1024 pixels needs 1,280 * 1 of a corresponding frame, 024 * 24=31,457,280 view data.If provide 24 Bit datas to the frame memory that can store 32 Bit datas, so remaining 8 Bit data memory spaces are exactly useless, and the total storage capacity of the frame data of the storage SXGA display device that will be provided by frame memory equals 1,280 * 1,024 * 32=41,943,040, promptly greater than the total data position.Consequently, the frame memory of 64 megabits can only be stored frame data of SXGA display device.Yet,, so just can store two frame data of SXGA display device if above-mentioned frame memory 44 has the memory capacity of 64 megabits.

Frame memory 44 saves as the mode of the substitute of one of wherein previously stored two frames according to the frame data with up-to-date input, stores 32 Bit datas of two frames.

Data-conditioner 49 receives the view data of two frames from frame memory 44, and regulates this view data.Say that at length data-conditioner 49 is the view data of two interframe relatively, and handle this view data to generate data R ', G ' and the B ' after regulating according to comparative result.For example, data-conditioner 49 compares the view data (being called ' present frame ' hereinafter) of a frame with the view data of closelying follow another frame (being called " previous frame " hereinafter) before present frame, and regulates the view data (being called " current image date " hereinafter) of present frame.The view data (for example, current image date) that one of can provide from data IOB 48 rather than frame memory 44 theres two frame data.

View data R ', G ' and B ' after regulating are sent to the data driver 500 shown in Fig. 1.

Signal handling equipment 40 can be included in the signal controller 600, specifically, signal controller 600 includes only signal processor 42.

Reduced the requirement of frame memory according to the bit number of the view data of present embodiment and the conversion of frequency, and reduced clock frequency so that reduce electromagnetic interference (EMI).

Now, describe signal handling equipment in accordance with another embodiment of the present invention in detail with reference to Fig. 8.

Fig. 8 is the block diagram of signal handling equipment in accordance with another embodiment of the present invention.

With reference to Fig. 8, comprise according to the signal handling equipment 50 of present embodiment: signal processor 52 and first and

second frame memories

54 and 56 that are connected in this signal processor 52.

First and

second frame memories

54 and 56 can comprise DDR RAM (double data rate random access memory).The DDR RAM that is also referred to as DDR SDRAM (synchronous DRAM) carries out read and write at rising edge that is applied to the clock on it and falling edge.On the contrary, SDR SDRAM (single data rate SDRAM) or SDRAM read or write at the rising edge or the falling edge of clock.Therefore, DDR RAM has the speed that doubles SDRAM.In other words, to store the required time of a certain amount of data be half of SDRAM required time to DDR RAM.

With reference to Fig. 9-11, describe the operation of the signal handling equipment shown in Fig. 8 in detail.

Fig. 9 and 10 for example understands the example waveform of the input/output signal of the signal processor shown in Fig. 8 respectively, and Figure 11 for example understands example waveform that read or that be written to the view data in the frame memory from frame memory.

With reference to Fig. 9, with input image data corresponding to 48 of the first clock period 1.5T ' inputs of clock frequency (for example 54 megahertzes).In 48 input image datas of input signal processor 52 each all comprise three 16 seat data (data[47:32], data[31:16] and data[15:0]), 12 16 seat data of input in being equivalent to the fixed time X of four first clock period thus.

With reference to Figure 10,48 input image datas that signal processor 52 will be in first clock frequency convert 32 output image datas being in second clock frequency (for example 81 megahertzes) (data[31:16] and data[15:0]) to.Described conversion be with basically with previous embodiment in the same method carry out, therefore omit detailed description to it.At this, T ' is the second clock cycle corresponding to the second clock frequency, and equals 2/3rds of first clock period.Be equivalent to 12 the 16 seat data of fixed time X internal conversion in six second clock cycles.

Therefore, during designated period X, the number of output data equals to import the number of data.

With reference to Figure 11,

frame memory

54 and 56 rising edge and falling edges at the clock with second clock frequency read or write.Therefore, handle 12 16 and import three clock period that the required times of subdata are equivalent to equal 0.5X.Consequently, this embodiment with half input time with image data storage in the frame memory 54 56.

First frame memory 54 and second frame memory 56 are via separately data bus and be connected in signal processor 52.This means that signal processor 52 can be independently and side by side visit frame memory 54 and 56.On the contrary, first and

second frame memories

54 and 56 sharing of common address bus preferably.

Write for one in 52 pairs first and second frame memories 54 of signal processor and 56, simultaneously in

frame memory

54 and 56 another read, this is described in detail with reference to Figure 12-15.

Figure 12 and 13 for example understands the example in the operation of the signal processor shown in input N frame and (N+1) Fig. 8 image duration respectively.

Suppose that the LCD according to present embodiment comprises a plurality of pixel columns, for example m pixel column.As shown in figure 10, N frame image data after switch bit number and clock frequency is represented with D (N), view data (being called " i line data " hereinafter) in i the pixel column in the middle of the N frame image data represents with D (N) i, and central i pixel column of N frame image data and the view data usefulness D (N) in (i+1) individual pixel column _{I, i+1}Expression.

With reference to Figure 12, the image data lines after signal processor 52 treatment conversion.Signal processor 52 comprises a plurality of line storage (not shown), and each line storage can both the capable view data of storage pixel.

Suppose that 54 pairs of N frame image datas of first frame memory (M1) write, and the image of 56 pairs of (N-1) frames of second frame memory (M2) is read.

The first line data D (N) at input N frame ₁During this time, signal processor 52 is D (N) ₁Store in the first line storage (not shown).

The second line data D (N) at input N frame ₂During this time, signal processor 52 is with D (N) ₁Be written to first frame memory 54 from first line storage, and it is D (N) ₂Store in the second line storage (not shown), and D (N) ₂Be written in first frame memory 54.Simultaneously, signal processor 52 is read D (N-1) from second frame memory 56 ₁And D (N-1) ₂, and they are stored in the third and fourth line storage (not shown).During cycle 1H,

frame memory

54 and 56 can be handled the view data of two pixel columns.

The third line data D (N) at input N frame ₃During this time, the view data of signal processor 52 comparison (N-2) frame, (N-1) frame and N frames is regulated for data.Say that at length signal processor 52 reads the D (N) that is stored in first line storage ₁, read the D (N-1) that is stored in the third line storer ₁With read the D (N-2) that is stored in second frame memory 56 ₁, and compare them so that the view data after generating adjusting.Simultaneously, signal processor 52 is D (N) ₃Store into and stored D (N) ₁First line storage in.This need not other additional row storer.In addition, signal processor 52 is with D (N-1) ₁And D (N-1) ₂Be written in first frame memory 54, and it reads D (N-2) from second frame memory 56 ₁And D (N-2) ₂, and they are stored in the 5th and the 6th line storage (not shown) for data relatively.

Fourth line data D (N) at input N frame ₄During this time, 52 pairs of signal processors are stored in the D (N) in second line storage ₂, be stored in the D (N-1) in the fourth line storer ₂With the D (N-2) that is stored in the 6th line storage ₂Read, and compare them so that the view data after generating adjusting.Simultaneously, signal processor 52 is D (N) ₄Store into and stored D (N) ₂Second line storage in.This need not other line storage.In addition, signal processor 52 is D (N-1) ₃Be written in first frame memory 54, and it is D (N-2) ₄Store in second line storage, and be written in first frame memory 54.In addition, signal processor is read D (N-1) from second frame memory 56 ₃And D (N-1) ₄, and they are stored in third and fourth line storage for data relatively.

Signal processor 52 is since the operation of the 5th pixel column and m pixel column multiimage data.

Like this, signal processor 52 is written to D (N) in first frame memory 54, so that first frame memory 54 storage D (N) and D (N-1), second frame memory 56 is stored D (N-1) and D (N-2), and two

frame memories

54 and 56 have all been stored three frame data whereby.In addition, signal processor 52 is read and is written to from

frame memory

54 and 56 in described

frame memory

54 and 56, compares (N-2) frame, (N-1) frame and N frame simultaneously so that the view data after generating adjusting.

With reference to Figure 13, during the view data of input (N+1) frame, first frame memory 54 and second frame memory, 56 their roles of exchange, so that first frame memory 54 is carried out read operation, and second frame memory 56 is carried out write operation.That is to say, D (N) and D (N-1) that 52 pairs of signal processors are stored in first frame memory 54 read, and they are stored in the line storage for data relatively, and its is written to D (N+1) that imports and the D (N) that is stored in the line storage in second frame memory 56 from external unit.Then, first frame memory, 54 storage D (N) and D (N-1), and second frame memory, 56 storage D (N+1) and D (N).

Because the operation of (N+1) frame is identical with the operation of N frame basically, thereby omit the detailed description of this generic operation of signal processor 52 and

frame memory

54 and 56.

For in succession frame repeats this operation.

Figure 14 and 15 for example understands another example in the operation of importing the signal processor shown in N frame and (N+1) image duration, Fig. 8 respectively.

As shown in figure 10, view data after the conversion of N frame represents that with D (N) view data after the described conversion obtains a plurality of data segments divided by 16, and i data segment (i) represented with D (N), (i j) represents and the individual data segment of an i data segment to the (i+1) is with D (N).

With reference to Figure 14, eight 16 bit image data are input in the signal processor 52, and signal processor 52 is by the view data after a plurality of clock-units (for example four clock-units) treatment conversion.Signal processor 52 can comprise a plurality of storer (not shown) that can store eight 16 Bit datas such as trigger.

Suppose that the view data of 54 pairs of N frames of first frame memory (M1) writes, and the image of 56 pairs of (N-1) frames of second frame memory (M2) is read.

During four clocks (i.e. first to the 4th clock) at first, signal processor 52 stores D (N) (1,8) in the first memory into.

During four clocks secondarily (i.e. the 5th to the 8th clock), signal processor 52 stores D (N) (9,16) in the second memory into.In addition, the D (N) (1,8) that is stored in the first memory is written in first frame memory 54, from second frame memory 56, reads D (N-1) (1,8) and it is stored in the 3rd storer at the 5th and the 6th clock period.At the 7th and the 8th clock period, from the 3rd storer, read D (N-1) (1,8) and be written in first frame memory 54, from second frame memory 56, read D (N-2) (1,8) and be stored in the 4th storer.

Meanwhile, the view data of N frame, (N-1) frame and (N-2) frame is read and compared to signal processor 52, regulates for carry out data at the 7th and the 8th clock period.At length say, read the D (N) (1,8) that is stored in the first memory by turn, be stored in the D (N-1) (1,8) in the 3rd storer and be stored in D (N-2) (1,8) in the 4th storer, and generate the view data after regulating.

During four clocks of the 3rd (i.e. the 9th to the 12 clock), signal processor 52 stores D (N) (17,24) in the first memory into.In addition,, the D (N) (9,16) that is stored in the second memory is written in first frame memory 54, from second frame memory 56, reads D (N-1) (9,16) and be written in the 3rd storer at the 9th and the tenth clock period.At the 11 and the 12 clock period, from the 3rd storer, read D (N-1) (9,16) and be written in first frame memory 54, and the D (N-2) (9,16) from second frame memory 56 is stored in the 4th storer.

At the 11 and the 12 clock period, the D (N) (9 in the second memory is sequentially read and relatively be stored in to signal processor 52,16), be stored in D (N-1) (9 in the 3rd storer, 16) and be stored in D (N-2) (9 in the 4th storer, 16), and the view data after generate regulating.

Like this, at continuous clock period, handle all images data of N frame.

Therefore, D (N) is written in first frame memory 54, and thus D (N) and D (N-1) are stored in first frame memory 54, and D (N-1) and D (N-2) are stored in second frame memory 56, so that two

frame memories

54 and 56 view data of all storing three frames.In addition, signal handling equipment carries out read and write to frame

memory

54 and 56, and reads and compare the view data of (N-2) frame, (N-1) frame and N frame, so that generate the view data after regulating.

With reference to Figure 15, during the view data of input (N+1) frame, first frame memory 54 and second frame memory, 56 their roles of exchange, so that first frame memory 54 is carried out read operation, and second frame memory 56 is carried out write operation.That is to say, signal processor 52 reads D (N) and the D (N-1) that is stored in first frame memory 54, and they are stored in the storer for data relatively, and it will be written in second frame memory 56 from the D (N+1) of external unit input and the D (N) that is stored in the storer.Then, first frame memory, 54 storage D (N) and D (N-1), and second frame memory, 56 storage D (N+1) and D (N).

Because the operation of its (N+1) frame is identical with the N frame basically, so omit the detailed description of this generic operation of signal processor 52 and

frame memory

54 and 56.

For in succession frame repeats this operation.

According to present embodiment, carry out view data by the unit of four clocks and handle and need not line storage.Replace to use described these storeies, and the storer with little memory capacity that uses is with the size that reduces signal handling equipment with reduce production costs.

Can change the time and the number of the clock that the unit comprised of the view data processing that is used for signal processor 52 and

frame memory

54 and 56.

As mentioned above, the bit number of input image data and the conversion of frequency can allow the view data of frame memory storage two frames, and can allow two frame memory storage be used for the view data of three frames that data regulate in conjunction with the DDR RAM of above-mentioned bit number and frequency inverted.For example, view data can be regulated by the view data that compares three frames.

Meanwhile, signal handling equipment may further include: be used for directly sending view data/receive the data I/O unit of view data there from the DDR storer to the DDR storer, will describe described data I/O unit below in detail.The data I/O unit can be placed between signal processor and the DDR storer.

Now, describe in detail according to the signal handling equipment embodiment of the invention, that comprise the DDR storer with reference to Figure 16-19.

Figure 16 is the block diagram according to the signal handling equipment that comprises the data output unit of embodiment, and Figure 17 is the signal timing diagram of the element of the signal handling equipment shown in Figure 16.

With reference to Figure 16, comprise according to the signal handling equipment of present embodiment: signal processor 60, data output unit 64 and DDR storer 62.This data output unit 64 comprises multiplexer 642 and trigger 644.

To be input among the input terminal D0 and D1 of multiplexer 642 from 32 input image datas of signal processor 60 (data1[31:0] and data2[31:0]).First clock (clock1) that will have predetermined period T is input among the selection terminal S of multiplexer 642, and multiplexer 642 and first clock (clock1) synchronously are input to one of them view data (data1[31:0] and data2[31:0]) among input terminal D0 and the D1 through lead-out terminal Q.At length say, when first clock (clock1) is high level, the view data of multiplexer 642 input D0 (data1[31:0]), and when first clock (clock1) is low level, the view data of its input D1 (data2[31:0]).With reference to Figure 17, multiplexer 642 is synthetic with them by alternately arranging view data (data1[31:0], data2[31:0]), so that generate the output data (data_OUT1[31:0]) of the two/one-period (T/2) with the cycle (T) that equals to import data (data1[31:0], data2[31:0]).Output data (data_OUT1[31:0]) is input in the trigger 644.Trigger 644 and the rising edge of second clock (clock2) are synchronously exported the view data that received through its lead-out terminal Q by its input terminal D (data_OUT1[31:0]).The output image data of trigger 644 (data_OUT2[31:0]) is input in the DDR storer 62 and with first clock (clock1) synchronously is stored in wherein.As shown in figure 17, the frequency (2/T) of the second clock (clock2) that uses in data output unit 64 is the twice of the frequency (1/T) of first clock (clock1) of use in DDR storer 62.

Figure 18 is the block diagram according to the signal handling equipment that comprises data input cell of embodiment, and Figure 19 is the signal timing diagram of the element of the signal handling equipment shown in Figure 18.

With reference to Figure 18, signal processor comprises: signal processor 60, data input cell 65 and DDR storer 62.Data input cell 65 comprises first and second multiplexers 654 and the 655 and first to the 3rd trigger 652,656 and 657.

To be input to from the view data DDR_data of DDR storer 62 in first trigger 652, and synchronously the view data of the input terminal D of first trigger 652 (data[31:0]) will be exported from the lead-out terminal Q of first trigger 652 there with the rising edge of above-mentioned second clock (clock2).The output data of first trigger 652 (data_IN[31:0]) is input among the input terminal D1 of the input terminal D0 of first multiplexer 654 and second multiplexer 655.Because the input terminal D1 and the lead-out terminal Q of second multiplexer 654 are connected with each other, and the input terminal D0 and the lead-out terminal of the 3rd multiplexer 655 are connected with each other, therefore first and second multiplexers 654 and 655 convert the view data with cycle 0.5T (data_IN[31:0]) to period T view data, and export them.Above-mentioned first clock (clock1) that will equal the work clock (DDR_clock) of DDR storer 62 is input among the selection terminal S of first and second multiplexers 654 and 655, odd number of images data in the middle of first multiplexer, 654 output image datas (data_IN[31:0]) (data1_IN[31:0]), and second multiplexer 655 and first clock (clock1) are synchronously exported even image data (data2_IN[31:0]).By the second and the 3rd trigger 656 and 657 view data (data1_IN[31:0], data2_IN[31:0]) all is input in the signal processor 60.Be similar to above-described data output unit 64, as shown in figure 19, the frequency 2/T of the second clock (clock2) that uses in data input cell 65 is the twice of the frequency 1/T of first clock (clock1) of use in DDR storer 62.

Now, with reference to the signal processor of Figure 20-23 detailed description according to other embodiments of the invention.

Figure 20 is the block diagram according to the signal handling equipment that comprises the data output unit of another embodiment, and Figure 21 is the signal timing diagram of the element of the signal handling equipment shown in Figure 20.

With reference to Figure 20, comprise: signal processor 60, be connected in the data output unit 66 that is used for synthetic input image data of this signal processor 60 and the DDR storer 62 that is connected in this data output unit 66 according to the data processing equipment of present embodiment.

Data output unit 66 comprises: be connected in signal processor 60 first and

second triggers

661 and 662, have the input terminal that is connected in first and

second triggers

661 and 662 and be connected in the multiplexer 663 of lead-out terminal of DDR storer 62 and the clock delay unit 664 that is used for generating delayed clock (DDR_clock1) and delayed clock (DDR_clock1) is input to DDR storer 62.Delayed clock (DDR_clock1) is to postpone to have predetermined period the input clock (clock) of (T) obtains by measuring dT on schedule, with described delayed clock be input to first and

second triggers

661 and 662 and multiplexer 663 in.

Now, describe the operation of the signal processor shown in Figure 20 in detail with reference to Figure 21.

Signal processor 60 receives view data there from external unit, and described view data be divided into will with synchronous two subdatas of output of the input clock with predetermined period (clock).In this embodiment, signal processor 60 outputs to the input terminal D of first trigger 661 to 32 odd number of images data (data1[31:0]), and even image data (data2[31:0]) is outputed to the input terminal D of second trigger 662.

The rising edge of first trigger 661 and input clock (clock) synchronously is latched into input image data (data1[31:0]) among the lead-out terminal Q, and the negative edge of second trigger 662 and input clock (clock) synchronously is input to view data (data2[31:0]) among the lead-out terminal Q.Then, as shown in figure 21, the output image data of the output image data of first trigger 661 (data3[31:0]) and second trigger 662 (data4[31:0]) replace by the half period (0.5T) of input clock (clock).

View data (data3[31:0] and data4[31:0]) is input among the input terminal D0 and D1 of multiplexer 663.Input clock (clock) is input among the selection terminal S of multiplexer 663, and multiplexer 663 synchronously will be input to one of them view data of input terminal D0 and D1 through lead-out terminal Q output Q with input clock (clock).At length say, when input clock (clock) is high level, the view data of multiplexer 663 input D0 (data3[31:0]), and when input clock (clock) is low level, the view data (data4 31:0) of its input D1).With reference to Figure 21, multiplexer 663 will be synthetic from the output image data of first and second triggers 661 and 662 (data3[31:0], data4[31:0]), so that generate the output data in the cycle (0.5T) with the half period (T) that equals to import data (data1[31:0], data2[31:0]).The output of the synthesis of alternating ground of view data is from the output image data of first and second triggers 661 and 662 (data3[31:0], data4[31:0]).

Output data (data_OUT[31:0]) is input in the DDR storer 62.DDR storer 62 is written to view data (data_OUT[31:0]) in the suitable address at the rising edge of the delayed clock that comes from clock delay unit 664 (DDR_clock1) and negative edge.For view data (data_OUT[31:0]) determines that dT time delay of delayed clock (DDR_clock1) obtains the boundary of Time Created and retention time, so that DDR storer 62 image data processing (data_OUT[31:0]) normally.

With reference to Figure 21, the frequency (1/T) of the input clock (clock) that uses in data output unit 66 equals the frequency (1/T) of the delayed clock (DDR_clock1) of use in DDR storer 62.

Figure 22 is the block diagram according to the signal handling equipment that comprises data input cell of another embodiment, and Figure 23 is the signal timing diagram of the element of the signal handling equipment shown in Figure 22.

With reference to Figure 22, signal processor comprises in accordance with another embodiment of the present invention: the DDR storer 62 of storing image data, be connected in this DDR storer 62 and the data input cell 67 of divide image data and the signal processor 60 that is connected in this data input cell 67 from this DDR storer 62.

Data input cell 67 comprises: have the input terminal that is connected in DDR storer 62 and be connected in first and

second triggers

672 and 673 and generate delayed clock (DDR_clock1) and delayed clock (DDR_clock1) is input to clock delay unit 671 in the DDR storer 62 of the lead-out terminal of signal processor 60.Delayed clock (DDR_clock1) is to postpone to have predetermined period the input clock (clock) of (T) obtains by measuring dT on schedule, and described delayed clock is input in first and

second triggers

672 and 673.

Now, describe the operation of the signal processor shown in Figure 22 in detail with reference to Figure 23.

DDR storer 62 is synchronously exported the view data DDR_data that is stored in the DDR storer 62 with cycle 0.5T with the rising edge and the negative edge of delayed clock (DDR_clock1).Output image data DDR_data is input in first and

second triggers

672 and 673.

The rising edge of first trigger 672 and input clock (clock) is the odd data in the middle of the output image data DDR_data (data3_IN[31:0]) synchronously, and second trigger 673 and the negative edge of input clock (clock) are synchronously exported even data (data4_IN[31:0]).The odd data that will change by period T (data3_IN[31:0]) and even data (data4_IN[31:0]) be input in the signal processor 60.

Signal processor 60 receives and regulates the view data from first and

second triggers

672 and 673, and the view data after the output adjusting.

Meanwhile, determine dT time delay of delayed clock (DDR_clock1), so that DDR storer 62 and first and

second triggers

672 and 673 image data processing and provide view data after the processing for signal processor 60 in time.

With reference to Figure 23, be similar to the embodiment of front, the frequency (1/T) of the input clock (clock) that uses in data input cell 67 equals the frequency (1/T) of the delayed clock DDR_clock1 of use in DDR storer 62.

Signal handling equipment can not only comprise data output unit 66 but also comprise data input cell 67 in accordance with another embodiment of the present invention.Signal processor 60 can comprise data output unit 66 or data input cell 67.

As mentioned above, data output unit 66 and data input cell 67 according to present embodiment are used the clock signal with frequency (1/T) (frequency that equals to use in the signal processor), and among the embodiment in front, data output unit 64 and data input cell 65 are used has the clock signal of frequency (2/T).Therefore, reduced power consumption and electromagnetic interference (EMI), and alleviated and produce the complexity of high-frequency clock signal, thereby reduced production cost according to the signal handling equipment of present embodiment.

Although above describing the preferred embodiments of the present invention in detail, this should obviously be understood that for a person skilled in the art: many distortion and/or modification in this basic inventive concept of lecturing all will fall within the spirit and scope of the present invention defined in the appended claims.

Claims

1. the method for the data in the processes and displays equipment, its current image date D (N) to the current N frame that receives handles, and described method comprises:

The old line data D (N-2) of storage N-2 frame in second frame memory, the N-2 frame is at the front cross frame of current N frame;

The current first line data D (N) ₁Store in first line storage of a plurality of line storages, each line storage can both the capable view data of storage pixel;

The current second line data D (N) ₂Store in second line storage of a plurality of line storages;

With D (N) ₁Be written to first frame memory from first line storage, and with D (N) ₂Be written to first frame memory from second line storage;

From second frame memory, read the first previous line data D (N-1) of previous frame N-1 frame ₁With the second line data D (N-1) ₂, and they are stored in third and fourth line storage, so that the first frame memory storage D (N) and D (N-1), and the second frame memory storage D (N-1) and D (N-2).

2. method according to claim 1 comprises that further more previous view data D (N-1), old view data D (N-2) and current image date D (N) regulate for data.

3. method according to claim 2 further comprises:

From first line storage, read D (N) ₁

From the third line storer, read D (N-1) ₁And

Read the first old line data D (N-2) that is stored in second frame memory ₁, so that compare D (N) ₁, D (N-1) ₁And D (N-2) ₁

4. method according to claim 3 further is included in and reads D (N) from first line storage ₁Afterwards, with the current the third line data D (N) in first line storage ₃Substitute the current first line data D (N) ₁

5. method according to claim 3 further comprises:

D (N-1) ₁And D (N-1) ₂Be written in first frame memory; With

From second frame memory, read D (N-2) ₁, and it is stored in the fifth line storer; And

From second frame memory, read D (N-2) ₂, and it is stored in the 6th line storage.

6. the method for the data in the processes and displays equipment, its current image date D (N) to the current N frame that receives handles, and described method comprises:

During first four clock period:

First eight D (N) are stored in the first memory;

During second four clock period:

Second eight D (N) are stored in the second memory;

First eight D (N) are stored in first frame memory, read first eight of previous view data D (N-1) of previous N-1 frame from second frame memory, and first eight of D (N-1) are written in the 3rd storer; And

From the 3rd storer, read first eight of D (N-1) and first eight of D (N-1) are written in first frame memory, and from second frame memory, pronounce to first eight of the old view data D (N-2) of the N-2 frame of the front cross frame of current N frame and first eight of D (N-2) are stored in the 4th storer, so that read D (N), D (N-1) and D (N-2) by turn.

7. the method for the data in the processes and displays equipment, its next view data D (N+1) to the next frame N+1 frame that receives handles, and described method comprises:

From first frame memory, read the current image date D (N) of present frame N frame, and D (N) is written in first line storage;

The previous view data D (N-1) that reads previous frame N-1 frame from first frame memory also is written to D (N-1) in second line storage;

D (N+1) is written in second frame memory, so that the first frame memory storage D (N) and D (N-1), and the second frame memory storage D (N) and D (N+1).