CN101281910A - Polysilicon concatenating diode - Google Patents
Polysilicon concatenating diode Download PDFInfo
- Publication number
- CN101281910A CN101281910A CN 200810062062 CN200810062062A CN101281910A CN 101281910 A CN101281910 A CN 101281910A CN 200810062062 CN200810062062 CN 200810062062 CN 200810062062 A CN200810062062 A CN 200810062062A CN 101281910 A CN101281910 A CN 101281910A
- Authority
- CN
- China
- Prior art keywords
- trap
- dark
- active area
- diode
- diffusion active
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920005591 polysilicon Polymers 0.000 title claims description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 48
- 238000009792 diffusion process Methods 0.000 claims abstract description 47
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 abstract 8
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 9
- 230000003068 static effect Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
The invention discloses a multi-crystal silicon cascade diode which includes a P substrate. N traps are equipped at two ends of the P substrate, two deep N traps which bottom are connected into a whole are arranged in each N trap, a P trap are equipped between the two deep N traps, N+ diffusion active regions are respectively arranged on each deep N trap, a P+ diffusion active region and a N+ diffusion active region are arranged on the P trap, all of the diffusion active regions are insulated by a shallow groove insulated layer, a plurality of P+ intrinsic multi-crystal silicon and a plurality of N+ intrinsic multi-crystal silicon which have same quantity with the P+ intrinsic multi-crystal silicon are equipped on the shallow groove insulated layer between the two N traps, the P+ intrinsic multi-crystal silicon and the N+ intrinsic multi-crystal silicon are distributed at an interval and connected by a intrinsic multi-crystal silicon. In the multi-crystal silicon cascade diode, the P+ diffusion active regions on each of the P traps and the N+ diffusion active regions between the two deep N traps are connected which are equivalent to that a emitter electrode and a base electrode in a parasitical triode of the cascade diode are connected, thereby inhibiting darlington effect.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate in particular to a kind of polysilicon concatenating diode.
Background technology
Static discharge (ESD, Electron Static Discharge) is when the pin suspension joint of an integrated circuit, and a large amount of electrostatic charges pour into the instantaneous process of integrated circuit, the about 100ns consuming time of whole process from outside to inside.When the static discharge of integrated circuit, can produce the high pressure of hundreds if not thousands of volts, with the gate oxide breakdown of input stage in the integrated circuit.Along with the progress of integrated circuit technology, the characteristic size of metal-oxide-semiconductor is more and more littler, and the thickness of gate oxide is also more and more thinner, under this trend, use high performance ESD protective device release electrostatic charge with the protection grid oxic horizon seem very important.
The model of ESD phenomenon mainly contains four kinds: human body discharging model (HBM), mechanical discharging model (MM), device charge model (CDM) and electric field induction model (FIM).Concerning general integrated circuit (IC) products, generally to pass through human body discharging model, the test of mechanical discharging model and device charge model.In order to bear so high static discharge voltage, integrated circuit (IC) products must be used the electrostatic discharge protector with high-performance, high tolerance usually.Resist the purpose that static hits in order to reach the protection chip; at present existing multiple electrostatic protection device is suggested, such as diode, and the NMOS of grounded-grid pipe; generally acknowledge that wherein the reasonable protective device of effect is controllable silicon (SCR, SiliconControlled Rectifier).But the trigger voltage of traditional silicon-controlled electrostatic discharge (ESD) protective device is very high.Along with dwindling of the characteristic size of device, the operating voltage of circuit also constantly descends, for the trigger voltage with the silicon-controlled electrostatic discharge (ESD) protective device is reduced in the considerable magnitude of voltage, people have proposed the silicon-controlled electrostatic discharge (ESD) protective device that a kind of utilization triggers based on concatenating diode.
Fig. 1 is the three kind connectivity scenarios of concatenating diode in the silicon-controlled electrostatic discharge (ESD) protective device.Concatenating diode silicon-controlled electrostatic discharge (ESD) protective device is the grid that after utilizing the low-voltage of concatenating diode to trigger electric current is poured into silicon-controlled device, makes the silicon-controlled electrostatic discharge (ESD) protective device open fast.But the difficult point of concatenating diode silicon-controlled electrostatic discharge (ESD) protective device is the design of diode in the CMOS technology, because Darlington effect (Darlington Effect) easily causes the direct current electric leakage of concatenating diode very big.
As shown in Figure 2, a kind of traditional concatenating diode, comprise P type substrate, P type substrate is provided with 4 N traps, each trap N is provided with P+ diffusion active area and N+ diffusion active area, all spread between active areas all by shallow groove isolation layer (STI, Shallow Trench Isolation) isolates (M.D.Ker, Y.W.Hsiao, and W.L.Wu, " ESD-Protection Design With ExtraLow-Leakage-Current Diode String for RF Circuits in SiGe BiCMOSProcess; " IEEE Transactions on Device and Materials Reliability, vol.6, pp.517-527,2006.).
The most submarginal P+ diffusion active area connects electrical anode (Anode) on this concatenating diode, and the most submarginal N+ diffusion active area connects electrical cathode (Cathode), but the electric leakage of the direct current of this concatenating diode is bigger, has limited its range of application.
Summary of the invention
The invention provides the little polysilicon concatenating diode of a kind of direct current electric leakage.
A kind of polysilicon concatenating diode comprises the P substrate, and P substrate one end is provided with the first dark N trap and the second dark N trap that a N trap and bottom fuse, and is provided with a P trap between the first dark N trap and the second dark N trap, and the side is surrounded by a N trap; The P substrate other end is provided with the 3rd dark N trap and the 4th dark N trap that the 2nd N trap and bottom fuse, and is provided with the 2nd P trap between the 3rd dark N trap and the 4th dark N trap, and the side is surrounded by the 2nd N trap; The first dark N trap, the second dark N trap, the 3rd dark N trap, be respectively equipped with N+ diffusion active area on the 4th dark N trap, the 2nd N+ spreads active area, the 3rd N+ spreads active area, the 4th N+ spreads active area, ecto-entad, the one P trap is provided with P+ diffusion active area and the 5th N+ diffusion active area, the 2nd P trap is provided with the 6th N+ diffusion active area and the 2nd P+ diffusion active area, all diffusion active areas are all isolated by shallow groove isolation layer, be covered with the N+ intrinsic polysilicon of some P+ intrinsic polysilicons and equal number on the shallow groove isolation layer between the one N trap and the 2nd N trap, the P+ intrinsic polysilicon distributes with N+ intrinsic polysilicon space and is connected by intrinsic polysilicon.
When above-mentioned concatenating diode was applied in the controllable silicon, its circuit connecting mode was as follows:
P+ on each P trap diffusion active area with and two dark N traps of both sides on N+ diffusion active area connect by lead, in the P+ intrinsic polysilicon or N+ intrinsic polysilicon on the shallow groove isolation layer between the one N trap and the 2nd N trap, except that the P+ intrinsic polysilicon or N+ intrinsic polysilicon of end, two ends, one deck P+ intrinsic polysilicon is connected by lead with one deck N+ intrinsic polysilicon in remaining P+ intrinsic polysilicon or the N+ intrinsic polysilicon, P+ diffusion active area on the one P trap connects electrical anode, the 5th N+ diffusion active area connects the P+ intrinsic polysilicon that is positioned at end on the shallow groove isolation layer between a N trap and the 2nd N trap, the 6th N+ on the 2nd P trap diffusion active area connects electrical cathode, and the 2nd P+ diffusion active area connects the N+ intrinsic polysilicon that is positioned at end on the shallow groove isolation layer between a N trap and the 2nd N trap.
P+ diffusion active area in the said structure on the P trap and N+ diffusion active area are equivalent to the anode and the negative electrode of diode, P+ intrinsic polysilicon and N+ intrinsic polysilicon are equivalent to a diode, as can be seen, said structure is equivalent to the concatenating diode be made up of at least 3 diodes polyphone.
P+ diffusion active area on each P trap of polysilicon concatenating diode of the present invention and the N+ diffusion active area on the dark N trap in both sides are connected, the emitter that promptly is equivalent to parasitic triode in the above-mentioned cascade diode links to each other with base stage, make the Darlington effect be inhibited, and electric current flows through from polysilicon diode, thereby reduced substrate current greatly, reached the little and low double effects of trigger voltage of direct current electric leakage.
Description of drawings
Fig. 1 is applied to the circuit theory diagrams of three kinds of connected modes in the controllable silicon for concatenating diode;
Fig. 2 is the cross-sectional view of existing cascade diode;
Fig. 3 is the cross-sectional view of polysilicon concatenating diode of the present invention;
Fig. 4 is the vertical view of polysilicon concatenating diode shown in Figure 3.
Embodiment
As shown in the figure, a kind of polysilicon concatenating diode comprises P substrate 1, and P substrate 1 one ends are provided with the first dark N trap 51 and the second dark N trap 52 that a N trap 21 and bottom fuse, be provided with a P trap 31 between the first dark N trap 51 and the second dark N trap 52, the side is surrounded by a N trap 21; P substrate 1 other end is provided with between the 3rd dark N trap 53 that the 2nd N trap 22 and bottom fuse and the 4th dark N trap 54, the three dark N traps 53 and the 4th dark N trap 54 and is provided with the 2nd P trap 32, and the side is surrounded by the 2nd N trap 22.
Be respectively equipped with N+ diffusion active area 81, the 2nd N+ diffusion active area 82, the 3rd N+ diffusion active area 83, the 4th N+ on first dark N trap 51, second dark N trap the 52, the 3rd dark N trap the 53, the 4th dark N trap 54 and spread active area 84, ecto-entad, the one P trap 31 is provided with P+ diffusion active area 61 and the 5th N+ diffusion active area 85, the 2nd P trap 32 is provided with the 6th N+ and spreads 86 active areas and the 2nd P+ diffusion active area 62, and all diffusion active areas are all isolated by shallow groove isolation layer 4.
Be covered with on the shallow groove isolation layer 4 between the one N trap 21 and the 2nd N trap 22 as if 2 P+ intrinsic polysilicons 91 and 2 N+ intrinsic polysilicons 92, P+ intrinsic polysilicon 91 distributes with N+ intrinsic polysilicon 92 spaces and is connected by intrinsic polysilicon 9.
N trap on the above-mentioned polysilicon diode, P trap, dark N trap, P+ diffusion active area and N+ diffusion active area obtain by carry out the ion injection on the P substrate.
P+ intrinsic polysilicon 91 also is to obtain by the ion injection on intrinsic polysilicon 9 with N+ intrinsic polysilicon 92.
When above-mentioned polysilicon concatenating diode was applied to controllable silicon, circuit connecting mode was as follows:
P+ on each P trap diffusion active area with and two dark N traps of both sides on N+ diffusion active area connect by lead, in the P+ intrinsic polysilicon 91 or N+ intrinsic polysilicon 92 on the shallow groove isolation layer 4 between the one N trap 21 and the 2nd N trap 22, except that the P+ intrinsic polysilicon 91 or N+ intrinsic polysilicon 92 of end, two ends, one deck P+ intrinsic polysilicon 91 and one deck N+ intrinsic polysilicon 92 are connected by lead in remaining P+ intrinsic polysilicon 91 or the N+ intrinsic polysilicon 92.
P+ diffusion active area 61 on the one P trap 21 connects electrical anode, the 5th N+ diffusion active area 85 connects shallow trench isolation between N traps 21 and the 2nd N trap 22 is positioned at end on 4 layers P+ intrinsic polysilicon 91, the 6th N+ on the 2nd P trap 22 diffusion active area 86 connects electrical cathode, is positioned at the N+ intrinsic polysilicon 92 of end on the shallow groove isolation layer 4 that the 2nd P+ diffusion active area 62 connects between N traps 21 and the 2nd N trap 22.
Claims (1)
1. polysilicon concatenating diode, comprise P substrate (1), it is characterized in that: P substrate (1) one end is provided with the first dark N trap (51) and the second dark N trap (52) that a N trap (21) and bottom fuse, be provided with a P trap (31) between the first dark N trap (51) and the second dark N trap (52), the side is surrounded by a N trap (21); P substrate (1) other end is provided with the 3rd dark N trap (53) and the 4th dark N trap (54) that the 2nd N trap (22) and bottom fuse, and is provided with the 2nd P trap (32) between the 3rd dark N trap (53) and the 4th dark N trap (54), and the side is surrounded by the 2nd N trap (22); The first dark N trap (51), the second dark N trap (52), the 3rd dark N trap (53), be respectively equipped with N+ diffusion active area (81) on the 4th dark N trap (54), the 2nd N+ spreads active area (82), the 3rd N+ spreads active area (83), the 4th N+ spreads active area (84), ecto-entad, the one P trap (31) is provided with P+ diffusion active area (61) and the 5th N+ diffusion active area (85), the 2nd P trap (32) is provided with the 6th N+ diffusion active area (86) and the 2nd P+ diffusion active area (62), all diffusion active areas are all isolated by shallow groove isolation layer (4), be covered with the N+ intrinsic polysilicon (92) of some P+ intrinsic polysilicons (91) and equal number on the shallow groove isolation layer (4) between the one N trap (21) and the 2nd N trap (22), P+ intrinsic polysilicon (91) distributes with N+ intrinsic polysilicon (92) space and is connected by intrinsic polycrystalline (9) silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810062062 CN100590875C (en) | 2008-05-28 | 2008-05-28 | Polysilicon concatenating diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810062062 CN100590875C (en) | 2008-05-28 | 2008-05-28 | Polysilicon concatenating diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101281910A true CN101281910A (en) | 2008-10-08 |
| CN100590875C CN100590875C (en) | 2010-02-17 |
Family
ID=40014290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810062062 Expired - Fee Related CN100590875C (en) | 2008-05-28 | 2008-05-28 | Polysilicon concatenating diode |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100590875C (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034812A (en) * | 2009-09-25 | 2011-04-27 | 精工电子有限公司 | Semiconductor device |
| CN102254911A (en) * | 2011-07-13 | 2011-11-23 | 浙江大学 | Controlled silicon device provided with secondary conductive path and triggered with help of diodes |
| CN102544068A (en) * | 2012-03-09 | 2012-07-04 | 浙江大学 | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes |
| CN102543998A (en) * | 2012-02-20 | 2012-07-04 | 中国科学院微电子研究所 | Polycrystalline silicon series diode string and manufacturing method thereof |
| CN102593125A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Groove type MOS (metal oxide semiconductor) electrostatic discharge structure and integrated circuit |
| CN102623453A (en) * | 2011-01-27 | 2012-08-01 | 无锡华润华晶微电子有限公司 | Power device, preparation method and energy-saving electronic lighting circuit using the same |
| CN103972172A (en) * | 2013-02-01 | 2014-08-06 | 厦门博佳琴电子科技有限公司 | Diode selection element array structure and manufacturing method |
| CN105702674A (en) * | 2016-03-18 | 2016-06-22 | 江苏艾伦摩尔微电子科技有限公司 | Novel electrostatic discharge protection apparatus |
| CN111725305A (en) * | 2020-07-31 | 2020-09-29 | 华虹半导体(无锡)有限公司 | Semiconductor device and method for manufacturing the same |
| CN111816650A (en) * | 2019-04-12 | 2020-10-23 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection structure and forming method thereof |
-
2008
- 2008-05-28 CN CN 200810062062 patent/CN100590875C/en not_active Expired - Fee Related
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034812B (en) * | 2009-09-25 | 2015-01-28 | 精工电子有限公司 | Semiconductor device |
| CN102034812A (en) * | 2009-09-25 | 2011-04-27 | 精工电子有限公司 | Semiconductor device |
| CN102623453A (en) * | 2011-01-27 | 2012-08-01 | 无锡华润华晶微电子有限公司 | Power device, preparation method and energy-saving electronic lighting circuit using the same |
| CN102623453B (en) * | 2011-01-27 | 2014-10-29 | 无锡华润华晶微电子有限公司 | Power device, preparation method and energy-saving electronic lighting circuit using the same |
| CN102254911A (en) * | 2011-07-13 | 2011-11-23 | 浙江大学 | Controlled silicon device provided with secondary conductive path and triggered with help of diodes |
| CN102254911B (en) * | 2011-07-13 | 2013-04-17 | 浙江大学 | Controlled silicon device provided with secondary conductive path and triggered with help of diodes |
| CN102543998A (en) * | 2012-02-20 | 2012-07-04 | 中国科学院微电子研究所 | Polycrystalline silicon series diode string and manufacturing method thereof |
| CN102544068A (en) * | 2012-03-09 | 2012-07-04 | 浙江大学 | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes |
| CN102593125A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Groove type MOS (metal oxide semiconductor) electrostatic discharge structure and integrated circuit |
| CN102544068B (en) * | 2012-03-09 | 2014-01-15 | 浙江大学 | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes |
| CN103972172A (en) * | 2013-02-01 | 2014-08-06 | 厦门博佳琴电子科技有限公司 | Diode selection element array structure and manufacturing method |
| CN103972172B (en) * | 2013-02-01 | 2016-10-05 | 厦门博佳琴电子科技有限公司 | A kind of diode selecting element arrays structure and manufacture method |
| CN105702674A (en) * | 2016-03-18 | 2016-06-22 | 江苏艾伦摩尔微电子科技有限公司 | Novel electrostatic discharge protection apparatus |
| CN105702674B (en) * | 2016-03-18 | 2019-01-04 | 江苏艾伦摩尔微电子科技有限公司 | A kind of electrostatic discharge protective device |
| CN111816650A (en) * | 2019-04-12 | 2020-10-23 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection structure and forming method thereof |
| CN111816650B (en) * | 2019-04-12 | 2023-05-26 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection structure and forming method thereof |
| CN111725305A (en) * | 2020-07-31 | 2020-09-29 | 华虹半导体(无锡)有限公司 | Semiconductor device and method for manufacturing the same |
| CN111725305B (en) * | 2020-07-31 | 2022-08-16 | 华虹半导体(无锡)有限公司 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100590875C (en) | 2010-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100590875C (en) | Polysilicon concatenating diode | |
| CN101281909B (en) | NMOS pipe built-in bidirectional thyristor electrostatic protection device | |
| CN100583429C (en) | PMOS pipe built-in bidirectional thyristor electrostatic protection device | |
| US7786504B2 (en) | Bidirectional PNPN silicon-controlled rectifier | |
| CN102956632B (en) | A kind of two-way SCR ESD-protection structure of low parasitic capacitance | |
| CN104716132B (en) | The thyristor and its circuit of a kind of low trigger voltage and high maintenance voltage | |
| CN102142440B (en) | Thyristor device | |
| CN102034858A (en) | Bidirectional triode thyristor for electrostatic discharge protection of radio frequency integrated circuit | |
| CN105655325A (en) | Electrostatic discharge protection circuit, and electrostatic discharge protection structure and manufacturing method thereof | |
| CN100470803C (en) | ESD protection circuit for enlarging the valid circulation area of the static current | |
| CN103165600B (en) | A kind of esd protection circuit | |
| CN110867487A (en) | Silicon controlled rectifier and manufacturing method thereof | |
| CN109742071A (en) | A kind of ESD protective device of SOI power switch | |
| CN108122904A (en) | A kind of esd protection structure | |
| CN102034814B (en) | Electrostatic discharge protective device | |
| CN103094278B (en) | The low pressure that PMOS embeds triggers the SCR device being used for esd protection | |
| CN100470804C (en) | A protection circuit for constructing ESD release channel with the polycrystalline silicon | |
| CN102169881A (en) | Power supply clamping structure method applied to high pressure process integrated circuit | |
| CN104269401A (en) | Novel ESD protection device based on SCR structure | |
| CN100530652C (en) | Controllable silicon used for electrostatic discharge protection | |
| CN100448007C (en) | Grid-shaped electrostatic discharge protection device | |
| CN201041806Y (en) | An ESD protection part for enlarging valid pass area of static current | |
| CN102270658B (en) | Low-trigger-voltage and low-parasitic-capacitance silicon controlled structure | |
| CN109300895B (en) | ESD protection device of LDMOS-SCR structure | |
| CN101814498B (en) | Structure with built-in NMOS auxiliary trigger controllable silicon |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100217 Termination date: 20110528 |