CN101277451B - Method, apparatus and system for data error correction - Google Patents
Method, apparatus and system for data error correction Download PDFInfo
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- CN101277451B CN101277451B CN 200810093944 CN200810093944A CN101277451B CN 101277451 B CN101277451 B CN 101277451B CN 200810093944 CN200810093944 CN 200810093944 CN 200810093944 A CN200810093944 A CN 200810093944A CN 101277451 B CN101277451 B CN 101277451B
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Abstract
Embodiment of the invention discloses a method, a device and a system of data error correction. The method comprises the following steps of: obtaining an output data speed of transport stream TS; the output data speed meets requirement of de-multiplexing; undergoing error correction for data to be corrected, and outputting the corrected data according to the output data speed. The embodiment of the invention obtains the output data speed of TS, undergoes error correction output treatment for the data to be corrected according to the output data speed, which accomplishes synchronization of decoding treatment, descrambling treatment and TS output treatment, so that the invention avoids speed conversion before outputting TS at the TS interface, so as to save a buffer for speed conversion, and reduce system cost.
Description
Technical field
The present invention relates to communication technical field, particularly a kind of methods, devices and systems of correcting data error.
Background technology
Along with the development of technology such as electronics, communication, the video broadcasting field, the simulation standard is to the inevitable trend that is converted into of digital standard.And the main target of DVB (Digital Video Broadcasting, digital video broadcasting) is exactly to seek a kind of digital television techniques that can all be suitable for all transmission mediums.Its design principle is to make system can transmit MPEG-2 (Moving Pictures ExpertsGroup-2 neatly, dynamic image expert group version 2) video, audio frequency and other data message, it is multiplexing to use unified MPEG-2 to transmit bit stream, use unified service information system, use unified scrambling system (cipher mode can be different), use unified RS (Reed-Solomon, Read-Solomon) sign indicating number fec systems, finally form a general digital television system.Different transmission mediums can be selected different modulation systems and channel coding method for use.All DVB series standard complete MPEG compatible-2 standards have been formulated decoder common interface standard, support condition simultaneously and have been received and provide characteristic such as Radio Data System.
In the existing technical scheme, decoder is taked modular mentality of designing, and FEC (Forward ErrorCoding, forward error correction coding) being divided into each submodule designs, wherein, the RS decoder designs as an independent module, and its input/output port is a Synchronization Design, and output speed is identical with input rate.Since error detection the time, mistake in computation position and wrong numerical value need the regular hour, the input data must carry out buffer memory to treat error correction, generally take the form of FIFO (First In First Out, first-in first-out) to carry out the delay of data.And the input data rate of the TS interface of FEC is a RS decoder output speed, and output speed is the speed of follow-up demultiplexing and source coding requirement, needs to carry out the format conversion of data rate before the output, therefore needs extra buffer to carry out the delay of data.
Therefore, the buffer memory that existing technical scheme is used is more, the system cost height.
Summary of the invention
The embodiment of the invention provides a kind of methods, devices and systems of correcting data error, to save buffer memory, reduces system cost.
For achieving the above object, the embodiment of the invention provides a kind of method of correcting data error on the one hand, may further comprise the steps:
Obtain the output data rate of transport stream TS, described output data rate is the speed that satisfies the demultiplexing requirement;
The data for the treatment of error correction are carried out error correction and exported the data of error correction according to described output data rate, and the described data for the treatment of error correction comprise the data of deinterleaving, comprising:
The data of deinterleaving are carried out error detection handle, the data that obtain error detection also write buffer memory with the data of described error detection;
From described buffer memory, read the data of described error detection according to described output data rate and carry out correction process, obtain the data of error correction;
According to described output data rate the data of described error correction are carried out scramble process, obtain the data of descrambling;
According to described output data rate the data of described descrambling are carried out serial parallel conversion and output TS.
On the one hand, the embodiment of the invention also provides a kind of decoder, comprising again:
Acquisition module is used to obtain the output data rate of transport stream TS, and described output data rate is the speed that satisfies the demultiplexing requirement;
Correction module, the data that are used for deinterleaving are just carried out the error detection processing, obtain the data of error detection; The output data rate that obtains according to described acquisition module carries out correction process with the data of described error detection, obtains the data of error correction; Send the data of described error correction according to described output data rate.
On the one hand, the embodiment of the invention also provides a kind of TS interface, comprising again:
Receiver module is used for receiving the data of descrambling according to output data rate;
Output module is used for according to described output data rate the data of the descrambling of described receiver module reception being carried out serial parallel conversion and output.
On the other hand, the embodiment of the invention also provides a kind of system of correcting data error, comprising: decoder, descrambler, TS interface and buffer;
Described decoder obtains the output data rate of transport stream TS, and described output data rate is the speed that satisfies the demultiplexing requirement; The data of deinterleaving are carried out error detection handle, obtain the data of error detection; According to described output data rate the data of described error detection are carried out correction process, obtain the data of error correction; Send the data of described error correction according to described output data rate;
Described descrambler is used for according to the output data rate of described TS the data of the error correction of described decoder output being carried out scramble process and being exported the data of descrambling;
Described TS interface is used for according to the output data rate of described TS the data of the descrambling of described descrambler output being carried out serial parallel conversion and output TS;
Described buffer is used to store the data for the treatment of error correction.
Compared with prior art, the embodiment of the invention has the following advantages: the embodiment of the invention is by obtaining the output data rate of TS, described output data rate is the speed that satisfies the demultiplexing requirement, the data for the treatment of error correction are carried out error correction and exported the data of error correction according to described output data rate, realized the combination of the output speed and the TS interface output speed of RS decoder, realized the synchronous of TS interface input and output rate, thereby avoided the rate transition of TS interface before output TS, therefore saved because of the required buffer of rate transition, reduced system cost.
Description of drawings
Fig. 1 is the data error-correcting method flow chart of the embodiment of the invention one;
Fig. 2 is that the correcting data error of the embodiment of the invention two is realized block diagram;
Fig. 3 is the data error-correcting method flow chart of the embodiment of the invention two;
Fig. 4 is the data error-correcting method flow chart of the embodiment of the invention three;
Fig. 5 is a kind of correcting data error system configuration schematic diagram of the embodiment of the invention four;
Fig. 6 is the another kind of correcting data error system configuration schematic diagram of the embodiment of the invention four.
Embodiment
Be described below in conjunction with accompanying drawing and implementation step embodiment the embodiment of the invention:
Be illustrated in figure 1 as the data error-correcting method flow chart of the embodiment of the invention one, specifically may further comprise the steps:
Step S101 obtains the output data rate of TS.For example, when needs output TS, obtain the output data rate of TS, described output data rate is the speed that satisfies the demultiplexing requirement.
Step S102 carries out the data for the treatment of error correction error correction and exports the data of error correction according to described output data rate.For example, after obtaining output data rate, from buffer memory, read the data of error detection according to described output data rate and carry out correction process, obtain the data of error correction, according to described output data rate the data of described error correction are carried out scramble process, obtain the data of descrambling, according to described output data rate the data of described descrambling are carried out serial parallel conversion and output then.
Above-mentioned data error-correcting method also can be before obtaining described output data rate, the data of deinterleaving are carried out EDC error detection and correction in the lump to be handled, obtain the data of error correction, and the data of error correction have been carried out buffer memory, and after obtaining described output data rate, directly the data that read error correction according to described output data rate from buffer memory are carried out subsequent treatment such as descrambling.
The embodiment of the invention is by obtaining output data rate, to treat that according to described output data rate the data of error correction carry out error correction output and handle, it is synchronous to have realized that decoding processing, scramble process and TS output are handled, thereby avoided the rate transition before the output TS, therefore saved because of the required buffer of rate transition, reduced system cost.
As shown in Figure 2, for the correcting data error of the embodiment of the invention two is realized block diagram, the FEC subsystem generally will pass through deinterleaving 205, RS decoding 201, descrambling 202 and TS output 203 in the DVB-S standard.Wherein, deciphered 201 o'clock carrying out RS, need to treat that the data of error correction carry out buffer memory 204.The embodiment of the invention is at DVB-C/S/T (DVB-Cable/Satellite/Terrestrial, wired/the satellite/terrestrial digital video broadcasting) the FEC subsystem of system is optimized, emphasis relates to RS decoding processing and TS output is handled, but mentality of designing of the present invention is not limited to DVB-C/S/T.
As shown in Figure 3, be the data error-correcting method flow chart of the embodiment of the invention two, the embodiment of the invention two is that example is described with DVB-S, RS decoding is handled be divided into erroneous calculations and error correction output two parts, wherein the error correction output specifically be may further comprise the steps by the output data rate control of TS:
Step S301 carries out error detection with the data of deinterleaving and handles and buffer memory.The data of the deinterleaving that receives are carried out error detection handle, mistake in computation position and wrong numerical value obtain the data of error detection, and the data of described error detection are carried out buffer memory.
Step S302 obtains the output data rate of TS.For example, when needs output TS, obtain the output data rate of TS, described output data rate is the speed that satisfies the demultiplexing requirement, and described output data rate can be configured as required.
Step S303 reads the data of error detection and carries out correction process from described buffer memory according to described output data rate.After obtaining described output data rate, from buffer memory, read the data of described error detection according to described output data rate and carry out correction process, obtain the data of error correction.
Step S304 carries out scramble process according to the described output data rate data of error correction, obtains the data of descrambling.
Step S305 carries out serial parallel conversion and output TS according to described output data rate with the data of described descrambling.
The embodiment of the invention is by obtaining the output data rate of TS, according to described output data rate with in the buffer memory the data of error detection carry out processing such as error correction, descrambling, then according to described output data rate output TS, it is synchronous to have realized that decoding processing, scramble process and TS output are handled, thereby avoided the rate transition before the dateout, therefore saved because of the required buffer of rate transition, reduced system cost.Simultaneously, the output data rate external controllable of RS decoder has strengthened RS decoder application flexibility; TS interface dateout is taked Synchronization Design, the data rate of the TS interface output mode with the data-signal of relative interior clock in system is exported, reduce by a clock zone, be very easy to intrasystem Time-Series analysis and placement-and-routing, reduced system cost.
As shown in Figure 4, data error-correcting method flow chart for the embodiment of the invention three, the embodiment of the invention embodiment of the invention is that the FEC subsystem at the DVB-C/S/T system is optimized equally, and emphasis relates to that RS decoding is handled and TS output processing, specifically may further comprise the steps:
Step S401 carries out EDC error detection and correction in the lump with the data of deinterleaving and handles, and obtains the data and the buffer memory of error correction.
Step S402 obtains the output data rate of TS.For example, when needs output TS, obtain the output data rate of TS, described output data rate is the speed that satisfies the demultiplexing requirement, and described output data rate can be configured as required.
Step S403 carries out scramble process according to the described output data rate data of error correction, obtains the data of descrambling.
Step S404 carries out serial parallel conversion and output TS according to described output data rate with the data of described descrambling.
The embodiment of the invention is carried out EDC error detection and correction in the lump with the data of deinterleaving and is handled data and the buffer memory that obtains error correction before obtaining the output data rate of TS.After obtaining the output data rate of TS, according to described output data rate the data of the error correction in the buffer memory are carried out exporting TS after scramble process and the serial parallel conversion process, it is synchronous to have realized that decoding processing, scramble process and TS output are handled, thereby avoided the rate transition before the dateout, therefore saved because of the required buffer of rate transition, reduced system cost.Simultaneously, the output data rate external controllable of RS decoder has strengthened RS decoder application flexibility.
As shown in Figure 5, a kind of correcting data error system configuration schematic diagram for the embodiment of the invention four comprises: decoder 1, descrambler 2, TS interface 3 and buffer 4.
Wherein, decoder 1 is used for reading the data for the treatment of error correction from buffer 4 and carries out correction process and export the data of error correction according to described output data rate, and described output data rate is the speed that satisfies the demultiplexing requirement.Described decoder 1 comprises the RS decoder.
Wherein, descrambler 2 is used for according to described output data rate the data of the error correction of decoder 1 output being carried out scramble process and being exported the data of descrambling.
Wherein, TS interface 3 is used for according to described output data rate the data of the descrambling of described descrambler output being carried out serial parallel conversion and output TS.
Wherein, buffer 4 is used to store the data for the treatment of error correction.
Wherein, decoder 1 comprises: acquisition module 11, be used to obtain the output data rate of TS, and described output data rate is the speed that satisfies the demultiplexing requirement.Correction module 12 is used for the data for the treatment of error correction are carried out correction process and exported the data of error correction according to described output data rate.
Wherein, above-mentioned correction module 12 further comprises: error detection submodule 121, and be used for that the data of deinterleaving are carried out error detection and handle, obtain the data of error detection.Error correction submodule 122, the data that are used for the error detection that the output data rate that obtains according to acquisition module 11 obtains error detection submodule 121 are carried out correction process, obtain the data of error correction.Send submodule 123, the data of the error correction that the output data rate transmission error correction submodule 122 that is used for obtaining according to acquisition module 11 obtains.Wherein, TS interface 3 comprises: receiver module 31 is used for receiving the data of descrambling according to output data rate.Output module 32 is used for according to described output data rate the data of the descrambling of receiver module 31 receptions being carried out serial parallel conversion and output.
Adopt above-mentioned correcting data error system, decoder 1 data of deinterleaving carries out error detection and handles, and obtains the data of error detection, and the data of described error detection are write buffer 4.Behind the data output rate that gets access to TS interface 3 (described output data rate is the speed that satisfies the demultiplexing requirement), decoder 1 carries out correction process from the data that buffer 4 reads described error detection, obtain the data of error correction, and send the data of described error correction according to described data output rate to descrambler 2.Descrambler 2 carries out scramble process according to the described output data rate data of error correction, obtains the data of descrambling, and according to described data rate the data of described descrambling is sent to TS interface 3.TS interface 3 carries out serial parallel conversion and output TS according to described output data rate with the data of described descrambling.
The correcting data error system of the embodiment of the invention is by obtaining the output data rate of TS, according to described output data rate with in the buffer memory the data of error detection carry out processing such as error correction, descrambling, then according to described output data rate output TS, it is synchronous to have realized that decoding processing, scramble process and TS output are handled, thereby avoided the rate transition before the dateout, therefore saved because of the required buffer of rate transition, reduced system cost.Simultaneously, the output data rate external controllable of decoder 1 has strengthened decoder 1 application flexibility; TS interface 3 dateouts are taked Synchronization Design, the data rate of the TS interface 3 output mode with the data-signal of relative interior clock in system is exported, reduce by a clock zone, be very easy to intrasystem Time-Series analysis and placement-and-routing, reduced system cost.
As shown in Figure 6, the another kind of correcting data error system configuration schematic diagram for the embodiment of the invention four comprises: decoder 1, descrambler 2, TS interface 3 and buffer 4.
Wherein, decoder 1 is used for reading the data for the treatment of error correction from buffer 4 and carries out correction process and export the data of error correction according to described output data rate, and described output data rate is the speed that satisfies the demultiplexing requirement.Described decoder 1 comprises the RS decoder.
Wherein, descrambler 2 is used for according to described output data rate the data of the error correction of decoder 1 output being carried out scramble process and being exported the data of descrambling.
Wherein, TS interface 3 is used for according to described output data rate the data of the descrambling of described descrambler output being carried out serial parallel conversion and output TS.
Wherein, buffer 4 is used to store the data for the treatment of error correction.
Wherein, decoder 1 comprises: acquisition module 11, be used to obtain the output data rate of TS, and described output data rate is the speed that satisfies the demultiplexing requirement.Correction module 12 is used for the data for the treatment of error correction are carried out correction process and exported the data of error correction according to described output data rate.
Wherein, above-mentioned correction module 12 further comprises: correction process submodule 124, and be used for that the data of deinterleaving are carried out EDC error detection and correction and handle, obtain the data of error correction.Data output sub-module 125, the data of the error correction that the output data rate transmission correction process submodule 124 that is used for obtaining according to acquisition module 11 obtains.
Wherein, TS interface 3 comprises: receiver module 31 is used for receiving the data of descrambling according to output data rate.Output module 32 is used for according to described output data rate the data of the descrambling of receiver module 31 receptions being carried out serial parallel conversion and output.
Adopt above-mentioned correcting data error system, decoder 1 data of deinterleaving carries out EDC error detection and correction and handles, and obtains the data of error detection, and the data of described error correction are write buffer 4.Behind the data output rate that gets access to TS interface 3 (described output data rate is the speed that satisfies the demultiplexing requirement), decoder 1 sends to descrambler 2 from the data that buffer 4 reads described error correction.Descrambler 2 carries out scramble process according to the described output data rate data of error correction, obtains the data of descrambling, and according to described data rate the data of described descrambling is sent to TS interface 3.TS interface 3 carries out serial parallel conversion and output TS according to described output data rate with the data of described descrambling.
The correcting data error system of the embodiment of the invention carries out EDC error detection and correction in the lump with the data of deinterleaving and handles data and the buffer memory that obtains error correction before obtaining the output data rate of TS.After obtaining the output data rate of TS, according to described output data rate the data of the error correction in the buffer memory are carried out exporting TS after scramble process and the serial parallel conversion process, it is synchronous to have realized that decoding processing, scramble process and TS output are handled, thereby avoided the rate transition before the dateout, therefore saved because of the required buffer of rate transition, reduced system cost.Simultaneously, the output data rate external controllable of decoder 1 has strengthened the decoder application flexibility.
The invention described above embodiment sequence number is not represented the quality of embodiment just to description.
It will be appreciated by those skilled in the art that the module in the device among the embodiment can be distributed in the device of embodiment according to the embodiment description, also can carry out respective change and be arranged in the one or more devices that are different from present embodiment.The module of the foregoing description can be merged into a module, also can further split into a plurality of submodules.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by hardware, also can realize by the mode that software adds necessary general hardware platform.Based on such understanding, technical scheme of the present invention can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
More than disclosed only be several specific embodiment of the present invention, still, the present invention is not limited thereto, any those skilled in the art can think variation all should fall into protection scope of the present invention.
Claims (7)
1. the method for a correcting data error is characterized in that, may further comprise the steps:
Obtain the output data rate of transport stream TS, described output data rate is the speed that satisfies the demultiplexing requirement;
The data for the treatment of error correction are carried out error correction and exported the data of error correction according to described output data rate, and the described data for the treatment of error correction comprise the data of deinterleaving, comprising:
The data of deinterleaving are carried out error detection handle, the data that obtain error detection also write buffer memory with the data of described error detection;
From described buffer memory, read the data of described error detection according to described output data rate and carry out correction process, obtain the data of error correction;
According to described output data rate the data of described error correction are carried out scramble process, obtain the data of descrambling;
According to described output data rate the data of described descrambling are carried out serial parallel conversion and output TS.
2. the method for a correcting data error is characterized in that, may further comprise the steps:
Obtain the output data rate of transport stream TS, described output data rate is the speed that satisfies the demultiplexing requirement;
The data of deinterleaving are carried out EDC error detection and correction handle, the data that obtain error correction also write buffer memory with the data of described error correction;
From described buffer memory, read the data of described error correction according to described output data rate and carry out scramble process, obtain the data of descrambling;
According to described output data rate the data of described descrambling are carried out serial parallel conversion and output TS.
3. a decoder is characterized in that, comprising:
Acquisition module is used to obtain the output data rate of transport stream TS, and described output data rate is the speed that satisfies the demultiplexing requirement;
Correction module is used for that the data of deinterleaving are carried out error detection and handles, and obtains the data of error detection; The output data rate that obtains according to described acquisition module carries out correction process with the data of described error detection, obtains the data of error correction; Send the data of described error correction according to described output data rate.
4. as decoder as described in the claim 3, it is characterized in that the data for the treatment of error correction comprise the data of deinterleaving, described correction module comprises:
The error detection submodule is used for that the data of deinterleaving are carried out error detection and handles, and obtains the data of error detection;
The error correction submodule, the data that are used for the error detection that the output data rate that obtains according to described acquisition module obtains described error detection submodule are carried out correction process, obtain the data of error correction;
Send submodule, be used for sending the data of the error correction that described error correction submodule obtains according to the output data rate that described acquisition module obtains.
5. as decoder as described in the claim 3, it is characterized in that described correction module also comprises:
The correction process submodule is used for that the data of deinterleaving are carried out EDC error detection and correction and handles, and obtains the data of error correction;
The data output sub-module is used for sending according to the output data rate that described acquisition module obtains the data of the error correction that described correction process submodule obtains.
6. as decoder as described in the claim 3, it is characterized in that described decoder comprises the RS decoder.
7. the system of a correcting data error is characterized in that, comprising: decoder, descrambler, TS interface and buffer;
Described decoder is used to obtain the output data rate of transport stream TS, and described output data rate is the speed that satisfies the demultiplexing requirement; The data of deinterleaving are carried out error detection handle, obtain the data of error detection; According to described output data rate the data of described error detection are carried out correction process, obtain the data of error correction; Send the data of described error correction according to described output data rate;
Described descrambler is used for according to described output data rate the data of the error correction of described decoder output being carried out scramble process and being exported the data of descrambling;
Described TS interface is used for according to described output data rate the data of the descrambling of described descrambler output being carried out serial parallel conversion and output TS;
Described buffer is used to store the data for the treatment of error correction.
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