CN101262004B - Phase change storage unit and method for dual shallow groove separated bipolar transistor selection - Google Patents
Phase change storage unit and method for dual shallow groove separated bipolar transistor selection Download PDFInfo
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- CN101262004B CN101262004B CN2008100359396A CN200810035939A CN101262004B CN 101262004 B CN101262004 B CN 101262004B CN 2008100359396 A CN2008100359396 A CN 2008100359396A CN 200810035939 A CN200810035939 A CN 200810035939A CN 101262004 B CN101262004 B CN 101262004B
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Abstract
The invention provides a phase change memory cell structure that is gated by bipolar transistors and isolated by double shallow trenches and a manufacturing method thereof. On a base of p-type or n-type conduction in a first conduction type, bit lines of a second conducting type with low resistance are utilized to serve as a collecting electrode of the bipolar transistors and the bit lines are separated by relatively deep shallow trench isolation (STI); a base electrode and an emitting electrode of the first conduction type are prepared above the bit lines, the bipolar transistors formed on the same bit line are separated by relatively shallow STI; finally, a phase change memory cell is prepared on each bipolar transistor. The bipolar transistors are manufactured and the phase change memory cell is prepared on each bipolar transistor largely by ion injection and regular semiconductor technique, and the memory cell is gated and operated by the bipolar transistors. Compared with the phase change memory cell with the existing structure, the phase change memory cell structure provided by the invention has high density and low manufacturing cost, and one bipolar transistor can correspond to a plurality of phase change memory cells.
Description
Technical field
The present invention relates to the simple eye structure and the manufacture method of phase-change memory device, or rather, relate to the phase-change memory cell and the method for the bipolar transistor selection of isolating based on dual shallow groove.Belong to the memory area in the microelectronics.
Background technology
Phase transition storage (PCM) is the focus of present nonvolatile memory research of new generation, has vast market prospect, it integrates high speed, high density, irradiation simple in structure, with low cost, anti-, advantage such as non-volatile, be at present by extensively good memory of future generation, it will have an opportunity to substitute present widely used flash memories, thereby occupy an important seat in the electronic memory field.
High density PCM is the important directions of present PCM development, and replace metal-oxide-semiconductor gating memory cell with bipolar transistor is a kind of effective way that improves memory density, because the area that descends bipolar transistor on year-on-year basis is less than metal-oxide-semiconductor, so the application of bipolar transistor in phase transition storage will improve the integrated level of PCM greatly, thereby make PCM more competitive.Samsung nearest in the past few years be devoted to always based on bipolar transistor selection phase transition storage research (people such as J.H.Oh, IEDM, 2006, p.49), and obtained significant achievement, and produced the device of 512M; However, in the research and patent of Samsung, all be to adopt the way of extension to make bipolar transistor, this way costs an arm and a leg, be unfavorable for reducing cost, so, if can provide cheaper structure of a kind of cost and manufacture method will increase its proper value greatly.The present invention intends providing a kind of structure of phase-changing memory unit of bipolar transistor of isolating (STI) based on dual shallow groove, and its manufacture method is easy, and is compatible fully with semiconductor technology, helps to reduce cost; And provide a kind of density higher 1B+nR structure, the density of further having promoted phase transition storage.
Summary of the invention
The object of the present invention is to provide the bipolar transistor selection phase-change memory cell of isolating based on dual shallow groove.
Another object of the present invention provides the manufacture method of described bipolar transistor selection phase-change memory cell of isolating based on dual shallow groove.
The phase-change memory cell structure of the bipolar transistor selection of isolating based on dual shallow groove, it is characterized in that in the substrate of first conduction type of p type conduction or n type conduction, utilize the collector electrode of the bit line of low-resistance second conduction type as bipolar transistor, above bit line, make the emitter of the base stage and first conduction type, on the bipolar transistor of making, make a plurality of phase-change memory cells of one or at least two afterwards; Adopt the dual shallow groove isolation technology, separate with darker shallow trench isolation between bit line and the bit line, between the transistor on the same bit line with more shallow shallow trench isolation separately.
By bipolar transistor phase-change memory cell is operated, utilized the difference of phase-change material phase transformation front and back resistance to carry out the storage of information.
Any in following 7 kinds of methods adopted in the making of the corresponding bipolar transistor structure of a described phase-change memory cell:
Method A:
A) on the substrate of first conduction type of p type conduction or n type conduction, form low-resistance bit line of second conduction type with ion implantation and photoetching process;
B) continue on the low resistance bit line of second conduction type that step a makes, to make the base stage of second conduction type and the emitter of first conduction type, form bipolar transistor with the bit line of above-mentioned second conduction type with semiconductor technology and ion implantation;
C) with the dual shallow groove isolation technology bit line and bit line are isolated, with the transistor isolation of same bit line top, make phase-change memory cell at last on bipolar transistor, phase-change material is sandwiched in the middle of the two-layer electrode;
Method B:
A) on the substrate of first conduction type of p type conduction or n type conduction, form low-resistance bit line of second conduction type with ion implantation and photoetching process;
B) continue to make the base stage of second conduction type and the emitter of first conduction type with ion implantation on the low resistance bit line of second conduction type that step a makes, the bit line of second conduction type made from step a forms bipolar transistor;
C) with isolated each bit line of dual shallow groove isolation technology, and each transistor on the isolated same bit line, phase-changing memory unit on bipolar transistor, made afterwards;
D) side that contacts with bipolar transistor of phase-change material does not have electrode, but directly contact with bipolar transistor, the silicide that the bipolar transistor surface forms is as heating electrode, perhaps adopting the bipolar transistor surface is heating electrode through the silicon layer of overdoping, and perhaps adopting the electrode of bipolar transistor surface additional deposition is heating electrode;
Method C:
A) on the substrate of first conduction type of p type conduction or n type conduction, inject and photoetching process forms low-resistance bit line of second conduction type with ion;
B) use the semiconductor technology formation center on the bit line of second conduction type that step a makes that comprises ion implantation to fill the annular bipolar transistor of medium;
C) with isolated respectively each bit line of dual shallow groove isolation technology, and each transistor on the isolated same bit line, above annular bipolar transistor, make phase-changing memory unit at last;
D) filled the annular bipolar transistor of medium, with vertical view after the electrode contact area shape deduction medium part of phase-change material below be annular; Phase-change material is clipped between the two-layer electrode, perhaps is clipped between electrode and the bipolar transistor; In the reversible variation that realizes under the effect of heat between high resistance and the low resistance;
Method D:
A) in the substrate of first conduction type of p type conduction or n type conduction, inject and mix with ion, on substrate, form the material layer of different conduction-types successively, down be followed successively by the first conduction type heavily doped layer from substrate surface, the little doped layer of second conduction type, the second conduction type heavily doped layer, the material layer after above-mentioned which floor doping forms the pn knot;
B) in the substrate of the formation pn knot that step a makes, prepare electrode, sediment phase change material layer and electrode layer successively; Carve flagpole pattern thereon by photoetching process again, the degree of depth of etching forms darker shallow trench isolation in the dual shallow groove isolation till the second conduction type heavily doped layer has been carved;
C) pass through photoetching process again, with the flagpole pattern etching described in the step b separately, etching depth is till having carved the little doped layer of first conduction type, form more shallow shallow trench isolation in the dual shallow groove isolation, form independently unit, described separate unit comprises the memory cell of bipolar transistor and its top;
D) carry out the fill process of medium again, form dual shallow groove and isolate bit line and bit line isolation, and each transistor isolation on the same bit line, and draw word line and bit line;
Method E:
A) on the substrate of first conduction type of p type conduction or n type conduction, inject and mix with ion, form the material layer of different conduction-types successively, substrate surface after mixing down is followed successively by the first conduction type heavily doped layer, the little doped layer of second conduction type, the second conduction type heavily doped layer;
B) film of the continuation deposition of electrode material and first conduction type in the substrate that step a makes; Prepare separate unit by semiconductor technology;
C) produce aperture wide at the top and narrow at the bottom with etching method again and be used for sediment phase change material and electrode;
D) produce phase-change memory cell at last with small area of contact.
Method F:
A) in the substrate of first conduction type of p type conduction or n type conduction, inject the material layer that forms different conduction-types successively with ion, down be followed successively by the first conduction type heavily doped layer from substrate surface, the second conduction type lightly-doped layer, the second conduction type heavily doped layer, and these three layers of dopant materials form the pn knot;
B) continue deposition of electrode material in the substrate that step a makes, and coat photoresist;
C) prepare figure by semiconductor technology again, by the twice photoetching process, preparation darker shallow trench isolation in first road is isolated each bit line; The second road photoetching lines form more shallow shallow trench isolation perpendicular to the first road shallow trench isolation, are used for isolated each transistor;
D) afterwards, do not remove the direct deposition medium material of photoresist, after polishing after the deposition, again photoresist is removed;
E) use side wall technology manufacturing cell device at last, help to reduce the contact area of phase-change material and heating electrode;
Method G:
A) in the substrate of first conduction type of p type conduction or n type conduction, inject the material layer that forms different conduction-types successively with ion, substrate after the doping down is followed successively by the first conduction type heavily doped layer from the surface, the little doped layer of second conduction type, the second conduction type heavily doped layer, above-mentioned three layers form the pn knot; And in the substrate of above-mentioned making, deposit the electrode material of the first kind again;
B) prepare flagpole pattern by semiconductor technology again, etching depth is until the substrate of first conduction type; Remove photoresist, deposition first kind dielectric material has formed darker shallow trench isolation after the deposition, each bit line is separated; After polishing then, finish up to first kind material removal medium with first kind electrode material top;
C) continue the sediment phase change material and the second type electrode material, photoetching process forms lines crossing with above-mentioned dark STI but that do not overlap, etching depth is up to the second conduction type low doped layer etching is finished, form more shallow shallow trench isolation, each transistor of same bit line top is separated, and after the etching the second type electrode just as word line;
D) the deposition second type media material forms the dual shallow groove isolation structure, polishes laggard line lead.
The described second conduction type low-resistance bit line adopts ion implantation to mix and get with the photoetching legal system.
The phase-change material of the phase-change memory cell for preparing among described method C, D, E, F or the G is clipped between the two-layer electrode or is clipped between electrode and the bipolar transistor; In the reversible variation that realizes under the effect of heat between high resistance and the low resistance.
A kind of in following 2 kinds of methods adopted in the making of described two or at least two s' the corresponding bipolar transistor of a plurality of phase-change memory cells:
Method A:
A) in the substrate of first conduction type of p type conduction or n type conduction, inject and other semiconductor technologies form low-resistance bit line of second conduction type with ion;
B) on the bit line of above-mentioned second conduction type, make the base stage of second conduction type and the emitter of first conduction type with semiconductor technology and ion implantation, form the annular bipolar transistor of center filled media with bit line as collector electrode;
C) by the dual shallow groove isolation technology each bit line is separated, and each transistor of same bit line top is separated;
D) above an annular bipolar transistor, make several phase-change memory cells more than two or two at last;
Method B:
A) in the substrate of first conduction type of p type conduction or n type conduction, inject and other semiconductor technologies form low-resistance bit line of second conduction type with ion;
B) on the bit line of second conduction type that step a makes, make the base stage of second conduction type and the emitter of first conduction type with ion implantation, formed bipolar transistor;
C) by the dual shallow groove isolation technology each bit line is separated, and each transistor of same bit line top is separated;
D) expose transistor after the polishing, the transistor center is emptied with semiconductor technology;
E) successive sedimentation electrode and oxide carry out chemico-mechanical polishing then, have just formed annular electrode;
F) above an annular bipolar transistor, make several phase-change memory cells more than two or two at last.
The described second conduction type low-resistance bit line adopts ion implantation to mix and get with the photoetching legal system.
The phase-change material of the phase-change memory cell of preparation is clipped between the two-layer electrode or is clipped between electrode and the bipolar transistor, in the reversible variation that realizes under the effect of heat between high resistance and the low resistance.
Among the disclosed embodiment provided by the invention, relate to and utilize semiconductor technology above the solid bipolar transistor that produces, to make phase change memory cell device; Phase-change memory cell in further embodiments is that preparation is on the annular transistor of middle filled media.
Among the embodiment provided by the invention, the preparation method of annular electrode is methods such as etching; In further embodiments, the annular electrode manufacture method is depositing electrode and a dielectric material in aperture, forms after chemico-mechanical polishing.
In a word, among the embodiment provided by the invention, a bipolar transistor correspondence a phase-change memory cell, then is that a bipolar transistor correspondence a plurality of phase-change memory cells in further embodiments.Described bipolar transistor can replace with diode, and the employing diode then can be save the little doped layer of second conduction type between the second conduction type heavily doped layer low resistance bit line and the first conduction type heavily doped layer, thereby can save relevant processing step.By phase-change memory cell provided by the invention, to compare with phase-change memory cell in the past, density is higher, and cost of manufacture is cheap.
Description of drawings
Fig. 1 embodiment of the invention 1 is provided, the schematic cross-section of the memory cell structure that relates to.
Fig. 2 A-2G is the schematic diagram of fabrication technology that middle memory cell embodiment illustrated in fig. 1 is shown.Wherein Fig. 2 A is the heavy doping bit line sectional view that forms after ion injection and the etching; Fig. 2 B be with Fig. 2 A corresponding bit lines etching after vertical view; Fig. 2 C is the bipolar transistor unit sectional view of making on the bit line; Fig. 2 D ion injects and forms the bit line lead-in wire; Fig. 2 E filled media is polished, and carries out silication again, again polishing; Fig. 2 F sediment phase change material and electrode, photoetching forms memory cell; Fig. 2 G, the final structure that forms.
Fig. 3 A embodiment of the invention 2 is provided, and relates to the sectional view based on the phase-change memory cell of annular bipolar transistor selection, and phase-change material is clipped between top electrode and the bipolar transistor among this figure.Fig. 3 B is the sectional view of being got along the 1-1 line among Fig. 3 A, and bipolar transistor is a loop configuration.
Fig. 4 is based on the schematic diagram of fabrication technology of the embodiment 2 of the memory cell of annular bipolar transistor.Wherein Fig. 4 A is the heavy doping bit line sectional view that forms after ion injection and the etching; Fig. 4 B be with Fig. 4 A corresponding bit lines etching after vertical view; Fig. 4 C is the bipolar transistor unit sectional view of making on the bit line; Fig. 4 D, filled media is drawn bit line; Fig. 4 E, CVD depositing electrode and insulating medium layer; Fig. 4 F, CMP (Chemical Mechanical Polishing) process forms annular electrode; Fig. 4 G, the vertical view after the CMP (Chemical Mechanical Polishing) process; Fig. 4 H prepares phase-change memory cell; Fig. 4 I, the final device architecture schematic diagram that forms.
The sectional view of the embodiment 4 of Fig. 5 A 1BnR structure provided by the present invention memory cell structure, the phase-change material of present embodiment is clipped between the electrode.Respectively 2-2 along the line among Fig. 5 A shown in Fig. 5 B and the 5C, the vertical view in the cross section that 3-3 got.
Fig. 6 is the another kind of schematic cross-section of the 1BnR structure memory cell shown in the embodiment 4, and the phase-change material of present embodiment is clipped between electrode and the bipolar transistor.
Fig. 7 A-7F is the schematic diagram of fabrication technology of the memory cell structure shown in the embodiment 5.Wherein, the bit line of 7A for making, Fig. 7 B are the vertical view after the bit line preparation; The sectional view that 5-5 along the line is got in Fig. 7 B is still shown in Fig. 7 A, and the sectional view that Fig. 7 C is got for 4-4 along the line among Fig. 7 B, 7D is once more the vertical view of photoetching process etching figure, the sectional view that 7E is got for 6-6 along the line among Fig. 7 D, and the sectional view that 7-7 along the line is got in Fig. 7 D is still as Fig. 7 C institute.
Fig. 8 A-8F is the schematic diagram of fabrication technology of memory cell among the embodiment 6.Fig. 8 A is ion injection, electro-deposition, gluing, and photoetching forms the sectional view of the x axle behind the bit line; Fig. 8 B is the sectional view of the y axle corresponding with 8A; Fig. 8 C, the deposition dielectric, and draw bit line; Fig. 8 D removes photoresist 55, and side wall technology forms side wall; Fig. 8 E, sediment phase change material in aperture, deposition materials, etching forms memory cell; Fig. 8 F, lead-in wire.
Fig. 9 A-9G is the schematic diagram of fabrication technology of memory cell among the embodiment 7.Wherein Fig. 9 A is the axial sectional view of x after bit line is made, and Fig. 9 B is the vertical view after bit line is made, and Fig. 9 C is the sectional view that 8-8 along the line is got among Fig. 9 B (corresponding and Fig. 9 A is the axial sectional view of y), Fig. 9 D, deposition medium material, polishing, sediment phase change material and electrode more again; Fig. 9 E, photoetching forms flagpole pattern; Fig. 9 F is the sectional view that 9-9 along the line is got among Fig. 9 E, and Fig. 9 G is the sectional view that Fig. 9 E 10-10 along the line is got.
Figure 10 A-10G is the schematic diagram of fabrication technology of memory cell among the embodiment 8.Wherein Figure 10 A is the axial sectional view of x after bit line is made, Figure 10 B is the vertical view after bit line is made, Figure 10 C is the sectional view that A-A along the line is got among Figure 10 B (corresponding and Figure 10 A is the axial sectional view of y), Figure 10 D, the deposition medium material, polish again, again sediment phase change material and electrode; Figure 10 E, photoetching forms flagpole pattern; Figure 10 F is the sectional view that B-B along the line is got among Figure 10 E, and Figure 10 G is the sectional view that Figure 10 E C-C along the line is got.
Embodiment
Embodiment 1
Shown in Figure 1 is the sectional view of an embodiment memory cell, in order to make phase-change memory cell shown in Figure 1, at first, the conductive formation that mixes in forming on silicon substrate by ion implantation; Carve the silicon lines, and form bit line, etching depth forms darker shallow trench isolation (STI) up to above-mentioned doped layer etching is finished; Be infused in the silicon material layer that the specific region forms two-layer different conduction-types by ion again; On bit line, prepare bipolar transistor by photoetching process,, form more shallow STI; At last above bipolar transistor, make phase-change memory cell, form basic memory device structures.
Substrate as first conduction type can be the p type or is the n type, is example with p type substrate for convenience of description at this.Fig. 2 A is to shown in the 2G being concrete manufacturing process embodiment illustrated in fig. 1.(1) shown in Fig. 2 A, on the silicon substrate 11 that the p type mixes, form the heavily doped low resistance bit line 12 of a series of n types with ion implantation or other semiconductor technologies, vertical view such as Fig. 2 B, wherein 81 is darker STI, 80 is the silicon lines that etch.(2) continue to etch figure, the method for utilizing ion to inject forms n type weak doping layer 13 and heavy doping p type layer 14, has promptly formed bipolar transistor with n type low resistance bit line, and the cross section is shown in Fig. 2 C.(3) inject the heavily doped lead-in wire 21 of formation n type by ion, shown in Fig. 2 D.(4) filled media material forms dual shallow groove and isolates, and form silicide 15 above bipolar transistor, as being shown as CoSi in the present embodiment
x, after polishing, form the structure shown in Fig. 2 E.(5) above bipolar transistor, deposit bottom electrode, phase-change material and top electrode successively, by the structure of photoetching formation as Fig. 2 F.(6) at last by the deposition of dielectric layer, ways such as glossing and photoetching form Fig. 2 G structure, and are just shown in Figure 1.
Embodiment 2
It shown in Fig. 3 A the improvement that Fig. 2 G is prepared bipolar transistor structure, after preparing the bipolar transistor shown in Fig. 2 C, form the bipolar transistor of hollow by semiconductor technology, and the space that forms in the bipolar transistor carried out the filling of dielectric material 26, having formed the center by chemical mechanical polishing method again is the ring-type bipolar transistor of medium 26.Present embodiment and embodiment 1 another difference shown in Figure 1 also are there is not the additional deposition electrode layer between phase-change material and bipolar transistor, but silicon after directly usefulness is mixed or silicide are as heating electrode.The thin layer silicide 27 that forms on annular bipolar transistor injects by ion or diffusion obtains, and it is compared with the W metal electrode lower conductivity and lower thermal conductivity.Be along the obtained sectional view of 1-1 line shown in Fig. 3 B in Fig. 3 A interface.
First conductivity type substrate among this embodiment is an example with the p type still.To the structure shown in the embodiment 2
Form the thicker heavily doped conductive formation of n type with ion implantation on p type substrate, sectional view is shown in Fig. 4 A;
Carve figure with photoetching process, vertical view is shown in 4B, and wherein 80 are the silicon lines that etch, and 81 be the direct darker STI of the bit line that forms, and purpose is that each bit line is separated;
Utilize ion implantation and semiconductor technology to form bipolar diode, shown in Fig. 4 C;
The filled media material forms STI, and wherein more shallow STI separates the bipolar transistor on the same bit line, and forms groove on transistor, shown in Fig. 4 D;
CVD method depositing electrode layer 91 and dielectric layer 92 are shown in Fig. 4 E;
After the chemico-mechanical polishing, shown in Fig. 4 F, just formed annular electrode; Vertical view is shown in Fig. 4 G.
Make phase-change memory unit element, shown in Fig. 4 H;
Lead-in wire, the final devices cellular construction is shown in Fig. 4 I.
It shown in Fig. 5 A the unit component sectional view of another embodiment.
In the present embodiment, etching several junior units (30-32 layer) behind depositing electrode, phase-change material and the electrode successively above the bipolar transistor 41, so a bipolar transistor just can several phase-changing memory units of gating.
Be respectively along the vertical view of 2-2 and 3-3 shown in Fig. 5 B and the 5C among Fig. 5 A.From Fig. 5 C, can see, not link to each other mutually between several memory cell 30-32.Device cell among Fig. 5 A is the deposition by medium 34 at last, lead-in wire 33 and 37, and electrode 38 and 39 is made and is finished at last.
And the difference of Fig. 6 and Fig. 5 A is do not have depositing electrode layer 30 between phase-change material layers and the annular bipolar transistor.
Form two STI among Fig. 6 and Fig. 5 A, each bit line separates with darker shallow trench isolation, and the transistor of same bit line top with more shallow shallow trench isolation separately.
First conductivity type substrate among this embodiment is an example with the p type still.
On the silicon substrate 42 of p type, by the layer 43 of the heavily doped low-resistivity of ion implantation formation n type, n light dope 44 and p type heavy doping 45; Form the cross section shown in Fig. 7 A by depositing electrode layer 46, phase-change material layers 47 and electrode layer 48 again.
Etch the figure of lines 49 by photoetching process, be parked in 42 layers of top behind the intact heavily doped silicon layer 43 of n type of etching, vertical view is shown in Fig. 7 B, form darker shallow channel 82 after the etching, among Fig. 7 B along the cross section of 4-4 direction shown in Fig. 7 C, darker shallow trench isolation purpose is that bit line is separated, and among Fig. 7 B along the cross section of 5-5 direction still shown in Fig. 7 A.
Etch figure 50 by photoetching process again, be parked on the n type heavy doping line 43 behind the intact lightly doped silicon layer 44 of n type of etching, form more shallow STI 83, the purpose of more shallow STI is that the different transistor on the same bit line is separated, vertical view is shown in Fig. 7 D, among Fig. 7 D along the cross section of 6-6 direction shown in Fig. 7 E, and among Fig. 7 B along the cross section of 7-7 direction still shown in Fig. 7 C.
By drawing of electrode 51, the deposition of medium 52 and CMP (Chemical Mechanical Polishing) process form two STI, deposit top electrode at last, have formed metal lead wire 53 by photoetching process, and final memory cell structure is shown in Fig. 7 F.Annotate: do not draw the electrode of bit line 43 in the present embodiment, do not have but do not represent.
Embodiment 6
First conductivity type substrate among this embodiment is an example with the p type still.
On the silicon substrate of p type, form middle n type doped layer, n light dope and the heavy doping of p type by ion implantation; By depositing electrode layer 54, resist coating layer 55 forms the cross section shown in Fig. 8 A again.Photoetching process etches bit line, and continues to produce the structure shown in Fig. 8 B, does not remove photoresist 55, and the deposition medium material 59 subsequently, forms two STI, photoetching extraction electrode 60, by the sectional view that forms after the chemico-mechanical polishing shown in Fig. 8 C.With glue 55 flush awaies, again with publish picture dielectric sidewall 61 among the 8D of side wall prepared.
Sediment phase change material 62 and top electrode 63 form the sectional view shown in Fig. 8 E by photoetching.Lead-in wire 64 is made electrode 65 and 66, and the sectional view of the unit component that finally obtains is shown in Fig. 8 F.
Embodiment 7
Clear in order to explain equally, first conductivity type substrate among this embodiment is defined as the p type.
On the silicon substrate of p type, form middle n type doped layer, n light dope and the heavy doping of p type by ion implantation; By depositing electrode layer 67, form the cross section shown in Fig. 9 A again.
Photoetching process etches the lines 68 of electrode material 67, shown in Fig. 9 B, is the sectional view of being got along the 8-8 line among Fig. 9 B shown in Fig. 9 C, can see that etching technics is parked on the p type substrate, forms darker STI.
Fill STI 69, be ground to electrode layer 68 by chemico-mechanical polishing again and stop, sediment phase change material layer 70, excessive layer 71 and upper electrode layer 72, the cross section is shown in Fig. 9 D.
Last deposition medium with each memory cell extraction electrode, and is drawn bit line by semiconductor technology simultaneously.
Present embodiment is for making the method that pn ties the phase transition storage of gating.
On the silicon substrate of p type, form middle n type doped layer and p type doped layer by ion implantation; By depositing electrode layer 67, form the cross section shown in Figure 10 A again.
Photoetching process etches the lines 68 of electrode material 67, shown in Figure 10 B, is the sectional view of being got along the A-A line among Figure 10 B shown in Figure 10 C, can see that etching technics is parked on the p type substrate, forms darker STI.
Fill STI 69, be ground to electrode layer 68 by chemico-mechanical polishing again and stop, sediment phase change material layer 70, excessive layer 71 and upper electrode layer 72, the cross section is shown in Figure 10 D.
Last deposition medium with each memory cell extraction electrode, and is drawn bit line by semiconductor technology simultaneously.
In sum, the invention provides a kind of phase-changing memory unit device and manufacturing process thereof of bipolar transistor selection of dual shallow trench isolation.Although only describe some preferred embodiment in detail, obvious for those skilled in the art, under the situation that does not depart from the scope of the present invention that defines by claims, can carry out some improvement and variation.Such as claim and bipolar transistor among the embodiment are changed into PN junction all is conspicuous.
Claims (5)
1. the phase-change memory cell structure of the bipolar transistor selection of isolating based on dual shallow groove, in the substrate of first conduction type of p type conduction or n type conduction, utilize the collector electrode of the bit line of low-resistance second conduction type as bipolar transistor, above bit line, make the emitter of the base stage and first conduction type, it is characterized in that on the bipolar transistor of making, making at least two phase-change memory cells; Adopt the dual shallow groove isolation technology, separate with darker shallow trench isolation between bit line and the bit line, between the transistor on the same bit line with more shallow shallow trench isolation separately.
2. by the phase change memory unit structure of the described bipolar transistor selection of isolating based on dual shallow groove of claim 1, it is characterized in that phase-change memory cell being operated, utilize the difference of phase-change material phase transformation front and back resistance to carry out the storage of information by bipolar transistor.
3. the method for preparing the phase-change memory cell structure of bipolar transistor selection of isolating based on dual shallow groove as claimed in claim 1, the making that it is characterized in that the corresponding bipolar transistor of described at least two phase-change memory cells adopt a kind of in following 2 kinds of methods:
Method A:
A) in the substrate of first conduction type of p type conduction or n type conduction with comprising that the semiconductor technology of ion implantation forms low-resistance bit line of second conduction type;
B), form the annular bipolar transistor of center filled media with bit line as collector electrode with comprising that the semiconductor technology of ion implantation makes the base stage of second conduction type and the emitter of first conduction type on the bit line of above-mentioned second conduction type;
C) by the dual shallow groove isolation technology each bit line is separated, and each transistor of same bit line top is separated;
D) above an annular bipolar transistor, produce at least two above phase-change memory cells at last;
Method B:
A) in the substrate of first conduction type of p type conduction or n type conduction with comprising that the semiconductor technology of ion in being infused in forms low-resistance bit line of second conduction type;
B) use ion implantation at step a, make the base stage of second conduction type and the emitter of first conduction type on the bit line of second conduction type of making, formed bipolar transistor;
C) by the dual shallow groove isolation technology each bit line is separated, and each transistor of same bit line top is separated;
D) expose transistor after the polishing, the transistor center is emptied with semiconductor technology;
E) successive sedimentation electrode and oxide carry out chemico-mechanical polishing then, form annular electrode;
F) above an annular bipolar transistor, produce at least two above phase-change memory cells at last.
4. by the described method of claim 3, it is characterized in that the described second conduction type low resistance bit line adopts ion implantation to mix and get with the photoetching legal system.
5. by the described method of claim 3, the phase-change material that it is characterized in that the phase-change memory cell for preparing is clipped between the two-layer electrode or is clipped between electrode and the bipolar transistor, in the reversible variation that realizes under the effect of heat between high resistance and the low resistance.
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|---|---|---|---|---|
| US8030635B2 (en) * | 2009-01-13 | 2011-10-04 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
| US8501574B2 (en) | 2009-10-07 | 2013-08-06 | Macronix International Co., Ltd. | Resistive memory device and manufacturing method thereof and operating method thereof |
| CN102044491B (en) * | 2009-10-19 | 2014-08-06 | 旺宏电子股份有限公司 | Resistance type memory device, manufacturing method and operating method thereof |
| CN102544076A (en) * | 2010-12-23 | 2012-07-04 | 中国科学院微电子研究所 | Resistive random access memory (RRAM) gated by bipolar transistor, RRAM array and manufacturing method for RRAM |
| CN102437179B (en) * | 2011-12-07 | 2014-03-26 | 中国科学院上海微***与信息技术研究所 | Layout structure of total dose radiation hardening submicron device |
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2008
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