CN101237440A - A data interweaving method and device - Google Patents
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Abstract
The invention discloses a data interleaved technique and a device thereof, which is used to improved the interleaved performance in the interleaved process. In the invention, two or more than two interleaved devices are respectively provided with different interleaved patterns; moreover, in the interleaved process, the two or more than two interleaved devices respectively interleaves the inputted data according to the configured interleaved patterns. As for the different parts of the target position of the data at the same defined initial position in the two or more than two interleaved patterns, the interleaved gain is generated by adopting the technical proposal of the invention after two bits with same input sequences are respectively interleaved by the two or more than two interleaved devices, that is, the distance of the two bits are changed, thereby improving the interleaved performance in the interleaved process.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of deinterleaving method and device of data.
Background technology
HSDPA (High Speed Downlink Packet Access, the high speed downlink packet access) the descending Radio Transmission Technology as a kind of enhancing was introduced in 3GPP (3rd GenerationPartnership Project in 2002, third generation collaborative project) the 5th edition (Release 5, abbreviation " R5 ") (Release 6 in and 3GPP the 6th edition, abbreviation " R6 ") carried out further improvement in, owing to adopted link adaptation techniques based on Adaptive Modulation and Coding, HARQ (Hybrid automatic repeat request based on physical layer retransmission and soft merging, mix automatic repeat requests), quick multi-user's packet scheduling, key technologies such as the short frame of 2ms, has the spectrum efficiency height, downlink transfer speed is big, remarkable advantages such as propagation delay time is little, thus can provide effective twelve Earthly Branches to hold to Packet data service.
E-DCH (Enhanced Dedicated Transport Channel, the enhancing special uplink channel) is called HSUPA (High Speed Uplink Packet Access again, high speed uplink packet inserts), it is the Radio Transmission Technology of 3GPP another enhancing of introducing in Release 6 after in Release 5, introducing HSDPA, owing to adopted up fast packet scheduling based on Node B (Node B), key technologies such as quick HARQ and the short frame of 2ms, E-DCH has the spectrum efficiency height, uplink speed is fast, remarkable advantages such as propagation delay time is little, thus the real-time game business more effectively supported, file is uploaded, grouping such as broadband multimedia services data service is used.
At present, at HS-DSCH (High Speed Downlink Shared Channel, high speed descending sharing channel) in the code multiplexing process, the 2ms TTI of HS-DSCH (Transmission Time Interval, Transmission Time Interval) it is fast to carry 1 data at most, and each HS-DSCH data block of the multiplexing chain of input coding is through being mapped to the HS-DSCH subframe of 3 time slots behind code multiplexing.The code multiplexing process of HS-DSCH mainly comprises following several steps: transmission block increases the cutting apart of cyclic redundancy check information, bit scramble, encoding block, chnnel coding, HARQ (Hybrid automatic repeat request, mix automatic repeat requests), physical channel segmentation, interweave, 16QAM (Quadrature Amplitured Modulation, quadrature amplitude modulation) constellation reorganization, physical channel mapping.
When interweaving in the code multiplexing process of HS-DSCH, the interleaving process of each physical channel is independent.The bit sequence (being data) that is input to block interleaver is u
P, 1, u
P, 2, u
P, 3..., u
P, UWherein p is physical channel (PhCH, Physical Channel) number, if the modulation system that the code multiplexing process of HS-DSCH adopts is the 16QAM modulation, U=1920 then adopts the interleaver of two same sizes, is R2 * C2=32 * 30 at present, be line number R2=32, the interleaver of columns C2=30.The bit sequence of physical channel segmentation module output is cut apart bit u in twos between interleaver
P, kAnd u
P, k+1Send to first interleaver, bit u
P, k+2And u
P, k+3Send to second interleaver, the output bit sequence of two interleavers according to the order combination in twos that distributes, is specially bit v again
P, kAnd v
P, k+1From the output of first interleaver, and bit v
P, k+2And v
P, k+3From second interleaver output, k mod 4=1 herein, promptly k is 1 divided by 4 remainders, and k is a positive integer, and later bit sequence is by that analogy.
As seen, when adopting the 16QAM modulation system, adopt the interleaver of two same sizes (R2 * C2=32 * 30), from the bit v of first interleaver output
P, kAnd v
P, k+1Because of having the gain that interweaves, from the bit v of second interleaver output through interweaving of first interleaver
P, k+2And v
P, k+3Because of having the gain that interweaves through interweaving of second interleaver.But because two interleavers interweave according to identical rule, so v
P, k+2With v
P, kBetween the gain that do not interweave, v
P, k+3With v
P, k+1Between the gain that do not interweave, that is, and through after interweaving, u
P, kAnd u
P, k+2Distance do not change.Also exist in the interlace operation of similar problem in E-DCH.
Summary of the invention
The embodiment of the invention provides a kind of deinterleaving method and device of data, in order to improve the felt properties of interleaving process.
In order to solve the problems of the technologies described above, the embodiment of the invention provides a kind of deinterleaving method of data, may further comprise the steps:
For two or more interleavers dispose the different patterns that interweaves respectively; And
When interweaving, described two or more interleavers carry out interlace operation according to the pattern that interweaves for its configuration to the input data respectively.
The present invention also provides a kind of interlaced device, and described interlaced device comprises draws together two or more interleavers and configuration module, wherein:
Described interleaver is used for according to the pattern that interweaves of configuration the input data being carried out interlace operation;
Described configuration module is used to described two or more interleavers to dispose the different patterns that interweaves respectively.
The technical scheme that adopts the embodiment of the invention to provide, in two or more patterns that interweave, the different part in target location of the data that the definition initial position is identical, identical two bits of input sequence are respectively through after the interweaving of two or more interleavers, can produce the gain that interweaves, promptly variation has taken place in the distance of these two bits, thereby can improve the felt properties of interleaving process.
Description of drawings
The interweave flow chart of Fig. 1 in first interleaver, carrying out in the embodiment of the invention;
Fig. 2 is the interlaced device block diagram of the embodiment of the invention.
Embodiment
The embodiment of the invention is an example to be applied in HS-DSCH and E-DCH, but is not limited to be applied in the code multiplexing process of HS-DSCH and E-DCH, and other process or device that relates to a plurality of interleavers is all similar with it.
Below in conjunction with accompanying drawing the embodiment of the invention is done description further.
Embodiment one
In embodiment one, code multiplexing process with the HS-DSCH that adopts the 16QAM modulation is an example, in this process, adopt the interleaver of two same sizes that input bit is interweaved, these two interleavers are R2 * C2=32 * 30, input bit is divided into the two-way bit sequence, bit u in twos between these two interleavers
P, kAnd u
P, k+1Send to first interleaver, bit u
P, k+2And u
P, k+3Send to second interleaver, the output bit sequence of two interleavers according to the order combination in twos that distributes, is specially bit v again
P, kAnd v
P, k+1From the output of first interleaver, and bit v
P, k+2And v
P, k+3From second interleaver output, k mod4=1 herein, later bit sequence is by that analogy.
In embodiment one, for these two interleavers dispose the different patterns that interweaves respectively, wherein, the pattern that respectively interweaves is an example only the initial position of input bit sequence is defined into the target location by row, in specific implementation, interleaver adopts, and the pattern that interweaves can be defined into the initial position of input bit sequence the target location or by cell the initial position of input bit sequence is defined into the target location by row by row, and in embodiment one, the pattern that interweaves of first interleaver is as shown in table 1:
Table 1
| Columns C2 | Pattern＜the P2 (0) that interweaves between row, P2 (1) ..., P2 (C2-1) 〉 |
| 30 | <0，20，10，5，15，25，3，13，23，8，18，28，1，11，21， 6，16，26，4，14，24，19，9，29，12，2，7，22，27，17> |
If the list entries u of first interleaver
P, 1, u
P, 2, u
P, 3..., u
P, UAfter the exchange, the filtering filling bit is from the first interleaver output sequence v between being listed as in first interleaver
P, 1, v
P, 2..., v
P, UThe interleaving process that carries out in first interleaver may further comprise the steps as shown in Figure 1:
Step S101 is with input bit sequence u
P, 1, u
P, 2, u
P, 3..., u
P, UY from the 0th row, the 0th row
P, 1Beginning writes matrix R2 * C2 line by line;
This matrix column from left to right be numbered 0,1,2 ..., C2-1; The row of this matrix is numbered 0,1,2 from top to bottom ..., R2-1.Writing the matrix R2 * C2 that finishes is:
Wherein, y
P, k=u
P, k, k=1,2 ..., U; If R2 * C2＞U, then at k=U+1, U+2 ..., during R2 * C2, in this matrix, add filling bit, even y
P, k=0 or make y
P, k=1.After exchanging according to the pattern that interweaves, this filling bit of deletion in the output sequence of matrix.In embodiment one, because in HSDPA (High speed downlink packet access, high speed downlink packet inserts), for 16QAM, for each road interleaver, the length of list entries is 32 * 30, therefore without filling bit.
Step S102 is according to the pattern＜P2 that interweaves (j) shown in the table 1 〉
J ∈ 0,1 ..., C2-1}Row exchange between this matrix is listed as;
Wherein P2 (j) is the initial position of j exchange row.Bit after this row exchange is y '
P, k, and the matrix after this row exchange is:
Step S103 pursues row output to the bit that exchanges the back matrix.
Bit through exchange between R2 * C2 matrix column after, by the row output sequence, the input bit y during promptly corresponding k＞U
P, kBeing output as bit is y '
P, kThe output bit sequence is v
P, 1, v
P, 2..., v
P, U, v wherein
P, 1For the subscript k that exports is minimum bit y '
P, k, v
P, 2For the subscript k that exports is time little bit y '
P, k, and the like.
The interleaving process that carries out in the interleaving process that carries out in second interleaver and first interleaver is identical, only be according to the pattern difference that interweaves.Behind second interleaved sequence of first interleaved sequence that obtains first interleaver output and the output of second interleaver, with first interleaved sequence and second interleaved sequence according to the order combination in twos that distributes.
Because in the present embodiment, only require that first interleaver is different with the pattern that interweaves that second interleaver adopts, therefore, in two patterns that interweave, the different part in the target location of the identical data of definition initial position is (for embodiment one, promptly for the different part in target location that exchanges the initial position correspondence of row in two patterns that interweave, identical two bits of input sequence are respectively through after the interweaving of two interleavers, can produce the gain that interweaves), identical two bits of input sequence are respectively through after the interweaving of two interleavers, can produce the gain that interweaves, promptly variation has taken place in the distance of these two bits.For example, in the pattern that interweaves that first interleaver adopts, initial position is that the target location of 0 row still is 0, and in the pattern that interweaves that second interleaver adopts, initial position is that the target location of 0 row is 30, as seen, the bit with the bit of first interleaver output and the output of second interleaver carry out in conjunction with the time, the initial position of two interleavers output be 0 be listed in interweave after, variation has taken place in distance, has produced the gain that interweaves.
In the present embodiment, the pattern that interweaves that two interleavers are adopted does not need concrete qualification, but, in order all to have the gain that interweaves between the bit that makes two interleaver outputs, in these two the different patterns that interweave, should guarantee the row that each initial position is identical, its target location is all inequality as far as possible.
And because the pattern that interweaves that two interleavers are adopted does not have concrete the qualification, therefore, the storage overhead that brings in order to reduce storage to interweave pattern, in the present embodiment, can only preserve the pattern that interweaves that an interleaver adopts, and be used as the pattern that interweaves that another interleaver adopts with the distortion of this pattern that interweaves.In embodiment one, the pattern that interweaves that first interleaver adopts is the pattern that interweaves shown in the table 1, and the pattern that interweaves that second interleaver adopts can obtain according to the distortion of the pattern that interweaves shown in the table 1, the mode of carrying out this distortion has a lot, for example adopts the pattern that interweaves shown in following several mode his-and-hers watches 1 to be out of shape:
Mode one
The pattern that interweaves of second interleaver is the backward of the pattern that interweaves of first interleaver, and then the pattern that interweaves shown in the table 1 being carried out corresponding deformation, to obtain the pattern that interweaves of second interleaver as shown in table 2:
Table 2
| Columns C2 | Pattern＜the P2 (0) that interweaves between row, P2 (1) ..., P2 (C2-1) 〉 |
| 30 | <17，27，22，7，2，12，29，9，19，24，14，4，26，16，6 21，11，1，28，18，8，23，13，3，25，15，5，10，20，0> |
Mode two
Generating the interweaving during pattern of second interleaver, earlier the pattern that interweaves of first interleaver is being carried out backward and arrange, the first half and latter half exchange of the pattern that interweaves after again backward being arranged, the pattern that interweaves of second interleaver that then obtains is as shown in table 3:
Table 3
| Columns C2 | Pattern＜the P2 (0) that interweaves between row, P2 (1) ..., P2 (C2-1) 〉 |
| 30 | <21，11，1，28，18，8，23，13，3，25，15，5，10，20，0 17，27，22，7，2，12，29，9，19，24，14，4，26，16，6> |
Mode three
The pattern that interweaves of second interleaver is that the first half of the pattern that interweaves and the latter half of first interleaver exchanges, and then the pattern that interweaves shown in the table 1 being carried out corresponding deformation, to obtain the pattern that interweaves of second interleaver as shown in table 4:
Table 4
| Columns C2 | Pattern＜the P2 (0) that interweaves between row, P2 (1) ..., P2 (C2-1) 〉 |
| 30 | <6，16，26，4，14，24，19，9，29，12，2，7，22，27，17 0，20，10，5，15，25，3，13，23，8，18，28，1，11，21> |
As seen, because the pattern that interweaves that obtains according to above-mentioned variety of way is to obtain through simply handling to be out of shape on the basis of the pattern that interweaves shown in the table 1, do not need other buffer memory to store this pattern that interweaves, saved storage overhead, and, because this deformation process is very simple, can't increase the complexity of interleaving treatment because of this deformation process.
When specific implementation, can not be out of shape another pattern that interweaves of generation yet, but directly preserve two patterns that interweave according to the pattern of storing that interweaves, these two patterns that interweave can dispose as required, as long as guarantee that two patterns that interweave are different.For example, the pattern that interweaves that makes second interleaver is a random alignment of the pattern that interweaves of first interleaver, i.e. 1～30 random alignment, but should guarantee that two patterns that interweave are inequality.Under the situation of two patterns that interweave of direct preservation, need to increase certain storage overhead, but owing to the required memory space of intersection chart sample body is little, therefore, the storage overhead of its increase can not cause the bigger burden of system yet.
Embodiment two
In embodiment two, code multiplexing process with the HS-DSCH that adopts the 64QAM modulation is an example, in this process, adopt the interleaver of three same sizes that input bit is interweaved, these three interleavers are R2 * C2=32 * 30, input bit is divided into three tunnel sequences, bit u between these three interleavers
P, kAnd u
P, k+1Send to first interleaver, bit u
P, k+2And u
P, k+3Send to second interleaver, bit u
P, k+4And u
P, k+5Send to the 3rd interleaver, each road sequence interweaves respectively, and the output bit sequence of three interleavers carries out combination according to the order of distributing again, is specially bit v
P, kAnd v
P, k+1From the output of first interleaver, bit v
P, k+2And v
P, k+3From the output of second interleaver, bit v
P, k+4And v
P, k+5From the output of first interleaver, later bit sequence by that analogy.
In embodiment two, equally, as long as guarantee that the pattern that interweaves of each interleaver employing is inequality, so, for the different part in target location of the initial position correspondence of exchange row in any two patterns that interweave in three patterns that interweave, identical two bits of input sequence through after the interweaving of two interleavers, can produce the gain that interweaves respectively, situation compared with each interleaver employing same interlace pattern can obtain the effect that better interweaves.
As seen, when adopting two or more interleavers to interweave,, just can obtain the effect that better interweaves as long as adopt the mutually different pattern that interweaves.In addition, if guarantee all to have the gain that interweaves between each bit, need then to guarantee that data definition that should be as far as possible that initial position is identical is to different target locations in this two or more different pattern that interweaves.
Embodiment three
In embodiment three, be example with the E-DCH that adopts the 4PAM modulation, in this process, adopting the identical size of two-way is the interleaver of R2 * 30, wherein R2 is for satisfying
Smallest positive integral.Input bit enters the two-way interleaver successively.u
P, kEnter first via interleaver, u
P, k+1Enter the second road interleaver.Through after the interweaving of two-way interleaver, read bit from two interleavers successively and export, be i.e. v
P, kFrom first interleaver, v
P, k+1From second interleaver, wherein k mod 2=1.Such as a length is 60 bit sequence, and its index is followed successively by: 1,2 ..., 60, then wherein index is { 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47,49,51,53,55,57, the sequence of 59} enters first interleaver, and index is { 2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58, the bit of 60} enters the second road interleaver.
If two interleavers adopt same interlace patterns as shown in table 1, then through after the interweaving of first via interleaver, the corresponding index of output bit is: { 1,41,21,11,31,51,7,27,47,17,37,57,3,23,43,13,33,53,9,29,49,39,19,59,25,5,15,45,55,35}, through after the interweaving of the second road interleaver, the corresponding index of output bit is: { 2,42,22,12,32,52,8,28,48,18,38,58,4,24,44,14,34,54,10,30,50,40,20,60,26,6,16,46,56,36}, then, the output bit of two interleavers is carried out in conjunction with after the index of the bit sequence that obtains be: { 1,2,41,42,21,22,11,12,31,32,51,52,7,8,27,28,47,48,17,18,37,38,57,58,3,4,23,24,43,44,13,14,33,34,53,54,9,10,29,30,49,50,39,40,19,20,59,60,25,26,5,6,15,16,45,46,55,56,35,36}.
As seen, through after the interweaving of two interleavers, the list entries index is the gain that do not interweave between the input bit of k and k+1, that is, the list entries index is that 1,2 bit, list entries index are the gain that all do not interweave of 41,42 ratio top grade.
And if make first interleaver adopt the pattern that interweaves as shown in table 1, and second interleaver adopts the pattern that interweaves as shown in table 2, and makes that aforesaid length is that the index of 60 bit sequence is that the bit of odd number is imported first interleaver, then the index of the output bit sequence of first interleaver is { 1,41,21,11,31,51,7,27,47,17,37,57,3,23,43,13,33,53,9,29,49,39,19,59,25,5,15,45,55,35} is that the bit of even number is imported second interleaver and this length is the index of 60 bit sequence, then the index of the output bit sequence of second interleaver is { 36,56,46,16,6,26,60,20,40,50,30,10,54,34,14,44,24,4,58,38,18,48,28,8,52,32,12,22,42,2}.Then, the output bit of two interleavers is carried out in conjunction with after the index of the bit sequence that obtains be: { 1,36,41,56,21,46,11,16,31,6,51,26,7,60,27,20,47,40,17,50,37,30,57,10,3,54,23,34,43,14,13,44,33,24,53,4,9,58,29,38,49,18,39,48,19,28,59,8,25,52,5,32,15,12,45,22,55,42,35,2}.
As seen, two interleavers are interweaving during pattern shown in employing table 1 and the table 2 respectively, and the bit that index was adjacent when each was imported has all interweaved out, can obtain bigger the interweave gain and the effect that better interweaves.When specific implementation, as long as make two interleavers adopt the different patterns that interweaves respectively.
Interlaced device in the embodiment of the invention comprises two or more interleavers and configuration module as shown in Figure 2, wherein:
These two or more interleavers are used for according to the pattern that interweaves of configuration the input data being carried out interlace operation;
Configuration module is used to these two or more interleavers to dispose the different patterns that interweaves respectively.
In this configuration module, can comprise second memory cell, be used for saving as simultaneously the different pattern that interweaves that these two or more interleavers dispose respectively.
But the storage overhead that brings in order to reduce storage to interweave pattern, in this interlaced device, can not save as the different pattern that interweaves that these two or more interleavers dispose respectively simultaneously, but only save as the pattern that interweaves that one of them interleaver disposes, therefore, this configuration module can comprise first memory cell and dispensing unit, wherein:
First memory cell is used to save as first of one of them interleaver configuration pattern that interweaves;
Dispensing unit is used for generating the different with it patterns that interweaves and disposing to other interleavers according to first pattern that interweaves that first memory cell is preserved.
In sum, the technical scheme that adopts the embodiment of the invention to provide, in two or more patterns that interweave, the different part in target location of the data that the definition initial position is identical, identical two bits of input sequence are respectively through after the interweaving of two or more interleavers, can produce the gain that interweaves, promptly variation has taken place in the distance of these two bits, thereby can improve the felt properties of interleaving process.And this scheme realizes simple, can increase storage overhead simultaneously.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the deinterleaving method of data is characterized in that, may further comprise the steps:
For two or more interleavers dispose the different patterns that interweaves respectively; And
When interweaving, described two or more interleavers carry out interlace operation according to the pattern that interweaves for its configuration to the input data respectively.
2. the method for claim 1, it is characterized in that, describedly dispose the different patterns that interweaves respectively and specifically comprise for two or more interleavers: be one of them interleaver configuration first pattern that interweaves earlier, and dispose to other interleavers according to this first different with it pattern that interweaves of pattern generation that interweaves.
3. method as claimed in claim 2 is characterized in that, the pattern that interweaves of described generation comprises: this first pattern that interweaves is carried out backward and arranges the pattern that interweaves obtain.
4. method as claimed in claim 2 is characterized in that, the pattern that interweaves of described generation comprises: earlier this first pattern that interweaves is carried out backward and arranges, the pattern that interweaves that the first half of the pattern that interweaves after again backward being arranged and latter half exchange obtain.
5. method as claimed in claim 2 is characterized in that, the pattern that interweaves of described generation comprises: this first first half and latter half that interweaves pattern is exchanged the pattern that interweaves that obtains.
6. as the described method of arbitrary claim in the claim 1 to 5, it is characterized in that in the pattern that respectively interweaves, the data definition that initial position is identical is to different target locations.
7. as the described method of arbitrary claim in the claim 1 to 5, it is characterized in that described interlace operation carries out in the code multiplexing process of high speed descending sharing channel or enhancing special uplink channel.
8. an interlaced device is characterized in that, described interlaced device comprises two or more interleavers and configuration module, wherein:
Described interleaver is used for according to the pattern that interweaves of configuration the input data being carried out interlace operation;
Described configuration module is used to described two or more interleavers to dispose the different patterns that interweaves respectively.
9. device as claimed in claim 8 is characterized in that described configuration module also comprises first memory cell and dispensing unit, wherein:
Described first memory cell is used to save as first of one of them interleaver configuration pattern that interweaves;
Described dispensing unit is used for generating the different with it patterns that interweaves and disposing to other interleavers according to first pattern that interweaves that described first memory cell is preserved.
10. device as claimed in claim 8 is characterized in that described configuration module also comprises second memory cell, is used for saving as simultaneously the different pattern that interweaves that described two or more interleavers dispose respectively.
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| CN101984567A (en) * | 2010-10-27 | 2011-03-09 | 京信通信***（中国）有限公司 | HS-DSCH interleaving method and device for high-order modulation |
| WO2012109851A1 (en) * | 2011-07-29 | 2012-08-23 | 华为技术有限公司 | Interleaving and de-interleaving method, interleaver and de-interleaver |
| CN109150200A (en) * | 2017-06-27 | 2019-01-04 | 华为技术有限公司 | A kind of method and apparatus of channel interleaving |
| CN109995434A (en) * | 2017-12-29 | 2019-07-09 | 华为技术有限公司 | A kind of data transmission method, communication equipment and storage medium |
| CN111786682A (en) * | 2015-03-02 | 2020-10-16 | 三星电子株式会社 | Transmitter and division method thereof |
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| GB2387515A (en) * | 2002-04-08 | 2003-10-15 | Ipwireless Inc | Mapping bits to at least two channels using two interleavers, one for systematic bits, and the other for parity bits |
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| AU2005262361B2 (en) * | 2004-07-01 | 2010-05-20 | Qualcomm Incorporated | Advanced MIMO interleaving |
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| CN101984567A (en) * | 2010-10-27 | 2011-03-09 | 京信通信***（中国）有限公司 | HS-DSCH interleaving method and device for high-order modulation |
| CN101984567B (en) * | 2010-10-27 | 2013-05-01 | 京信通信***（中国）有限公司 | HS-DSCH interleaving method and device for high-order modulation |
| WO2012109851A1 (en) * | 2011-07-29 | 2012-08-23 | 华为技术有限公司 | Interleaving and de-interleaving method, interleaver and de-interleaver |
| US9916240B2 (en) | 2011-07-29 | 2018-03-13 | Huawei Technologies Co., Ltd. | Interleaver and de-interleaver for correcting a burst bit error |
| CN111786682A (en) * | 2015-03-02 | 2020-10-16 | 三星电子株式会社 | Transmitter and division method thereof |
| CN111786682B (en) * | 2015-03-02 | 2023-09-01 | 三星电子株式会社 | Transmitter and dividing method thereof |
| US11831331B2 (en) | 2015-03-02 | 2023-11-28 | Samsung Electronics Co., Ltd. | Transmitter and segmentation method thereof |
| CN109150200A (en) * | 2017-06-27 | 2019-01-04 | 华为技术有限公司 | A kind of method and apparatus of channel interleaving |
| US11082070B2 (en) | 2017-06-27 | 2021-08-03 | Huawei Technologies Co., Ltd. | Channel interleaving method and apparatus |
| CN109995434A (en) * | 2017-12-29 | 2019-07-09 | 华为技术有限公司 | A kind of data transmission method, communication equipment and storage medium |
| CN109995434B (en) * | 2017-12-29 | 2020-09-08 | 华为技术有限公司 | Data transmission method, communication equipment and storage medium |
| US11381338B2 (en) | 2017-12-29 | 2022-07-05 | Huawei Technologies Co., Ltd. | Data transmission method, communications device, and storage medium |
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| CN101237440B (en) | 2012-01-25 |
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