CN101227298B - Router power consumption determination method based on network on chip - Google Patents

Abstract

The invention discloses a router power model on the basis of a network-on-chip, which simplifies router operations into four power dissipation links namely write-cache, read-cache, a bestride switch and a bestride link according to the power dissipation specific weight and attributes dynamic power dissipation to bit flipping activities which are triggered when a present data film arrives, and numbers the power dissipation by the bit flipping activities to obtain the router power model. Considering that the implementation complexity which is required by the network-on-chip requirements to the power model is as low as possible, the invention can adopt the statistical average in stead of the instantaneous sampled value to obtain a power dissipation simplified model. Hardware implementation methods of two power dissipation models are given out aiming at a five-channel rooter structure, the simplified model is introduced to a self-adaptive routing algorithm, which realizes the power dissipation distribution optimization of the network-on-chip. The router power model which is proposed by the invention has low algorithm complexity and simple realization, is suitable for network-on-chip, and can be used in research and application in the aspects of power dissipation performance statistics, the power dissipation distribution optimization, thermal protection and the like.

Description

Router power consumption based on network-on-chip is determined method

Technical field

The present invention relates to a kind of router power consumption model that is applied to network-on-chip, specifically a kind of router power consumption model of low complex degree based on network-on-chip.

Background technology

Network-on-chip (NoC) is that (System on a chip SoC) provides a new example to following complication system chip, receives increasing concern recently.When integrated scale was more and more big on the sheet of NoC, the power consumption of network just became one of design key problem, for example power consumption profile optimization and heat protection.

Main task based on the router power consumption model power consumption model of network-on-chip is exactly the power consumption state of real-time statistics router, with power managed functions such as the power consumption performance statistics of supporting network-on-chip, power consumption profile optimization, heat protections.The trade-off factor of power consumption model mainly is presented as precision and implementation complexity, and network-on-chip has proposed special requirement to the complexity of power consumption model.

Typical network-on-chip structure has multiple structures such as two-dimensional grid, annular grid, star, fat tree, it is characterized in that integrated a large amount of, standardized communication device, treatment element and memory element on chip, and is huge.When the communication flows distribution undue concentration of network-on-chip, can cause the chip local overheating, influence the reliability of system, even defective chip, cause heavy losses.Therefore, power consumption statistics and power managed function have become a kind of urgent requirement for NoC.

Two-dimensional grid (4 * 4) NoC system model as shown in Figure 1.NoC is made up of router (R), link and local subsystem (LS).Router is the server parts; Local subsystem comprises a network interface (NI), can have processing unit (PE) or memory cell (Mem) or the combination of the two.

The NoC power managed be characterized as distributed management, finish by each router, its key is the router power consumption modeling.Because router is present among the NoC in large quantities, make that the introducing of power managed mechanism increases the NoC cost not obviously, reduce network performance, router power consumption model must have less computation complexity and realize cost.

Summary of the invention

In order to satisfy the requirement of NoC system power dissipation management function, the purpose of this invention is to provide a kind of router power consumption model of low complex degree based on network-on-chip.This router power consumption model is simplified router operation according to power consumption proportion be four main power consumption links: write buffer memory, read buffer memory, across switch with across link, and the bit reversal activity that triggers when dynamic power consumption is arrived owing to the current data sheet is added up power consumption by the bit reversal activity.

The objective of the invention is to be achieved through the following technical solutions:

A kind of router power consumption model based on network-on-chip, it is characterized in that: it is reduced to router operation and writes buffer memory, reads buffer memory according to power consumption proportion, across switch with across four power consumption links of link, and the bit reversal activity that triggers when dynamic power consumption is arrived owing to the current data sheet, add up power consumption by the bit reversal activity, the router power consumption model that obtains is as follows:

$P_{\mathrm{total}}=(C_{\mathrm{wr}-\mathrm{bit}}\×\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{wr}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{wr}}+C_{\mathrm{rd}-\mathrm{bit}}\×\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{rd}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{rd}})/T$

In the formula, P _TotalBe router power consumption, N _{Flit_wr}Be data slice number, the N that enters router at T in the time period _{Flit_rd}Be data slice number, the C that leaves router at T in the time period _{Rd_bit}The power consumption factor of the single bit reversal of expression read operation, power consumption factor, the S (i) that Cwr-bit represents the single bit reversal of write operation respectively _{Buff_rd}Bit reversal number, S (i) that the expression read operation causes _{Buff_wr}The bit reversal number that the expression write operation causes.

Still have higher computation complexity but accurately add up the bit reversal number, can not finely satisfy the requirement that realizes on the sheet.Can further adopt the assembly average of bit reversal number to replace instantaneous sampling value among the present invention, thereby simplify calculating greatly, it is suitable that this approximation method is used great majority.Adopt the assembly average of bit reversal number to replace instantaneous sampling value, it is as follows to obtain the router power consumption model simplified style:

P _total＝(C _wr-flit×N _{flit_wr}+C _rd-flit×N _{flit_rd})/T

In the formula, C _Rd-flitBe the average power consumption coefficient that router is read the operation of individual data sheet, C _Wr-flitIt is the average power consumption coefficient that router is write the operation of individual data sheet.

The present invention is applicable in the five-way road structure router.This model also can be supported the research and the application of aspect such as power consumption performance statistics, power consumption profile optimization, the heat protection of network-on-chip.

Foundation is during based on the router power consumption model of network-on-chip, and at first, how dynamic power consumption produces when needing clear and definite NoC system transmissions data.Shown in Fig. 2 (a), data will evoke sequence of operations (typical case is not with the router of tunnel) across router and link: write buffer memory 1, route 2, switch arbitration 3, read buffer memory 4, across switch 5 with across link 6, finally arrive downstream router.Each operation all can produce dynamic power consumption.Result of study shows, compares with other several operations, and the power consumption that arbitration and logical routing cause is negligible.Therefore, the power consumption link of router can be simplified to for four steps, see Fig. 2 (b): write buffer memory 1, read buffer memory 2, across switch 3 with across link 4.

In the router, dynamic power consumption and current data sheet cause the bit reversal activity of each link closely related when arriving, and do not have the bit reversal activity just not have dynamic power consumption.Therefore, can carry out online power consumption in each link edge total bit reversal activity of statistics estimates.Below will adopt based on the method for bit reversal activity the average power consumption of operating shown in Fig. 2 (b) will be carried out modeling.

The reading and writing buffer memory: in router, reading and writing buffer memory is two main operations that trigger the buffer memory dynamic power consumption.T reads the average power consumption P of (writing) buffer memory in the time period _{Buff_rd}(P _{Buff_wr}) can be by following four parameter approximate evaluations: read (writing) buffer memory times N _{Buff_rd}(N _{Buff_wr}) and read the bit reversal that causes of (writing) operation and count S (i) _{Buff_rd}(S (i) _{Buff_wr}).Expression formula is suc as formula shown in (1), (2).Wherein, C _{Buff_rd}(C _{Buff_wr}) be the power consumption factor of reading (writing) buffer memory.

$P_{\mathrm{buff}\_\mathrm{rd}}=(C_{\mathrm{buff}\_\mathrm{rd}}\×\underset{i=1}{\overset{N_{\mathrm{buff}\_\mathrm{rd}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{rd}})/T---\left(1\right)$

$P_{\mathrm{buff}\_\mathrm{wr}}=(C_{\mathrm{buff}\_\mathrm{wr}}\×\underset{i=1}{\overset{N_{\mathrm{buff}\_\mathrm{wr}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{wr}})/T---\left(2\right)$

Across switch: switch is transferred to output with data slice from buffer memory.The bit reversal at switch edge is counted S (i) _CrossbarWith across the switch times N _CrossbarDetermined the power consumption of switch, expression formula as the formula (3).Wherein, C _CrossbarIt is the power consumption factor of switching manipulation.

$P_{\mathrm{crossbar}}=(C_{\mathrm{crossbar}}\×\underset{i=1}{\overset{N_{\mathrm{crossbar}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{crossbar}})/T---\left(3\right)$

Across link: the power consumption of link adopts the edge bit reversal to count S (i) too _LinkWith link across times N _CrossbarCome modeling, as the formula (4).Wherein, C _LinkIt is the power consumption factor of link operation.

$P_{\mathrm{link}}=(C_{\mathrm{link}}\×\underset{i=1}{\overset{N_{\mathrm{link}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{link}})/T---\left(4\right)$

Router total power consumption shown in Fig. 2 (b) as the formula (5).

P _total＝P _{buff_wr}+P _{buff_rd}+P _crossbar+P _link (5)

The bit reversal number is the Hamming distance (Hamming distance) of adjacent two data sheet, has only when data content to change or data slice occurs in sequence when changing and just can change.Shown in Fig. 2 (b), operating continuity has guaranteed S (i) _{Buff_rd}≡ S (i) _Crossbar≡ S (i) _LinkRouter power consumption model can be reduced to formula (6) thus.

$P_{\mathrm{total}}=(C_{\mathrm{wr}-\mathrm{bit}}\×\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{wr}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{wr}}+C_{\mathrm{rd}-\mathrm{bit}}\×\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{rd}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{rd}})/T---\left(6\right)$

In the formula, N _{Flit_wr}(N _{Flit_rd}) be the data slice number that enters (leaving) router at T in the time period, C _Rd-bit, C _Wr-bitRepresent that respectively reading and writing operate the power consumption factor of single bit reversal, as the formula (7).

$\left\{\begin{array}{c}{C}_{\mathrm{wr}-\mathrm{bit}}=C_{\mathrm{buff}\_\mathrm{wr}}\\ C_{\mathrm{rd}-\mathrm{bit}}=C_{\mathrm{buff}\_\mathrm{rd}}+C_{\mathrm{crossbar}}+C_{\mathrm{link}}\end{array}\right.---\left(7\right)$

Formula (6) is complete router power consumption model, and promptly the router power consumption model complete model only has parameter S (i) _{Buff_rd}And S (i) _{Buff_wr}Need online statistics.Still have higher computation complexity but accurately add up the bit reversal number, can not finely satisfy the requirement that realizes on the sheet.The present invention further adopts the assembly average of bit reversal number to replace instantaneous sampling value, thereby has simplified calculating greatly, and it is suitable that this approximation method is used great majority.So router power consumption model is further simplified an accepted way of doing sth (8).

P _total＝(C _wr-bit×S _{buff_wr}×N _{flit_wr}+C _rd-bit×S _{buff_rd}×N _{flit_rd})/T(8)

So far, the router power consumption model that obtains simplifying, i.e. router power consumption model simplified style, as the formula (9).

P _total＝(C _wr-flit×N _{flit_wr}+C _rd-flit×N _{flit_rd})/T (9)

Wherein, C _Rd-flit(C _Wr-flit) be the average power consumption coefficient that router is read (writing) individual data sheet (flit) operation, depend primarily on technology and design itself that design is adopted, and be subjected to the influence of application characteristic to a certain extent.Can adjust weight parameter as the case may be.

Power consumption model for specific implementation the present invention proposes is applied to this model in the router of five-port structure.Router has five bidirectional ports: north (North), east (East), south (South), west (West) and this locality (Local).Each port has the input and output passage.Input channel comprises buffer memory and logical routing, and output channel comprises arbitrated logic.Local port is responsible for communicating by letter of router and local subsystem, and other port is responsible for communicating by letter of router and neighbour's router, as shown in Figure 1.For the route of seating surface to power consumption, router also comprises a power consumption estimation module (power consumption calculation) and a power consumption table register (depositing the neighboring router power consumption state).Router topology as shown in Figure 3.

Concrete structure in conjunction with router comes timing with clock, and then the complete model of router power consumption and simplified model change an accepted way of doing sth (10) and formula (11) respectively.

$P_{\mathrm{full}}=\underset{t=t-m+1}{\overset{t}{\mathrm{\Σ}}}(C_{\mathrm{wr}-\mathrm{bit}}\×\underset{i=1}{\overset{5}{\mathrm{\Σ}}}n{(i,t)}_{\mathrm{flit}\_\mathrm{wr}}S{(i,t)}_{\mathrm{buff}\_\mathrm{wr}}+C_{\mathrm{rd}-\mathrm{bit}}\×\underset{i=1}{\overset{5}{\mathrm{\Σ}}}n{(i,t)}_{\mathrm{flit}\_\mathrm{rd}}S{(i,t)}_{\mathrm{buff}\_\mathrm{rd}})/m---\left(10\right)$

$P_{\mathrm{simple}}=\underset{t=t-m+1}{\overset{t}{\mathrm{\Σ}}}(C_{\mathrm{wr}-\mathrm{flit}}\×\underset{i=1}{\overset{5}{\mathrm{\Σ}}}n{(i,t)}_{\mathrm{flit}\_\mathrm{wr}}+C_{\mathrm{rd}-\mathrm{flit}}\×\underset{i=1}{\overset{5}{\mathrm{\Σ}}}n{(i,t)}_{\mathrm{flit}\_\mathrm{rd}})/m---\left(11\right)$

In the formula, and n (i, t) _{Flit_rd}(n (i, t) _{Fliit_wr}Be the number of times that t clock cycle i input channel read (writing) operation, its value is 0 or 1; S (i, t) _{Flit_rd}(S (i, t) _{Flit_wr}) be that t clock cycle i input channel read the bit reversal number that (writing) operation causes; M is the sampling time window, and for to the heat accumulation of network and the consideration of heat dissipation effect, the big more illustrative system heat dissipation ability of m value is poor more, and m gets 1, just is equivalent to t transient power consumption constantly.

The router power consumption complete model is comparatively complicated, but precision is higher, can be with cache read (writing) number of operations, read and write bit reversal number and three the parameter (C that cause at every turn _Rd-bit, C _Wr-bitAnd m) approximate representation.And simplified model can be with cache read (writing) number of operations and three parameter (C _Rd-bit, C _Wr-bitAnd m) approximate representation, complexity is low, is suitable for realizing on the sheet.

Router power consumption is represented that by each link power consumption sum each link power consumption is then by the product representation of each link power consumption factor with the movable number of its bit reversal.

The movable number of bit reversal calculates by the current data sheet with by the Hamming distance of rewrite data sheet (Hammingdistance), has only when data content to change or data slice just can cause the bit reversal activity when occurring in sequence change.

Among the present invention, each link power consumption factor can be taken from the parameter of special process, is intended for practical application; Only need compare in the research topic of power consumption relative size at some, the power consumption factor integer can be calculated to simplify.

The router power consumption model that the present invention proposes, algorithm complex is low, realizes simply, is suitable for network-on-chip, can be used for the research and the application of the aspects such as power consumption performance statistics, power consumption profile optimization, heat protection of network-on-chip.

Description of drawings

Fig. 1 is the structural representation of two-dimensional grid NoC system model (4 * 4);

Fig. 2 (a) is a router power consumption link schematic diagram;

Fig. 2 (b) is the router power consumption link schematic diagram of simplifying;

Fig. 3 is the router topology schematic diagram;

Fig. 4 is a router power consumption model complete model hardware configuration schematic diagram;

Fig. 5 is a S counter hardware configuration schematic diagram;

Fig. 6 is that router power consumption model is simplified power consumption model hardware configuration schematic diagram;

Fig. 7 is a throughput graph;

Fig. 8 is the mean packet delay curve chart;

Fig. 9 is average (AVG-P)/maximum (MAX-P) power consumption curve chart;

Figure 10 is power consumption variance curve figure.

Embodiment

Embodiment 1

A kind of router power consumption model based on network-on-chip, it is reduced to router operation and writes buffer memory according to power consumption proportion, read buffer memory, across switch with across four power consumption links of link, and the bit reversal activity that triggers when dynamic power consumption is arrived owing to the current data sheet, add up power consumption by the bit reversal activity, the router that obtains

Power consumption model is as follows:

$P_{\mathrm{total}}=(C_{\mathrm{wr}-\mathrm{bit}}\×\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{wr}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{wr}}+C_{\mathrm{rd}-\mathrm{bit}}\×\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{rd}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{rd}})/T.$

In the formula, P _TotalBe router power consumption, N _{Flit_wr}Be data slice number, the N that enters router at T in the time period _{Flit_rd}Be data slice number, the C that leaves router at T in the time period _Rd-bitThe power consumption factor of the single bit reversal of expression read operation, power consumption factor, the S (i) that Cwr-bit represents the single bit reversal of write operation respectively _{Buff_rd}Bit reversal number, S (i) that the expression read operation causes _{Buff_wr}The bit reversal number that the expression write operation causes.

The hardware of power consumption model is realized by shown in Figure 4 fully.Mainly by 10 S counters, 10 and door, 4 adders, 2 multipliers, 1 divider, and 1 m rank shift register formation.The S counter is used to add up the bit reversal number, and its structure adopts the individual XOR gate of N (being the data slice width, is 35 in the design), 1 adder and 1 alternative MUX to calculate two Hamming distances between the data slice as shown in Figure 5.D1 is the current data sheet, and d2 is by the rewrite data sheet, and both corresponding position XOR summations can be obtained the bit reversal number that this operation causes.Be mainly used in the effective reading and writing operation of generation enable signal with door, have only effectively (rd[i] ﹠amp of read operation; Ept[i]) or effective (the wr[i] ﹠amp of write operation; Full[i]) just need calculate the bit reversal number.Adder is mainly used in sum operation.Multiplier is used for the introducing of power consumption weight.Divider is used to ask average power consumption.M rank shift register is realized the preservation of continuous m cycle power consumption state, the casting out of the introducing of current state and expired state.

Embodiment 2

Adopt the assembly average of bit reversal number to replace instantaneous sampling value, it is as follows to obtain the router power consumption model simplified style:

P _total＝(C _wr-flit×N _{flit_wr}+C _rd-flit×N _{flit_rd})/T

In the formula, C _Rd-flitBe the average power consumption coefficient that router is read the operation of individual data sheet, C _Wr-flitIt is the average power consumption coefficient that router is write the operation of individual data sheet.

Simplifying the hardware of power consumption model realizes as shown in Figure 6.Mainly constitute with door, 4 adders, 1 divider and 1 m rank shift register by 10 alternative MUX, 10.Be that with the difference of the maximum of complete model simplified model has been removed S counter and the such complex unit of multiplier from only with alternative MUX, just realized that with door and adder reading and writing operate the statistics of power consumption, has reduced implementation complexity greatly.The purposes of other unit is with the explanation unanimity in the complete model.

For the effect of exemplary power consumption model in the NoC power managed, we will simplify power consumption model and introduce in the adaptive routing algorithm (strange-the even model that turns round) that avoids deadlock, for NoC provides adaptive routing protocol towards power consumption, make the NoC power consumption profile trend towards balance, avoid the appearance of hot localised points.

Towards the Routing Protocol (TURN-P) of power consumption based on very-the idol model that turns round, its allows packet to transmit along the minimal path between the source and destination.Turn round and be restricted to: odd column restriction north-Xi turns round (NW) and Nan-Xi turns round (SW); Turn round (EN) in even column restriction east-north and Dong-Nan turns round (ES); Restriction 180 degree turn round.Satisfying under the situation of above-mentioned restriction rule, if exist many feasible paths, router can select the lower path of power consumption index to transmit.

In order to investigate the performance of New Deal, will be in the experiment based on congested Routing Protocol (TURN-C) reference as a comparison, both throughputs (Throughput), mean packet delay (Latency), power consumption curve such as Fig. 7-shown in Figure 10.In the experiment, emulation platform is 4 * 4 network NoC simulators, power consumption model parameter value: C _Wr-flit=1, C _Rd-flit=1 and m=1.Experimental result shows: the overall performance of TURN_P is not near TURN_C (throughput almost descends, and the mean packet delay is omited height a bit).But the power consumption profile of TURN_P is obviously more optimized (maximum power dissipation and power consumption variance descend respectively (0.5-4%) and (1-10%)) than TURN_C.If this power consumption model can be obtained better effect in conjunction with complete self adaptive routing algorithm and deadlock recovery strategy.

Power consumption model of the present invention is except combining with adaptive routing algorithm; realization is beyond the routing mechanism of power consumption; the heat that can also be used to NoC is protected aspects such as (set the power consumption threshold value, forbid focus communication), power consumption statistics, power consumption performance evaluation.

Claims (3)

1. the router power consumption based on network-on-chip is determined method, it is characterized in that: it is reduced to router operation and writes buffer memory, reads buffer memory according to power consumption proportion, across switch with across four power consumption links of link, and the bit reversal activity that triggers when dynamic power consumption is arrived owing to the current data sheet, add up power consumption by the bit reversal activity, the router power consumption model that obtains is as follows:

$P_{\mathrm{total}}=(C_{\mathrm{wr}-\mathrm{bit}}\×\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{wr}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{wr}}+C_{\mathrm{rd}-\mathrm{bit}}\underset{i=1}{\overset{N_{\mathrm{flit}\_\mathrm{rd}}}{\mathrm{\Σ}}}S{\left(i\right)}_{\mathrm{buff}\_\mathrm{rd}})/T$

In the formula, P _TotalBe router power consumption, N _{Flit_wr}Be data slice number, the N that enters router at T in the time period _{Flit_rd}Be data slice number, the C that leaves router at T in the time period _Rd-bitThe power consumption factor of the single bit reversal of expression read operation, power consumption factor, the S (i) that Cwr-bit represents the single bit reversal of write operation respectively _{Buff_rd}Bit reversal number, S (i) that the expression read operation causes _{Buff_wr}The bit reversal number that the expression write operation causes.

2. the router power consumption based on network-on-chip according to claim 1 is determined method, it is characterized in that: adopt the assembly average of bit reversal number to replace instantaneous sampling value, it is as follows to obtain the router power consumption model simplified style:

P _total＝(C _wr-flit×N _{flit_wr}+C _rd-flit×N _{flit_rd})/T

In the formula, C _Rd-flitBe the average power consumption coefficient that router is read the operation of individual data sheet, C _Wr-flitIt is the average power consumption coefficient that router is write the operation of individual data sheet.

3. the router power consumption based on network-on-chip according to claim 1 is determined method, it is characterized in that: this power consumption determines that method is used for five-way road structure router.

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