CN101223605A - Memory control device - Google Patents
Memory control device Download PDFInfo
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- CN101223605A CN101223605A CNA2006800254552A CN200680025455A CN101223605A CN 101223605 A CN101223605 A CN 101223605A CN A2006800254552 A CNA2006800254552 A CN A2006800254552A CN 200680025455 A CN200680025455 A CN 200680025455A CN 101223605 A CN101223605 A CN 101223605A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
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Abstract
There is provided a memory control device capable of smoothing memory access peak band width and achieving refresh operation required at a low peak band width by appropriately dividing the band width required for refresh operation. The memory control device operates a regular refresh request circuit normally performing refresh request at a constant ratio in parallel with a first and a second concentrated refresh request circuit corresponding to a first and a second requester and issuing refresh in a concentrated manner while the refresh request issuing condition is satisfied such as the time band when the memory access band width is lowered.
Description
Technical field
The present invention relates to storage control device, particularly the memory access control circuit controlled of the storer that needs are refreshed.
Background technology
In system LSI in recent years, often a plurality of functions are concentrated in 1 chip.At this moment, for the reduction of seeking system cost, low power consumption etc., often adopt the integrated memory architecture that storer intrinsic in each functional module is integrated.
In the integrated memory architecture, need satisfied be in the peak bandwidth of regulation at each peak bandwidth sum this all functions module, that each functional module is required.And, the time described peak bandwidth and big, for corresponding to this, need the operating frequency of increase memory bus width or raising storer etc., cause the problem of the advantage of obliterating the integrated memory architecture, need to take to offset the countermeasure of this problem thus, therefore need reduce this peak bandwidth as far as possible.
On the other hand, integrated memory as such system LSI, use high speed and jumbo SDARM or DDR-SDRAM, but, these nonvolatile memories need refresh activity, therefore and this refresh activity is by competing mutually with common storage access and bandwidth consumed is carried out, and does not influence peak bandwidth ground and carries out this refresh activity and become an important topic (with reference to patent documentation 1).
At present, the method as solving above-mentioned problem mainly adopts 2 kinds of methods.
One of described 2 kinds of methods are, by in official hour, not implementing refreshing of desired times with omitting, certain allocated bandwidth is given the method (hereinafter referred to as often refreshing) that often refreshes, another method is, by concentrated the refreshing of time band that descends in common storage access frequency, thereby finish required refreshing in the stipulated time (refreshing) at short notice hereinafter referred to as concentrating.
As concentrating the method that refreshes, for example in the system LSI that carries out the AV processing, the method that the time of using frequency of access to descend in waiting during the vertical blank of image output is with etc. are representative.
Patent documentation 1: TOHKEMY 2000-311484 communique
In addition, in the memory access control circuit that the aforesaid storer that needs are refreshed is controlled, along with the refreshing frequency that the increase of memory span is required is taken advantage of increase with 2 power, therefore refresh shared bandwidth also along with the increase of memory span is taken advantage of increase with 2 power.
Under such situation, there is following pointed problem in described 2 kinds of methods.
For often refreshing, become in access under the situation of peak value each functional module, the bandwidth that wherein refreshes directly will be by congested, and therefore the peak bandwidth that should compensate increases.
On the other hand, often refresh the problem that has though concentrate to refresh can not produce, need carry out all required refreshing frequencies in the short time band that frequency of access descends, therefore the bandwidth that refreshes in refreshing concentrated time band becomes big.At this time, when using the bigger mass storage of required refreshing frequency, the bandwidth that refreshes will substantially exceed because the occupied bandwidth that frequency of access descends and reduces, the opposite higher peak bandwidth of generation that will cause sometimes.
Summary of the invention
The present invention produces in view of above-mentioned existing problem, its purpose is to provide a kind of storage control device, come the peak bandwidth of storage access is carried out smoothing by suitably cutting apart the required bandwidth of refresh activity, can finish required refresh activity by lower peak bandwidth thus.
The storage control device that the 1st aspect of the present invention relates to, it carries out storer control by the access of carrying out a plurality of requestors of access request from the storer that refreshes at needs being mediated, controlling, it is characterized in that, this storage control device comprises memory access control circuit, described memory access control circuit has: circuit is mediated in access, and it is mediated the memory access requests from described a plurality of requestors at described storer; And a plurality of refresh requests circuit, it mediates the refresh requests that circuit carries out described storer to described access, often refresh requests circuit and one or more refresh requests circuit provisory constitute described a plurality of refresh requests circuit by one, the described circuit of refresh requests is often mediated the refresh requests that circuit always continues the described storer of output to described access, perhaps always export the refresh requests of described storer at interval with certain hour, described refresh requests circuit provisory satisfy its refresh requests of setting separately issue condition during the refresh requests that circuit continues the described storer of issue is mediated in described access.
The storage control device that the 2nd aspect of the present invention relates to, in the storage control device of aspect the 1st, putting down in writing, it is characterized in that, all or part of of described a plurality of requestors is to described memory access control circuit, output is that the frequency of access that setting becomes ON when following reduces signal in the frequency of access at described storer, to reduce described a plurality of requestors' all or part of the quantity of signal identical for be provided with quantity and the described frequency of access of output of described refresh requests circuit provisory, and the described described refresh requests issue condition that respectively has the refresh requests circuit of condition is that to reduce signal be ON to pairing described frequency of access.
The storage control device that the 3rd aspect of the present invention relates to, in the storage control device aspect the 2nd, it is characterized in that, mediate in the circuit at described storer, the described access permission frequency that described refresh requests circuit provisory is set be the described frequency of access according to the described request person output corresponding with this refresh requests circuit provisory when reducing signal and being OFF value and the difference of the value during for ON set, mediate in the circuit at described storer, the described access permission frequency that the described circuit of refresh requests is often set is configured to, and the refreshing frequency of Zhi Hanging and the described storer difference of required refreshing frequency and the refreshing frequency carried out in described certain hour by described refresh requests circuit provisory in described certain hour is identical within a certain period of time.
The storage control device that the 4th aspect of the present invention relates to, in the storage control device aspect the 3rd, it is characterized in that, the requestor who described access is mediated circuit issue memory requests is the image processing circuit that carries out Flame Image Process, periodically repeat between the frequent active period of the access of external memory storage and the sparse interregnum of described access as the requestor of this image processing circuit, described memory access control circuit have with as the corresponding refresh requests circuit described provisory of the requestor of described image processing circuit, the signal that expression is in interregnum as the requestor of described image processing circuit reduces signal as described frequency of access to be used.
The storage control device that relates to according to the 1st aspect or the 2nd aspect by above-mentioned formation, can suitably mix and often refresh and concentrate and refresh, can avoid peak value owing to storage access, refresh congestedly produce higher peak bandwidth.
In addition, the storage control device that relates to according to the 3rd aspect, can provide and often to refresh and concentrate and refresh with certain recently providing, alleviate the simple memory access control method of peak bandwidth with information according to the requestor's of priori prediction bandwidth variations.
In addition,, can be provided in the signal conditioning package of handling image, can alleviate the simple memory access control method of the peak bandwidth that refreshes according to the storage control device that the invention of the 4th aspect relates to.
Description of drawings
Fig. 1 is the figure of formation of the storage control device of expression embodiments of the present invention 1.
Fig. 2 is illustrated in the storage control device of embodiment 1, the concept map of the refresh activity when often refreshing with 2 concentrated refreshing.
Fig. 3 is a concept map of only representing the refresh activity when often refreshing.
Fig. 4 is the concept map of the refresh activity when representing only by 2 concentrated refreshing.
Description of reference numerals
1000, storage control device 100, memory access control circuit 10, external memory storage 20, the 1st requestor 21, the 2nd requestor 30, often refresh requests person 40, the 1st concentrates refresh requests person 41, the 2nd concentrates refresh requests person 50, often the refreshing frequency register 60, the 1st concentrates refreshing frequency register 61, the 2nd concentrates refreshing frequency register 70, the 1st requestor's frequency dropping signal 71, the 2nd requestor's frequency dropping signal 80, the 1st concentrates refresh request signal 81, the 2nd concentrates refresh request signal 82, refresh request signal often 90, refresh cycle counter A0 often, the 1st concentrates refresh cycle counter A1, the 2nd concentrates refresh cycle counter B0, arbiter
Embodiment
(embodiment 1)
Utilize Fig. 1 that the storage control device of embodiments of the present invention 1 is described.
Fig. 1 is the pie graph of the storage control device 1000 of expression embodiments of the present invention 1.
In storage control device shown in Figure 1 1000,100 pairs of memory access control circuits are controlled at the access from a plurality of requestors of the storer that needs refresh, it links to each other with the external memory storage 10 that described needs refresh, and is connected with the 1st requestor 20 and the 2nd requestor 21 that this external memory storage 10 are carried out access request respectively.
In addition, this memory access control circuit 100 have inside include refreshing frequency register 50 often and often refresh cycle counter 90 refresh requests person often 30, include and the 1st concentrate refreshing frequency register 60 and the 1st to concentrate the 1st of refresh cycle counter A0 to concentrate refresh requests person 40, include the 2nd and concentrate refreshing frequency register 61 and the 2nd to concentrate the 2nd of refresh cycle counter A1 to concentrate refresh requests person 41 and arbiter B0.
Described arbiter B0 and described the 1st requestor the 20, the 2nd requestor 21, often refresh requests person the 30, the 1st concentrates refresh requests person 40 and the 2nd to concentrate refresh requests person 41 to be connected, acceptance is from separately request and mediation, concentrates refresh requests person the 40, the 2nd to concentrate refresh requests person the 41, the 1st requestor 20 and the 2nd requestor's 21 order preferentially to accept according to refresh requests person the 30, the 1st often.
Described memory access control circuit 100 bases are by the selected requestor of arbiter B0, to external memory storage 10 issue an orders.Particularly when refresh requests person often the 30, the 1st concentrates refresh requests person the 40, the 2nd to concentrate among the refresh requests person 41 any one selected, to external memory storage 10 issue refresh commands.Here, refreshing required period is 20 circulations.
Often refresh requests person 30 within it portion have often refreshing frequency register 50 and often refresh cycle counter 90, and be connected with arbiter B0 by refresh request signal often 82.
Often refresh cycle counter 90 is to increase by 1 counter at circulation each time, in the value of this counter with when often the setting value of refreshing frequency register 50 is equal, circulates at it next time and to return 0.When often refresh cycle counter 90 was identical value, often refresh requests person 30 was made as ON with refresh request signal often 82 at refreshing frequency register 50 often, and to arbiter B0 issue request.
The 1st concentrated refresh requests person 40 portion within it has the 1st concentrated refreshing frequency register 40 and the 1st concentrated refresh cycle counter A0, be connected with arbiter B0 by the 1st concentrated refresh request signal 80, be connected with the 1st requestor 20 by the 1st requestor's frequency dropping signal 070.
The 1st concentrates refresh cycle counter A0 only to increase by 1 counter at circulation each time when the 1st requestor's frequency dropping signal 70 is ON, when the value of this counter and the 1st concentrates the setting value of refreshing frequency register 60 to equate, circulate at it next time and to return 0.When the 1st concentrated refreshing frequency register 60 and the 1st to concentrate refresh cycle counter A0 to be identical value, the 1st concentrated refresh requests person 40 to concentrate refresh request signal 80 to be made as ON with the 1st, and to arbiter B0 issue request.
The 2nd concentrated refresh requests person 41 portion within it has the 2nd concentrated refreshing frequency register 61 and the 2nd concentrated refresh cycle counter A1, be connected with arbiter B0 by the 2nd concentrated refresh request signal 81, be connected with the 2nd requestor 21 by the 2nd requestor's frequency dropping signal 71.
The 2nd concentrates refresh cycle counter A1 only to increase by 1 counter at circulation each time when the 2nd requestor's frequency dropping signal 71 is ON, when the value of this counter and the 2nd concentrates the setting value of refreshing frequency register 61 to equate, circulate at it next time and to return 0.When the 2nd concentrated refreshing frequency register 61 and the 2nd to concentrate refresh cycle counter A1 to be identical value, the 2nd concentrated refresh requests person 41 to concentrate refresh request signal 81 to be made as ON with the 2nd, and to arbiter B0 issue request.
Suppose to learn in advance that the 1st requestor 20 and the 2nd requestor 21 have following feature about memory access requests.That is, to continue the high time (hereinafter referred to as between active period) of frequency of access during the 15.2ms, afterwards, to continue the low time band (hereinafter referred to as interregnum) of frequency of access during the 1.4ms.Repeat periodically above during.
The 1st requestor 20 is made as OFF with the 1st requestor's frequency dropping signal 70 between active period, at interregnum the 1st requestor's frequency dropping signal 70 is made as ON.In addition, the 2nd requestor 21 is made as OFF with the 2nd requestor's frequency dropping signal 71 between active period, at interregnum the 2nd requestor's frequency dropping signal 71 is made as ON.
The 1st requestor 20 is about 40MHz at the peak value of the necessary occupied bandwidth between active period, and the 1st requestor 20 is 35MHz in the necessary occupied bandwidth of interregnum.On the other hand, the 2nd requestor 21 is about 20MHz at the peak value of the necessary occupied bandwidth between active period, and the 2nd requestor 21 is about 10MHz in the necessary occupied bandwidth of interregnum.
In addition, the 2nd requestor 21 and the 1st requestor 20 are requestors of non-synchronization action, and be inconsistent with the zero hour of interregnum between the active period of the two.
Below, the action of the storage control device 1000 of present embodiment 1 is described.
At first, in the storage control device 1000 of formation shown in Figure 1, the value that setting was equivalent to for 15.4 μ seconds is as the setting value of refreshing frequency register 50 often, the value that setting was equivalent to for 4 μ seconds is as the 1st setting value of concentrating refreshing frequency register 60, sets the value that was equivalent to for 2 μ seconds as the 2nd setting value of concentrating refreshing frequency register 61.The movement oscillogram of the refresh request signal often 82 of this moment shown in Figure 2, each concentrated refresh request signal 80,81 and each requestor's frequency dropping signal 70,71.
Set according to this, often the every 64m of refresh requests person 30 issues 4155 times refresh requests second.On the other hand, the 1st requestor the 20, the 2nd requestor 21 produces the 5.39m interregnum of second in during 64m second.Therefore, the 1st concentrates refresh requests person 40 to carry out 1347 times refresh requests in the 1st requestor's 20 interregnum, and the 2nd concentrates refresh requests person 41 to issue 2695 times refreshing in the 2nd requestor's 21 interregnum.
Therefore, often refresh requests person the 30, the 1st concentrate refresh requests person the 40, the 2nd to concentrate refresh requests person 41 to be issued all be 8197 times in refreshing during 64m second, satisfy required refreshing frequency.
At this moment, when considering the occupied bandwidth corresponding with external memory storage 10, under the 1st requestor 20 and the 2nd requestor 21 are in situation between active period, often refresh requests person 30 occupies 1.3MHz, the 1st requestor 20 occupies 40MHz, the 2nd requestor 21 occupies 20MHz, so the occupied bandwidth corresponding with described external memory storage 10 is 61.3MHz.
When the 1st requestor 20 is between active period, the 2nd requestor 21 is under the situation of interregnum, often refresh requests person 30 occupies 1.3MHz, the 1st requestor 20 occupies 40MHz, the 2nd requestor 21 occupies 10MHz, the 2nd concentrates refresh requests person 41 to occupy 10MHz, so the occupied bandwidth corresponding with described external memory storage 10 is 61.3MHz.
When the 1st requestor 20 is in interregnum, the 2nd requestor 21 is under the situation between active period, often refresh requests person 30 occupies 1.3MHz, the 1st requestor 20 occupies 35MHz, the 1st concentrates refresh requests person 40 to occupy 5MHz, the 2nd requestor 21 occupies 20MHz, so the occupied bandwidth corresponding with described external memory storage 10 is 61.3MHz.
When the 1st requestor 20 and the 2nd requestor 21 are under the situation of interregnum, often refresh requests person 30 occupies 1.3MHz, the 1st requestor 20 occupies 35MHz, the 1st concentrates refresh requests person 40 to occupy 5MHz, the 2nd requestor 21 occupies 10MHz, the 2nd concentrates refresh requests person 41 to occupy 10MHz, so the occupied bandwidth corresponding with described external memory storage 10 is 61.3MHz.
Below, corresponding therewith, consideration is not used situation about refreshing of the present invention, situation about promptly only refreshing by described refresh requests person often 30 and is only concentrated refresh requests person 40 and the 2nd to concentrate the bandwidth that refreshes under the situation that refresh requests person 41 refreshes by the described the 1st in the storage control device 1000 of formation shown in Figure 1.
1) at first, shown in Figure 3 in the storage control device 1000 of formation shown in Figure 1, do not use based on the 1st and concentrate refresh requests person 40 and the 2nd to concentrate the situation of refresh requests person 41 refresh activity, promptly do not use the 1st, the 2nd these two concentrated refresh requests persons 40,41, and only carry out refresh activity under all situations about refreshing by refresh requests person 30 often.
In this case, often refresh requests person 30 need carry out during 64m second and refresh for 8192 times, therefore the bandwidth of occupying 2.56MHz.Therefore, when the 1st requestor 20 and the 2nd requestor 21 were between active period, total occupied bandwidth was 62.56MHz.
2) then, shown in Figure 4 in the storage control device 1000 of formation shown in Figure 1, only use the 1st to concentrate refresh requests person 40 and the 2nd to concentrate the bandwidth that refreshes under the situation that refresh requests person 41 refreshes.
In this case, the 1st to concentrate the summation of the refreshing frequency that refreshing frequency that refresh requests person 40 should issue at the 1st requestor's 20 interregnum and the 2nd concentrated refresh requests person 41 should issue at the 2nd requestor's 21 interregnum be 8192 times in second at 64m.
During empty during 64m second is 5.39m second, therefore the 1st concentrate refresh requests person 40 and the 2nd concentrate refresh requests person 41 need be during this 5.39m second in the refreshing of issue total 8192 times.Like this, when the 1st concentrates refresh requests person 40 and the 2nd to concentrate refresh requests person 41 all to be in interregnum the 1st concentrate refresh requests person 40 and the 2nd concentrate refresh requests person 41 refresh shared bandwidth and be 29.87MHz, be 74.87MHz after adding the 1st requestor 20 and the 2nd requestor's 21 bandwidth.
This need not concentrate refresh requests person 40 and the 2nd to concentrate refresh requests person 41 refresh activity and the bandwidth of the bigger 74.87MHz of total occupied bandwidth 62.56MHz when only carrying out all refreshing by refresh requests person 30 often than not using in the storage control device 1000 of formation shown in Figure 1 based on the 1st, method by the invention described above, in contrast to this, can dwindle bandwidth.
In addition, in present embodiment 1, the requestor who described access is mediated circuit issue memory access requests can be the image processing circuit that carries out Flame Image Process.
At this moment, this image processing circuit periodically repeats between the frequent active period of the access of described external memory storage and the sparse interregnum of described access, but described memory access control circuit has the described provisory refresh requests circuit corresponding with described image processing circuit, by representing that the signal that described image processing circuit is in interregnum uses as described frequency of access dropping signal, can constitute the simple memory access control method that can in the signal conditioning package of handling image, reduce the peak bandwidth that refreshes.
Like this, according to the storage control device 1000 of present embodiment 1, the access-control scheme that the storer that refreshes with needs is corresponding has: circuit is mediated in access, and its requestor at the request storage access mediates storage access; And a plurality of refresh requests circuit, it is mediated circuit with described access and is connected respectively, described access is mediated circuit and is come grand access according to the access permission frequency that connected requestor is set respectively, in the described refresh requests circuit one is a refresh requests circuit often, this often the refresh requests circuit circuit mediated in described access always continue the output request, perhaps circuit is mediated in described access and always export request at interval with certain hour, refresh requests circuit in addition is a refresh requests circuit provisory, this refresh requests circuit provisory continues issue during the satisfied refresh requests issue condition of setting at each this refresh requests circuit asks, in addition, described access is mediated requestor or the requestor group of received frequency of access of circuit beyond it carries out described refresh requests circuit the requestor of this mediation and is reduced signal, described refresh requests circuit provisory that quantity is set is identical with the quantity that the described frequency of access of output reduces signal, the refresh requests issue condition of this refresh requests circuit provisory is that pairing described frequency of access reduction signal is ON, so can suitably mix and often refresh and concentrate and refresh, obtain and to avoid because the peak value of storage access, refresh congested and produce the effect of higher peak bandwidth.
In addition, mediate in the circuit in described access, the access permission frequency that described refresh requests circuit provisory is set is that the value when reducing signal and be OFF according to the described frequency of access by described request person's prediction of correspondence and the difference of the value during for ON are set, mediate in the circuit in described access, the access permission frequency that the described circuit of refresh requests is often set is preestablished, can carry out number of times and described storer required refreshing frequency and be contemplated as the identical degree that refreshes of difference of the refreshing frequency of in described certain hour, carrying out by described refresh requests circuit provisory in described certain hour within a certain period of time, can often refresh and concentrate and refresh with certain recently providing so can provide, alleviate the simple memory access control method of peak bandwidth with information according to the requestor's of priori prediction bandwidth variations.
In addition, to be made as image processing apparatus to the requestor of described access mediation circuit issue memory requests, described image processing apparatus periodically repeats between the frequent active period of the access of described external memory storage and the sparse interregnum of described access, the described provisory refresh requests circuit corresponding with described image processing circuit is set in described memory access control circuit, the signal that this image processing circuit of expression is in interregnum reduces signal as described frequency of access to be used, and the simple memory access control method that can alleviate the peak bandwidth that refreshes at the signal conditioning package of handling image can be provided thus.
Utilizability on the industry
The memory access control circuit that the present invention relates to has in that finish can on the basis of refreshing The effect that suppresses the peak bandwidth of memory access, it is applicable to as AV processes carrying out The memory access control circuit that uses among the large scale system LSI.
Claims (4)
1. storage control device, it carries out storer control by the access of carrying out a plurality of requestors of access request from the storer that refreshes at needs being mediated, controlling, it is characterized in that, this storage control device comprises memory access control circuit, and described memory access control circuit has:
Circuit is mediated in access, and it is mediated the memory access requests from described a plurality of requestors at described storer; And
A plurality of refresh requests circuit, it mediates the refresh requests that circuit carries out described storer to described access,
Often refresh requests circuit and one or more refresh requests circuit provisory constitute described a plurality of refresh requests circuit by one, the described circuit of refresh requests is often mediated the refresh requests that circuit always continues the refresh requests of the described storer of output or always exports described storer with certain hour at interval to described access, described refresh requests circuit provisory satisfy its refresh requests of setting separately issue condition during circuit mediated in described access continue the described refresh requests of issue.
2. storage control device according to claim 1 is characterized in that,
All or part of of described a plurality of requestors is that the frequency of access that setting becomes ON when following reduces signal to the output of described memory access control circuit in the frequency of access at described storer,
To reduce described a plurality of requestors' all or part of the quantity of signal identical for be provided with quantity and the described frequency of access of output of described refresh requests circuit provisory,
The described described refresh requests issue condition that respectively has the refresh requests circuit of condition is that pairing described frequency of access reduction signal is ON.
3. storage control device according to claim 2, it is characterized in that, mediate in the circuit at described storer, the described access permission frequency that described refresh requests circuit provisory is set be the described frequency of access according to the described request person output corresponding with this refresh requests circuit provisory when reducing signal and being OFF value and the difference of the value during for ON set
Mediate in the circuit at described storer, the described access permission frequency that the described circuit of refresh requests is often set is configured to, and the refreshing frequency of Zhi Hanging and the described storer difference of required refreshing frequency and the refreshing frequency carried out in described certain hour by described refresh requests circuit provisory in described certain hour is identical within a certain period of time.
4. storage control device according to claim 3 is characterized in that, the requestor who described access is mediated circuit issue memory requests is the image processing circuit that carries out Flame Image Process,
Periodically repeat between the frequent active period of the access of external memory storage and the sparse interregnum of described access as the requestor of this image processing circuit,
Described memory access control circuit have with as the corresponding refresh requests circuit described provisory of the requestor of described image processing circuit, the signal that expression is in interregnum as the requestor of described image processing circuit reduces signal as described frequency of access to be used.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP201493/2005 | 2005-07-11 | ||
| JP2005201493 | 2005-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101223605A true CN101223605A (en) | 2008-07-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800254552A Withdrawn CN101223605A (en) | 2005-07-11 | 2006-07-04 | Memory control device |
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| Country | Link |
|---|---|
| US (1) | US20090129214A1 (en) |
| JP (1) | JPWO2007007599A1 (en) |
| CN (1) | CN101223605A (en) |
| WO (1) | WO2007007599A1 (en) |
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| CN113535089A (en) * | 2020-05-22 | 2021-10-22 | 长江存储科技有限责任公司 | Method for refreshing mapping table of SSD |
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| WO2009139109A1 (en) * | 2008-05-13 | 2009-11-19 | パナソニック株式会社 | Memory control device and information processing device using the same |
| JP5155221B2 (en) * | 2009-03-11 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | Memory control device |
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| JPH11353872A (en) * | 1998-06-04 | 1999-12-24 | Oki Electric Ind Co Ltd | Memory interface circuit |
| JP2000235789A (en) * | 1999-02-16 | 2000-08-29 | Hitachi Ltd | Memory controller |
| JP2002366944A (en) * | 2001-06-06 | 2002-12-20 | Sony Corp | Image processor |
| JP2005107648A (en) * | 2003-09-29 | 2005-04-21 | Hitachi Ulsi Systems Co Ltd | Memory controller |
-
2006
- 2006-07-04 US US11/995,302 patent/US20090129214A1/en not_active Abandoned
- 2006-07-04 JP JP2007524589A patent/JPWO2007007599A1/en active Pending
- 2006-07-04 WO PCT/JP2006/313339 patent/WO2007007599A1/en active Application Filing
- 2006-07-04 CN CNA2006800254552A patent/CN101223605A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113535089A (en) * | 2020-05-22 | 2021-10-22 | 长江存储科技有限责任公司 | Method for refreshing mapping table of SSD |
| CN113535089B (en) * | 2020-05-22 | 2024-05-17 | 长江存储科技有限责任公司 | Refreshing method for mapping table of SSD |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090129214A1 (en) | 2009-05-21 |
| JPWO2007007599A1 (en) | 2009-01-29 |
| WO2007007599A1 (en) | 2007-01-18 |
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