CN101221960B - Pixel structure - Google Patents
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- CN101221960B CN101221960B CN2008100010652A CN200810001065A CN101221960B CN 101221960 B CN101221960 B CN 101221960B CN 2008100010652 A CN2008100010652 A CN 2008100010652A CN 200810001065 A CN200810001065 A CN 200810001065A CN 101221960 B CN101221960 B CN 101221960B
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Abstract
The invention discloses a pixel structure which is arranged on a substrate and electrically connected with a scanning wire and a data line, wherein, the pixel comprises a semi-conductor pattern and a pixel electrode. The semi-conductor pattern comprises at least two channel regions, at least one doped region and a source electrode region as well as a drain electrode region. The channel regions are positioned below the scanning wire, wherein, the channel regions have different width/length ratios. The doped region is connected between the channel regions. The pixel electrode is electrically connected with the drain electrode region, wherein, the source electrode region is connected between one of the channel regions and the data line, and the drain electrode region is connected between the other channel region and the pixel electrode. The scanning wires above different channel regions have different widths, and the length of each channel region is equal to the width of the scanning wire.
Description
Technical field
The present invention relates to a kind of dot structure, and relate in particular to a kind of dot structure with multichannel district.
Background technology
(Thin Film Transistor Liquid Crystal Display TFT-LCD) becomes main flow in present many flat-panel screens to TFT thin film transistor monitor.According to the channel layer Material Selection, Thin Film Transistor-LCD can be divided into amorphous silicon film transistor (amorphous silicon TFT) LCD and low-temperature polysilicon film transistor, and (Low-Temperature PolySilicon Thin FilmTransistor, LTPS-TFT) LCD etc. is two kinds.
Because the electron mobility of low-temperature polysilicon film transistor can reach 200cm
2More than/the V-sec, thus can make the thin-film transistor element area occupied littler of meeting the demand of high aperture (aperture), and then promote the display brightness of display and reduce whole power consumption problem.But comparatively speaking, low-temperature polysilicon film transistor also has higher leakage current (leakage current) and (is about 10
-9Micromicroampere), and brings out hot carrier effect (hot carrier effect) in drain electrode (drain) easily, and then cause element to be degenerated.Therefore, add shallow doped-drain (Light Doped Drain, abbreviation LDD) between many now channel regions in low-temperature polysilicon film transistor and source/drain or utilize the design in multiplexor district, to avoid the problems referred to above.
Fig. 1 is the dot structure of the polycrystalline SiTFT LCD of prior art.Please refer to Fig. 1, dot structure 100 comprises scan line 110, data wire 120, polysilicon layer 130 and transparent pixels electrode 140.Scan line 110 has at least one L type branch 112, and polysilicon layer 130 intersects to form first passage district 132 and second channel district 134 with L type branch 112.In addition, the two ends of low-temperature polycrystalline silicon layer 130 have source area 136 and drain region 138 respectively, to form the polycrystalline SiTFT 150 of multichannel design.Data wire 120 electrically connects source area 136, and transparent pixels electrode 140 then electrically connects drain region 138.In addition, polysilicon layer 130 more constitutes a storage capacitors 152 with the part that pixel electrode 140 overlaps.Because multichannel design, low-temperature polysilicon film transistor 150 have lower leakage current under closing state, and help to promote the quality of dot structure 100.Yet the configuration of L type branch 112 but can influence the position that storage capacitors 152 disposed and the demonstration aperture opening ratio that makes dot structure 100 descends.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of dot structure, the problem that the polycrystalline SiTFT that designs with the solution multichannel is restricted the demonstration aperture opening ratio of dot structure.
For achieving the above object, the present invention proposes a kind of dot structure, is disposed on the substrate and with an one scan line and a data wire to electrically connect, and dot structure comprises a semiconductor pattern and a pixel electrode.Semiconductor pattern comprises at least two channel regions, at least one doped region and one source pole district and a drain region.Channel region is positioned at the scan line below, and wherein channel region has different width to length ratio values.Doped region is connected between the channel region.Pixel electrode and drain region electrically connect, and wherein source area is connected between one of them channel region and the data wire, and the drain region is connected between another channel region and the pixel electrode.Scan line has different width above different channel regions, and a length of each channel region equates with the width of scan line.
In one embodiment of this invention, above-mentioned scan line has different width above different channel regions, and a length of each channel region equates with the width of scan line.
In one embodiment of this invention, above-mentioned scan line has a branch, and branch is perpendicular to scan line.Wherein at least one channel region is positioned at branch below, and it is identical with the width of branch to be positioned at the length of channel region of branch below.
In one embodiment of this invention, above-mentioned semiconductor pattern comprises poly-silicon pattern.
In one embodiment of this invention, above-mentioned semiconductor pattern also comprises a capacitance electrode, electrically connects with drain region and pixel electrode, and wherein capacitance electrode is positioned at the pixel electrode below.In addition, dot structure comprises that also one shares electrode, is disposed between capacitance electrode and the pixel electrode.
In one embodiment of this invention, the shape of above-mentioned doped region comprises L shaped or U-shaped.
In one embodiment of this invention, part scan line, source area and the drain region of above-mentioned channel region below constitute a polycrystalline SiTFT.
And for achieving the above object, the present invention proposes a kind of dot structure in addition, comprises one scan line, a data wire, semiconductor pattern and a pixel electrode.Scan line and data wire are staggered, and have a branch, and branch is positioned at the data wire below.Semiconductor pattern comprises at least two channel regions, at least one doped region and one source pole district and a drain region.Channel region is positioned at the scan line below, and wherein channel region has different width to length ratio values.Doped region is connected between the channel region.Pixel electrode and drain region electrically connect, and wherein source area is connected between one of them channel region and the data wire, and the drain region is connected between another channel region and the pixel electrode.
In one embodiment of this invention, the length of the above-mentioned channel region that is positioned at the branch below is identical with the width of branch.
In one embodiment of this invention, above-mentioned semiconductor pattern comprises poly-silicon pattern.
In one embodiment of this invention, above-mentioned semiconductor pattern also comprises a capacitance electrode, electrically connects with drain region and pixel electrode, and wherein capacitance electrode is positioned at the pixel electrode below.In addition, dot structure comprises that also one shares electrode, is disposed between capacitance electrode and the pixel electrode.
In one embodiment of this invention, above-mentioned capacitance electrode and the branch both sides that lay respectively at scan line.
In one embodiment of this invention, the shape of above-mentioned doped region comprises L shaped.
In one embodiment of this invention, above-mentioned semiconductor pattern is extended to second side of data wire by first side of data wire.
In one embodiment of this invention, part scan line, source area and the drain region of above-mentioned channel region below constitute a polycrystalline SiTFT.
The present invention utilizes the variation of semiconductor pattern to make semiconductor pattern and scan line intersect at two zones at least, and helps to reduce the leakage current of polycrystalline SiTFT.In addition, the present invention is arranged at the data wire below with the branch of scan line, can further avoid the demonstration aperture opening ratio of dot structure influenced.Generally speaking, dot structure provided by the present invention has and high shows that the polycrystalline SiTFT in aperture opening ratio and the dot structure has excellent electrical property.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the dot structure schematic diagram of the polycrystalline SiTFT LCD of prior art;
Fig. 2 is the dot structure schematic diagram of one embodiment of the invention;
Fig. 3 illustrates the dot structure schematic diagram into another embodiment of the present invention;
Fig. 4 illustrates the dot structure schematic diagram into an embodiment more of the present invention;
Fig. 5 A and Fig. 5 B are two kinds of dot structure schematic diagrames of another embodiment of the present invention;
Fig. 6 illustrates the dot structure schematic diagram into an embodiment more of the present invention.
Wherein, Reference numeral:
100,200,300,400,500,600: dot structure
110,210,410,510: scan line
112,412,512: branch
120,220,520: data wire
130: polysilicon layer
132,134,232A, 232B, 332A, 332B, 332C, 432,532A, 532B, 632A, 632B, 632C: channel region
136,236,336,536: source area
138,238,538: the drain region
140,240,540: pixel electrode
150,250,350,450,550,650: polycrystalline SiTFT
152: storage capacitors
230,330,530,630: semiconductor pattern
234,334A, 334B, 434A, 434B, 534,634A, 634B: doped region
252,552: capacitance electrode
560: shared electrode
L, L1, L2: length
Td, Ts: contact hole
D, D1, D2, D3: width
Embodiment
Fig. 2 is the dot structure of one embodiment of the invention.Please refer to Fig. 2, dot structure 200 electrically connects an one scan line 210 and a data wire 220, and wherein scan line 210 and data wire 220 are staggered.Dot structure 200, scan line 210 and data wire 220 for example are to be disposed on the substrate (not illustrate).Dot structure 200 comprises a semiconductor pattern 230 and a pixel electrode 240.Semiconductor pattern 230 comprises at least two channel region 232A, 232B, at least one doped region 234 and one source pole district 236 and a drain region 238. Channel region 232A, 232B are positioned at scan line 210 belows, and wherein channel region 232A has different width to length ratio values with channel region 232B.Doped region 234 is connected between channel region 232A and the channel region 232B.Pixel electrode 240 electrically connects with drain region 238, and wherein source area 236 is connected between channel region 232A and the data wire 220, and drain region 238 is connected between channel region 232B and the pixel electrode 240.
The part scan line 210 that is arranged in channel region 232A and channel region 232B below can be considered grid at dot structure 200, with the open and close of control dot structure 200.In addition, semiconductor pattern 230 for example is to be made by the polysilicon material, that is to say that semiconductor pattern 230 is a poly-silicon pattern.Therefore, the part scan line 210 of channel region 232A and channel region 232B below, source area 236 and drain region 238 common formation one polycrystalline SiTFTs 250.When polycrystalline SiTFT 250 was closed, the crystal grain interface of poly-silicon pattern may cause the phenomenon of leakage current among channel region 232A, the 232B, and influences the quality of dot structure 200.In order to solve the problem that may cause leakage current when polycrystalline SiTFT 250 is closed, the notion of multiplexor design is suggested.Yet, by prior art as can be known, the demonstration aperture opening ratio that can be influenced dot structure 200 by scan line 210 along the branch that stretches is set for the multiplexor design.So the present invention utilizes the warpage structure of semiconductor pattern 230 to reach multichannel design in this proposition.
The semiconductor pattern 230 of present embodiment for example has the structure of multi-winding, and is overlapped in a plurality of zones and constitutes multiplexor with scan line 210.Semiconductor pattern 230 is a transparent pattern, so the demonstration aperture opening ratio of dot structure 200 can not be affected because of the design of the multiplexor of present embodiment.That is to say that the dot structure 200 of present embodiment is difficult for having the phenomenon of leakage current to take place, and can keep good demonstration aperture opening ratio simultaneously.
Specifically, when polycrystalline SiTFT 250 was opened, electric current for example was perpendicular to the bearing of trend of scan line 210 in the transmission direction of channel region 232A and 232B.So the width D 1 of scan line 210, D2 can influence length L 1, the L2 of channel region 232A, 232B.In general, the length L 1 of channel region 232A, 232B, the long more leakage current that then helps to reduce polycrystalline SiTFT 250 of L2.Therefore, for the length L 2 that increases channel region 232B, it for example is in other regional width D 1 greater than scan line 210 that scan line 210 is arranged in channel region 232B width D 2.Certainly, in other embodiments,, the width of scan line 210 in channel region 202A broadened for the length L 1 that increases channel region 232A.
Certainly, contact hole Td and contact hole Ts are positioned at the relative both sides of scan line 210.Fig. 3 illustrates the dot structure into another embodiment of the present invention.Please refer to Fig. 3, dot structure 300 is similar to the design of dot structure 200, and wherein the contact hole Td of dot structure 300 and contact hole Ts are positioned at the relative both sides of scan line 210.In addition, the semiconductor pattern 330 of dot structure 300 has doped region 334A, the 334B of three channel region 332A, 332B, 332C and two U types.At this moment, the part scan line 210 of channel region 332A, 332B, 332C below, source area 236 and drain region 238 common formation one polycrystalline SiTFTs 350.
In the present embodiment, scan line 210 has different width D 1, D2 and D3 respectively with the part that semiconductor pattern 330 intersects.So channel region 332A, channel region 332B and channel region 332C can have different width to length ratio values.On the practice, scan line 210 can be greater than the width of scan line 210 in other zone, so that polycrystalline SiTFT 350 has electric characteristics preferably corresponding to the width D among channel region 332A, 332B, the 332C 1, D2, D3.In addition, semiconductor pattern 330 for example is that the polysilicon material is made, and the polysilicon material has the characteristic of light-permeable.Therefore, the structure of bended semiconductor pattern 330 can reach the design of multiplexor in the present embodiment, and makes dot structure 300 have good demonstration aperture opening ratio simultaneously.
Fig. 4 illustrates and is the dot structure of an embodiment more of the present invention.Please refer to Fig. 4, dot structure 400 is similar to the dot structure 200 of Fig. 2, and data wire 420 is staggered with scan line 410, and its difference is that scan line 410 has a branch 412, and branch 412 intersects with semiconductor pattern 230.Semiconductor pattern 230 constitutes channel region 432 with the part that branch 412 intersects, and doped region 434A and 434B then are respectively between channel region 232A and channel region 432, and between channel region 232B and the channel region 432.On the practice, the semiconductor pattern 230 of present embodiment is identical with the external form of the semiconductor pattern 230 of Fig. 2, and has three channel region 232A, 232B and 432 in the dot structure 400 owing to the design of branch 412 makes.In addition, the external form of doped region 434A and 434B also changes over two L types by the U type.
In addition, branch 412 is a rectangular patterns, and compared to the L type branch 112 of prior art, the design of present embodiment helps to make dot structure 400 to possess good demonstration aperture opening ratio.Branch 412 and capacitance electrode 252 lay respectively at the both sides of scan line 410, so the allocation position of capacitance electrode 252 and area can not be subjected to the influence of branch 142.That is to say that along with different design requirements, capacitance electrode 252 is configurable on any position of scan line 410 and 220 regions of data wire.In addition, the bearing of trend of branch 412 is perpendicular to the bearing of trend of scan line 410, and the length of the channel region 432 of branch 412 belows is identical with the width D of branch 412.Therefore, scan line 410 can make with the line width variation of branch 412 different length width ratio between each channel region 232A, 232B and 432.The 230 identical designs of present embodiment utilization and semiconductor pattern make dot structure 400 have plural channel region 232A, 232B and 432, to promote the quality of dot structure.
Fig. 5 A and Fig. 5 B are two kinds of dot structures of another embodiment of the present invention.Please refer to Fig. 5, dot structure 500 comprises one scan line 510, a data wire 520, semiconductor pattern 530 and a pixel electrode 540.Scan line 510 and data wire 520 are staggered and scan line 510 has a branch 512, and branch 512 is positioned at data wire 520 belows.Semiconductor pattern 530 comprises at least two channel region 532A, 532B, at least one doped region 534 and one source pole district 536 and a drain region 538.
In the present embodiment, semiconductor pattern 530 is extended to second side of data wire 520 by first side of data wire 520.The source area 536 of semiconductor pattern 530 for example is to electrically connect by contact hole Ts and data wire 520, and drain region 538 then is to electrically connect by contact hole Td and pixel electrode 540.In the dot structure 500, contact hole Ts and contact hole Td are positioned at the relative both sides of scan line 510.Therefore, the warpage structure of the semiconductor pattern 530 of present embodiment is crossed the both sides of data wire 520, scan line 510 and branch 512 to be overlapped in a plurality of zones with scan line 510 and branch 512 thereof.So dot structure 500 has a plurality of channel region 532A and 532B, to help to lower the situation that leakage current takes place down polycrystalline SiTFT 550 in off position.In brief, dot structure 500 has good quality.In addition, the branch 512 of scan line 510 is positioned at data wire 520 belows, can further avoid the demonstration aperture opening ratio of dot structure 500 to be affected.
The bearing of trend of branch 512 is perpendicular to the bearing of trend of scan line 510, and the length L 2 of the channel region 532B of branch 512 belows is identical with the width D 1 of branch 512.Therefore, the length L 2 of channel region 532A and 532B, L1 are relevant with width D 1, the D2 of the width of scan line 510 and branch 512 respectively in the present embodiment.If scan line 510 is wide more with width D 1, the D2 of branch 512, then can effectively reduce the leakage current of polycrystalline SiTFT 550 more.
In addition, the display voltage when showing in order to stablize dot structure 500, semiconductor pattern 530 can comprise also that one is positioned at the capacitance electrode 552 of pixel electrode 540 belows, itself and drain region 538 and pixel electrode 540 electrically connect.Further, please refer to Fig. 5 B, dot structure 500 also can dispose shared electrode 560 between pixel electrode 540 and capacitance electrode 552.Because the branch 512 of scan line 510 is positioned at data wire 520 belows,, further make the shared electrode 560 and the Position Design of capacitance electrode 552 have elasticity so the position of shared electrode 560 and capacitance electrode 552 can not be subjected to the configuration of branch 512 and influence.
Fig. 6 illustrates and is the dot structure of an embodiment more of the present invention.Please refer to Fig. 6, dot structure 600 is similar to dot structure 500, and its difference is that semiconductor pattern 630 is different with the external form of semiconductor pattern 530.The semiconductor pattern 630 of dot structure 600 comprises triple channel district 632A, 632B, 632C and two doped region 634A, 634B.In addition, doped region 634A, 634B are connected between channel region 632A, 632B and the 632C.Source area 538 is connected between channel region 632A and the data wire 520, and drain region 638 is connected between channel region 632C and the pixel electrode 540.In addition, capacitance electrode 552 and branch 512 lay respectively at the both sides of scan line 510.
In the present embodiment, the bearing of trend of the branch 512 of scan line 510 is perpendicular to the bearing of trend of scan line 510, and the length L of the channel region 632B of branch 512 belows is identical with the width D of branch 512.Therefore, when the width D 2 of scan line 510 and its branch 51 was wide more, channel region 632A, 632B and 632C can have long passage length, to promote the electric characteristics of polycrystalline SiTFT 650.
In sum, the present invention utilizes different semiconductor pattern designs, makes to have a plurality of channel regions in the dot structure, and the branch with scan line is arranged at the data wire below simultaneously.Therefore, the demonstration aperture opening ratio of dot structure can not be restricted because of the branch of scan line.Also promptly, dot structure of the present invention has the high aperture opening ratio that shows.In addition, in the dot structure of the present invention, semiconductor pattern and scan line are overlapped in a plurality of zones and form a plurality of channel regions, help to reduce the situation that polycrystalline SiTFT in the dot structure produces leakage current in off position the time.Generally speaking, dot structure of the present invention has the high aperture opening ratio that shows, also has good quality simultaneously.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (7)
1. dot structure is disposed on the substrate and with an one scan line and a data wire and electrically connects, and it is characterized in that this dot structure comprises:
The semiconductor pattern, this semiconductor pattern comprises:
One U type doped region;
At least two channel regions, this at least two channel region are intersected with this scan line by the semiconductor pattern that connects these U type doped region two ends and form, and this at least two channel region is positioned at below this scan line, and wherein those channel regions have different width to length ratio values;
An one source pole district and a drain region; And
One pixel electrode electrically connects with this drain region, and wherein this source area is connected between one of them channel region and this data wire, and this drain region is connected between another channel region and this pixel electrode;
Wherein, this scan line has different width above different channel regions, and respectively a length of this channel region equates with a width of this scan line.
2. dot structure according to claim 1 is characterized in that this scan line has a branch, and this branch is perpendicular to this scan line.
3. dot structure according to claim 2 is characterized in that, at least one this channel region is positioned at this branch below, and it is identical with the width of this branch to be positioned at the length of this channel region of this branch below.
4. dot structure according to claim 1 is characterized in that this semiconductor pattern comprises a poly-silicon pattern.
5. dot structure according to claim 4 is characterized in that this semiconductor pattern also comprises a capacitance electrode, electrically connects with this drain region and this pixel electrode, and this capacitance electrode is positioned at this pixel electrode below.
6. dot structure according to claim 5 is characterized in that, comprises that also one shares electrode, is disposed between this capacitance electrode and this pixel electrode.
7. dot structure according to claim 1 is characterized in that, this scan line of part, this source area and this drain region of this channel region below constitute a polycrystalline SiTFT.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100010652A CN101221960B (en) | 2008-01-18 | 2008-01-18 | Pixel structure |
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| CN2008100010652A CN101221960B (en) | 2008-01-18 | 2008-01-18 | Pixel structure |
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| CN2010102345408A Division CN101950746B (en) | 2008-01-18 | 2008-01-18 | Pixel structure |
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| CN101221960B true CN101221960B (en) | 2010-12-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104793415A (en) * | 2014-01-17 | 2015-07-22 | 群创光电股份有限公司 | Thin film transistor substrate, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102549638B (en) * | 2009-10-09 | 2015-04-01 | 株式会社半导体能源研究所 | Light-emitting display device and electronic device including the same |
| JP5982147B2 (en) * | 2011-04-01 | 2016-08-31 | 株式会社半導体エネルギー研究所 | Light emitting device |
| CN103746000B (en) * | 2013-12-25 | 2017-03-08 | 深圳市华星光电技术有限公司 | A kind of polysilicon TFT device and its manufacture method |
| TWI476493B (en) * | 2014-02-14 | 2015-03-11 | Au Optronics Corp | Pixel structure |
| CN105824160B (en) * | 2015-01-08 | 2020-06-16 | 群创光电股份有限公司 | Display panel |
| CN106449651B (en) * | 2016-09-12 | 2019-05-21 | 厦门天马微电子有限公司 | Dot structure and display device |
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| CN1542528A (en) * | 2003-04-29 | 2004-11-03 | 友达光电股份有限公司 | Fabrication method of thin film transistor liquid crystal display panel |
| CN1550826A (en) * | 2003-05-16 | 2004-12-01 | ������������ʽ���� | Liquid crystal device ,active matrix base board,display device and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1542528A (en) * | 2003-04-29 | 2004-11-03 | 友达光电股份有限公司 | Fabrication method of thin film transistor liquid crystal display panel |
| CN1550826A (en) * | 2003-05-16 | 2004-12-01 | ������������ʽ���� | Liquid crystal device ,active matrix base board,display device and electronic device |
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| CN104793415A (en) * | 2014-01-17 | 2015-07-22 | 群创光电股份有限公司 | Thin film transistor substrate, display panel and display device |
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