CN101211970B - Semiconductor device and producing method thereof - Google Patents
Semiconductor device and producing method thereof Download PDFInfo
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- CN101211970B CN101211970B CN2006101482488A CN200610148248A CN101211970B CN 101211970 B CN101211970 B CN 101211970B CN 2006101482488 A CN2006101482488 A CN 2006101482488A CN 200610148248 A CN200610148248 A CN 200610148248A CN 101211970 B CN101211970 B CN 101211970B
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Abstract
The invention relates to a semiconductor apparatus comprising a semiconductor substrate, a gate dielectric layer positioned on the semiconductor substrate, a gate positioned on the gate dielectric layer as well as a source cathode and a drain positioned between the two sides of the dielectric layer in the semiconductor layer. The semiconductor apparatus also comprises a joint interface layer extending along the surface of the source cathode and drain and the joint interface layer extending along the gate surface. The joint interface layers insulate and isolate with the gate dielectric layer. The joint interface layers of the semiconductor apparatus contain doping interface providing a continuous electronic states which can complete the electron transmission under low effect of a electric field, thus reducing the contact desistence between the semiconductor and the joint metal of the contact hole. The apparatus just needs the connection between the super thin doping interface layer and the metal layer so as to further reduce the size of the semiconductor apparatus and increase the density of the semiconductor apparatus.
Description
Technical field
The present invention relates to semiconductor device and preparation method thereof, interconnect structure and preparation method thereof between particularly a kind of semiconductor device.
Background technology
The device architecture of traditional semiconductor memory for example application number is the memory construction that 03145409 Chinese patent provides; As shown in Figure 1; Be formed with gate dielectric 2 and grid 3 on the Semiconductor substrate 1 successively; Said gate dielectric 2 is silicon dioxide or silica-silicon-nitride and silicon oxide layer etc., and said grid 3 is a polysilicon layer.The both sides of gate dielectric 2 and grid 3 have clearance wall (spacer) 5, and the material of clearance wall 5 is silicon dioxide, silicon nitride or silicon oxynitride etc., in the Semiconductor substrate 1 of clearance wall 5 both sides, is formed with source-drain electrode 6.
In the application and manufacture craft of reality, because considering of the engineering design of source-drain electrode for fear of the ionization by collision effect that hot current-carrying ion causes, adopted lightly-doped source/drain electrode (1ightly dopedsource/drain, LDD) structure usually.As shown in Figure 2; Have gate dielectric 12 and grid 13 on the Semiconductor substrate 11 successively; In the Semiconductor substrate 11 of gate dielectric 12 both sides, be formed with low doping source drain region 14; The both sides of gate dielectric 12 and grid 13 have clearance wall 15, in the Semiconductor substrate 11 of clearance wall 15 both sides, are formed with heavy-doped source drain region 16.An effect in heavy-doped source drain region 16 is: be connected Metal Contact in the contact hole, form the ohmic contact (Ohmic Contact) of low contact resistance.When carrying out metal line, 17 expressions,, require metal is infiltrated the heavy-doped source drain region in order to reach lower contact resistance with the interior ohmic contact regions that is connected Metal Contact of contact hole.Ohmic contact regions has the suitable degree of depth.
Above-mentioned semiconductor component structure with clearance wall becomes the motive force of semiconductor technology evolves.Along with the develop rapidly of semiconductor fabrication, semiconductor chip develops towards higher device density, high integration direction.Therefore, the size of semiconductor element is also done littler and littler; The channel length of element is more and more short, and the doped source of requirement/drain electrode degree of depth is also more and more shallow.
Manufacture craft development for ohmic contact regions can be with reference to SiliconMaterial and Device Characterization 2nd Edition 1998 John Wiley and Sons with the method for measurement of contact resistance; ByDieter K.Schroder; The the 133rd to 142 page, when the heavy doping ion concentration range is increased to 5E20/cm by 2E17
3The time, the contact resistance value scope of n type silicon and ohmic contact that metal forms reduces to 3E-8 Ω/cm by 1E-3
2, when the heavy doping ion concentration range is increased to 5E20/cm by 1E16
3The time, the contact resistance value of p type silicon and ohmic that metal forms reduces to 1.5E-8 Ω/cm from 6E-3
2The dopant ion concentration of this technology changes 4 rank, and the variation of contact resistance value reaches rank 5 times, and the variation of contact resistance is through regulating doped region dopant ion concentration and regulating electronic barrier, and dopant ion concentration is higher, and potential barrier reduces.Therefore, this technology strictness relies on the concentration of dopant ion, has limited the degree of depth of source-drain area.
According to the achievement in research (1996 IEEE Symposium on VLSI TechnologyDigest, 14-15 page or leaf) of Texas Instrument, the source-drain area that utilizes Titanium silicide to form, the degree of depth of source-drain area can drop to 500 dusts.The research paper of Toshiba (1994 IEEE Transaction on ElectronDevices, Vo1.41, No.12,2305-2317 page or leaf) for example again, the source-drain area that utilizes titanium or nickel silicide to form, wherein the degree of depth of Titanium silicide can reach near 300 dusts.
Along with constantly reducing of semiconductor element supply power voltage, the tunnel degree of depth and junction depth, the dopant ion density in low doping source drain region is near the dopant ion density in heavy-doped source drain region, to satisfy the needs that reduce contact resistance.Therefore, the technology of distinguishing heavy-doped source drain region and lightly-doped source drain region through clearance wall has seemed and has not been the ten minutes needs, and the existence of clearance wall has also enlarged size of devices, is unfavorable for the trend that device size is more and more littler.It is also more and more high with the specification requirement of passive device (PassiveDevices) to connect active device (Active Devices), and, form more shallow source-drain area, also be a wherein very important link.
Summary of the invention
The problem that the present invention solves provides a kind of semiconductor device and preparation method thereof, reduces device doped region and the interior contact resistance that is connected metal of contact hole, and helps reducing size of devices.
For addressing the above problem; The present invention provides a kind of semiconductor device; Comprise Semiconductor substrate, be positioned at the gate dielectric on the Semiconductor substrate and be positioned at the grid on the gate dielectric, and the source electrode and the drain electrode that are positioned at the gate dielectric both sides in the Semiconductor substrate; Also comprise linkage interface layer that is positioned at source electrode and drain surface extension and the linkage interface layer that extends along gate surface, said linkage interface layer and gate dielectric layer insulation are isolated.
Wherein, said linkage interface layer is the metal reaction alloy, and said alloy is any one in oxygen, nitrogen, hydrogen, boron, arsenic or the phosphorus, the reaction alloy that said metal reaction alloy is cobalt, nickel, molybdenum, titanium, copper or niobium.
Perhaps, the said linkage interface layer metal silicide that is cobalt, nickel, molybdenum, titanium, copper or niobium.Contain any one alloy in aerobic, nitrogen, hydrogen, boron, arsenic or the phosphorus in the said metal silicide.
The thickness of the thickness linkage interface layer of said linkage interface layer is 10 to 50 dusts greater than 0 smaller or equal to 100 dusts preferably.
The present invention also provides a kind of manufacture method of semiconductor device, comprises the steps:
Semiconductor substrate is provided, is formed with gate dielectric and the source electrode and the drain electrode that are positioned at the grid on the gate dielectric and are positioned at the Semiconductor substrate of gate dielectric both sides on the Semiconductor substrate;
On said Semiconductor substrate, form mask, the Semiconductor substrate outside leak in the sidewall of cover gate and gate dielectric and source;
Formation is along the linkage interface layer of source electrode and drain surface extension and the linkage interface layer that extends along gate surface;
Remove said mask.
Compared with prior art, the present invention has the following advantages:
1, semiconductor device provided by the invention has the linkage interface layer in source electrode and drain electrode and gate surface extension; Said linkage interface layer contains available electronic state continuously; Under lower electric field action, can accomplish electric transmission, reduce the contact resistance between the metal that is connected with contact hole.
2, semiconductor device provided by the invention can make the dopant ion concentration of source electrode and drain electrode change in the larger context; The continuous electronic state that utilizes the linkage interface layer to be provided; Even under lower dopant ion concentration conditions, also can reach the low resistance ohmic contact.
3, semiconductor device provided by the invention can use the dopant ion concentration of different source electrodes and drain electrode, to distinguish core and output/input element.Utilize lower dopant ion concentration output/input element, can improve chip reliability.
4, the present invention can reduce size of semiconductor device, has satisfied the trend that semiconductor device is done littler and littler.
Description of drawings
Fig. 1 is the structural representation of prior art semiconductor device;
Fig. 2 is the structural representation that prior art comprises the semiconductor memory of ohmic contact regions;
Fig. 3 is the semiconductor device structure sketch map that the present invention forms;
Fig. 4 A to Fig. 4 E is a manufacturing method of semiconductor device process structure sketch map according to the invention.
Embodiment
Essence of the present invention is to provide a kind of semiconductor device that does not contain clearance wall; Can be transistors such as memory, logical device; Reduce the size of semiconductor device that forms, satisfied the trend that device is done littler and littler, and; Be formed with along the linkage interface layer of source electrode and drain surface extension in source electrode and the corresponding zone of drain electrode; Said linkage interface layer is the metal reaction alloy, and said alloy is any one in oxygen, nitrogen, hydrogen, boron, arsenic or the phosphorus, the reaction alloy of the reaction alloy that said metal reaction alloy is a cobalt, the reaction alloy of nickel, molybdenum, the reaction alloy of titanium, the reaction alloy of copper or the reaction alloy of niobium; The metal silicide that perhaps contains any one alloy in aerobic, nitrogen, hydrogen, boron, arsenic or the phosphorus; Said metal reaction alloy or metal silicide contain available electronic state continuously, under lower electric field action, can accomplish electric transmission, have reduced the contact resistance between the metal that is connected with contact hole.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed practical implementation.
At first; The present invention provides a kind of semiconductor device; Shown in accompanying drawing 3; Comprise Semiconductor substrate 100, be positioned at the gate dielectric 110 on the Semiconductor substrate 100 and be positioned at the grid 120 on the gate dielectric 110, and the source electrode 130 and drain electrode 140 that are positioned at gate dielectric 110 both sides in the Semiconductor substrate 100; Also comprise linkage interface layer 150 that extends along source electrode 130 and drain electrode 140 surfaces and the linkage interface layer 150 that extends along grid 120 surfaces, said linkage interface layer 150 is isolated with gate dielectric layer 110 insulation.
Said Semiconductor substrate 100 can comprise the silicon or the SiGe (SiGe) of monocrystalline or polycrystalline structure; Can also be to contain the for example silicon or the SiGe that mix of N type or P type of dopant ion; The semiconductor structure that also can comprise mixing, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; It also can be silicon-on-insulator (SOI).
Said gate dielectric 110 can be silica (SiO
2) or silicon oxynitride (SiNO).At the following process node of 65nm, the characteristic size of grid is very little, gate dielectric 110 preferred high-k (high K) materials.Said hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.
Said linkage interface layer 150 extends along the surface of source electrode 130 and drain electrode 140 and grid 120; In the accompanying drawing; Linkage interface layer 150 along the surface of source electrode 130 and drain electrode 140 and grid 120 to extending below; According to the difference of linkage interface layer 150 formation technology, linkage interface layer 150 also possibly or extend upward at the surperficial downward simultaneously of source electrode 130 and drain electrode 140 and grid 120, that is to say; Linkage interface layer 150 maybe be to extending in the inside of source electrode 130 and drain electrode 140 and grid 120 on the surface of source electrode 130 and drain electrode 140 and grid 120, also maybe be simultaneously to extending in the outside of source electrode 130 and drain electrode 140 and grid 120.Of the present invention upwards is downwards according to the location expression in the accompanying drawing.
Perhaps, said linkage interface layer be cobalt metal silicide, the metal silicide of nickel, the metal silicide of molybdenum, the metal silicide of titanium, the metal silicide of copper or the metal silicide of niobium.Contain any one alloy in aerobic, nitrogen, hydrogen, boron, arsenic or the phosphorus in the said metal silicide.
The formation technology of said linkage interface layer 150 is under any one the plasma atmosphere in containing argon ion and oxonium ion, nitrogen ion, hydrogen ion, borane ion, arsenic hydride ion or hydrogen phosphide ion; Splash-proofing sputtering metal is cobalt, nickel, molybdenum, titanium, copper or niobium for example; Form infiltration oxonium ion, nitrogen ion, hydrogen ion, boron ion are arranged; Arsenic ion, perhaps the linkage interface layer 150 of any one ion in the phosphonium ion.The thickness of said linkage interface layer 150 is 10 to 50 dusts greater than 0 smaller or equal to 100 dusts preferably.The existence of said linkage interface layer 150 makes the dopant ion density of source electrode and drain region have bigger excursion, and for example, the dopant ion concentration range is that 1E18 is to 6E20/cm
3And in above-mentioned dopant ion concentration range, the conducting metal that all has in the interlayer contact hole has less contact resistance.
Because said metal reaction alloy contains oxonium ion, nitrogen ion, hydrogen ion, boron ion, arsenic ion, therefore perhaps any one in the phosphonium ion, provide continuous electronic energy rank at the linkage interface layer of silicon and metal; Directly, make it be in continuous available electronic state with electronics fermi level (Fermi Level) overlaid of metal.Under very low electric field action, can accomplish electric transmission, reduce the contact resistance between the metal that is connected with contact hole.And can under the situation of the dopant ion concentration of bigger source electrode of scope and drain region, realize low-resistancely electrically contacting.
The present invention also provides a kind of manufacture method of semiconductor device; Comprise the steps: to provide Semiconductor substrate, be formed with gate dielectric and the source electrode and the drain electrode that are positioned at the grid on the gate dielectric and are positioned at the Semiconductor substrate of gate dielectric both sides on the Semiconductor substrate; On said Semiconductor substrate, form mask, the Semiconductor substrate outside leak in the sidewall of cover gate and gate dielectric and source; Formation is along the linkage interface layer of source electrode and drain surface extension and the linkage interface layer that extends along gate surface; Remove said mask.
Below in conjunction with accompanying drawing 4A to 4E said manufacturing method of semiconductor device is done detailed description.Shown in accompanying drawing 4A, Semiconductor substrate 100 is provided, be formed with gate dielectric layer 110 and grid 120 on the Semiconductor substrate 100.The formation technology of gate dielectric 120 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, the thickness of gate dielectric layer 110 is 15 to 60 dusts.The formation technology of said grid 120 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, for example low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technology.The thickness of grid 120 is 800 to 3000 dusts.Is mask with grid 120 with gate dielectric layer 110; Can in the Semiconductor substrate 100 of gate dielectric layer 110 both sides, form source electrode 130 and drain electrode 140; The dopant ion concentration of said source electrode 130 and drain electrode 140 can change in the larger context, and dopant ion concentration is that 1E18 is to 6E20/cm
3The degree of depth of said source electrode 130 and drain electrode 140 is 600 to 2000 dusts.
Shown in accompanying drawing 4B; On the Semiconductor substrate 100, on the grid 120 and the sidewall of grid 120 and gate dielectric layer 110 form etching barrier layer 160; For example photoresist layer, silicon nitride layer etc., the formation technology of said etching barrier layer 160 can adopt any prior art.
Shown in accompanying drawing 4C; The etching barrier layer 160 of correspondence position on the etching barrier layer 160 of correspondence position and the grid 120 in removal source electrode 130 and the drain electrode 140; Simultaneously, keep the etching barrier layer 160 of the sidewall of grid 120 and gate dielectric layer 110, and form opening 170.
Shown in accompanying drawing 4D; With etching barrier layer 160 is mask; Under plasma ambient, carry out metal sputtering, form downwards or downward and upwardly extending linkage interface layer 150 of while at the source electrode 140 of opening 170 correspondences and the surface of drain electrode 130 and grid 120.Said plasma comprises argon ion and oxonium ion, nitrogen ion, hydrogen ion, boron ion, arsenic ion, perhaps any one in the phosphonium ion.
Said metal is cobalt, nickel, molybdenum, titanium, copper or niobium.The thickness of said linkage interface layer 150 is less than 100 dusts, is about 10 to 50 dusts preferably.
The pressure of splash-proofing sputtering metal is 0.5 to 1.5 millitorr (1T=133Pa) under plasma environment.In the process of sputter, form the thin layer of metal and metal reaction alloy, described metal reaction alloy refers to contain the metal of said dopant ion.Through pressure is controlled, when forming thin layer, also remove the partial reaction alloy, the dynamic equilibrium that reaches deposition and remove makes the thickness of thin layer reach desired value, realizes lower contact resistance.The characteristic contact resistance of the linkage interface layer that the present invention forms is that 3E-8 is to 2E-9 Ω/cm
2
Shown in accompanying drawing 4E, remove etching barrier layer 160, form the structure of the semiconductor device of the present invention's formation.The semiconductor device that adopts the present invention to form can be transistors such as memory, logical device.
Because the linkage interface layer of the semiconductor device that the present invention forms contains the doped interface that continuous electronic state is provided, and under very low electric field action, can accomplish electric transmission, has reduced be connected contact resistance metal between of semiconductor with contact hole.This device only needs doped interface layer as thin as a wafer to be connected with metal; Can dwindle the size of semiconductor device further, increase the density of semiconductor device.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (7)
1. the manufacture method of a semiconductor device is characterized in that, comprises the steps:
Semiconductor substrate is provided, is formed with gate dielectric and the source electrode and the drain electrode that are positioned at the grid on the gate dielectric and are positioned at the Semiconductor substrate of gate dielectric both sides on the Semiconductor substrate, said gate lateral wall does not have side wall;
On said Semiconductor substrate, form mask, the Semiconductor substrate outside leak in the sidewall of cover gate and gate dielectric and source;
With the mask layer is mask; Splash-proofing sputtering metal forms along the linkage interface layer of source electrode and drain surface extension and the linkage interface layer that extends along gate surface under plasma environment; Said plasma comprises any one in argon ion and oxonium ion, nitrogen ion, hydrogen ion, borane ion, arsenic hydride ion or the hydrogen phosphide ion; Said metal is cobalt, nickel, molybdenum, titanium, copper or niobium; Said linkage interface layer is the alloy of metal reaction alloy or metal silicide, and said alloy is any one in oxygen, nitrogen, the hydrogen;
Remove said mask.
2. according to the manufacture method of the said semiconductor device of claim 1, it is characterized in that said plasma comprises argon ion and oxonium ion.
3. the manufacture method of semiconductor device according to claim 1; It is characterized in that the reaction alloy of the reaction alloy that said metal reaction alloy is a cobalt, the reaction alloy of nickel, molybdenum, the reaction alloy of titanium, the reaction alloy of copper or the reaction alloy of niobium.
4. the manufacture method of semiconductor device according to claim 1; It is characterized in that the metal silicide of the metal silicide that said linkage interface layer is a cobalt, the metal silicide of nickel, molybdenum, the metal silicide of titanium, the metal silicide of copper or the metal silicide of niobium.
5. the manufacture method of semiconductor device according to claim 1 is characterized in that, the thickness of said linkage interface layer greater than 0 smaller or equal to 100 dusts.
6. the manufacture method of semiconductor device according to claim 5 is characterized in that, the thickness of said linkage interface layer is 10 to 50 dusts.
7. according to the manufacture method of the said semiconductor device of claim 1, it is characterized in that the pressure of splash-proofing sputtering metal is 0.5 to 1.5 millitorr under plasma environment.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9276011B2 (en) | 2013-03-15 | 2016-03-01 | Micron Technology, Inc. | Cell pillar structures and integrated flows |
| US9431410B2 (en) | 2013-11-01 | 2016-08-30 | Micron Technology, Inc. | Methods and apparatuses having memory cells including a monolithic semiconductor channel |
| US9437604B2 (en) | 2013-11-01 | 2016-09-06 | Micron Technology, Inc. | Methods and apparatuses having strings of memory cells including a metal source |
| CN104752334B (en) * | 2013-12-31 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of contact plunger |
| US9515158B1 (en) * | 2015-10-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with insertion layer and method for manufacturing the same |
| CN110148564A (en) * | 2019-06-05 | 2019-08-20 | 长江存储科技有限责任公司 | A kind of DDD UHV MOS device structure and its manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1249065A (en) * | 1997-03-14 | 2000-03-29 | 株式会社日立制作所 | Process for producing semiconductor IC device |
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| CN1249065A (en) * | 1997-03-14 | 2000-03-29 | 株式会社日立制作所 | Process for producing semiconductor IC device |
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