CN101211919A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN101211919A
CN101211919A CNA2007101948923A CN200710194892A CN101211919A CN 101211919 A CN101211919 A CN 101211919A CN A2007101948923 A CNA2007101948923 A CN A2007101948923A CN 200710194892 A CN200710194892 A CN 200710194892A CN 101211919 A CN101211919 A CN 101211919A
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金成珍
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DB HiTek Co Ltd
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Abstract

本发明公开了一种具有在栅极侧壁处形成的间隔垫图案的半导体器件及其制备方法。半导体器件包括在半导体衬底上形成的包括多个栅极的栅极图案、在包括栅极图案的衬底的整个表面上形成的阻挡绝缘层和在由阻挡绝缘层包围的各自栅极的相对侧壁区域处形成的间隔垫图案，使得间隔垫图案具有小于各自栅极的高度。

Description

半导体器件
本申请要求享有在2006年12月29日提交的韩国专利申请No.10-2006-0137352的权益，在这里将其全部作为参考。
技术领域
本发明涉及一种半导体器件及其制备方法，尤其涉及一种具有在栅极侧壁处形成的间隔垫图案的半导体器件及其制备方法。
背景技术
随着半导体器件已经更加高度集成，图案之间的间隔可变得更窄。因此，以用于层间绝缘的层间绝缘层填充间隔可能变得更加困难。
在其中可以最小线宽和间距形成半导体器件的半导体器件单元阵列中，用于器件隔离层的沟槽区域的线宽和字线之间的距离可变得迅速降低。由于在字线侧壁处形成的间隔垫图案，字线之间的距离可能显著降低到不能容易地实现间隙填充的程度。
当填充沟槽区域或字线之间的间隙时，间隙填充可能显著受到间隙的宽度和深宽比的影响。当深宽比为4∶1或更大且间隙宽度为100nm或更小时，可能不能完全填充间隙，并且可产生孔隙。
在闪存器件中，由于其结构特征，字线可具有大的垂直尺寸，其结果是字线之间间隙的深宽比可比其它器件大。而且，由于字线具有字线上部宽度大于字线下部宽度的轮廓，字线之间的间隙在临近衬底的区域处可能是狭窄的，由此不能完全间隙填充层间绝缘层，并且因此，可产生孔隙。
图1和2是示出制备现有技术半导体器件的方法的剖视图。
参考图1，包括多个栅极的栅极图案12可在半导体衬底10上形成。可彼此一致的第一绝缘层24和第二绝缘层26可在其上可形成栅极图案12的衬底上形成。
第一绝缘层24可能由氧化物和正硅酸乙酯(TEOS)构成，其可通过栅极图案12侧壁的氧化获得，而第二绝缘层26可能由硅氮化物构成。
参考图2，为了在栅极图案12侧壁处形成间隔垫图案26s，可各向异性地蚀刻第二绝缘层26。可通过在具有高选择性的蚀刻条件中蚀刻第二绝缘层26，同时使用第一绝缘层24作为蚀刻防止层，形成间隔垫图案26s。
当可将在栅极图案12处的栅极的线宽和栅极之间的距离降低到90nm或更小时，可在具有300nm或更大高度的栅极之间形成具有高深宽比的间隙。尤其，在临近栅极之间的衬底的区域，由于间隔垫图案26s的结构特征，可使栅极宽度显著降低。
因此，如果形成层间绝缘层28，可能不能以层间绝缘层28完全填充由在栅极图案12的相对栅极处的间隔垫图案26s之间确定的间隙，其结果是可能产生孔隙30。
如果在半导体衬底上将栅极图案12的栅极排成一行，以便电极彼此平行，则可能在栅极之间产生孔隙，同时孔隙可能与栅极平行。因此，如果在各自栅极之间形成通过层间绝缘层28连接到半导体衬底的接触图案，则导电膜可渗入到孔隙30中。因此，可能在接触图案处发生短路。
发明内容
实施例涉及一种半导体器件及其制备方法，尤其涉及一种具有在栅极侧壁处形成的间隔垫图案的半导体器件及其制备方法。
实施例可涉及一种在构成栅极图案的栅极之间的层间绝缘层中基本上没有孔隙产生的半导体器件及其制备方法。
实施例涉及一种具有在构成栅极图案的栅极侧壁处在可能填充层间绝缘层的间隙区域中形成的小深宽比的间隔垫图案的半导体器件及其制备方法。
根据实施例，半导体器件可包括在半导体衬底上形成的包括多个栅极的栅极图案、在包括栅极图案的衬底的表面，例如整个表面上形成的阻挡绝缘层、和在由阻挡绝缘层包围的各自栅极的相对侧壁区域处形成的间隔垫图案，使得间隔垫图案具有小于各自栅极的高度。
根据实施例，制备半导体器件的方法可包括：在半导体衬底上形成包括多个栅极的栅极图案；在包括栅极图案的衬底的表面，例如整个表面上形成阻挡绝缘层；在可形成阻挡绝缘层的衬底表面，例如整个表面上形成间隔垫绝缘层；以及在各自栅极的相对侧壁区域处形成间隔垫图案，使得间隔垫图案具有小于各自栅极的高度。
根据实施例，形成间隔垫图案可包括：在间隔垫绝缘层上形成掩模图案，使得掩模图案以预定宽度从各自栅极侧壁处的阻挡绝缘层延伸，以及使用掩模图案作为蚀刻掩模各向异性地蚀刻间隔垫绝缘层。
附图说明
图1和图2是示出制备现有技术半导体器件的方法的截面工艺过程图；
图3是示出根据实施例的半导体器件的截面视图；
图4到图6是示出根据实施例的制备半导体器件的方法的截面工艺过程图。
具体实施方式
参考图3，包括多个栅极62的栅极图案可在半导体衬底50上形成。根据实施例，可能将栅极62可以其中栅极62可彼此平行的结构或以复杂的平面结构而设置在半导体衬底50上。
根据实施例，在存储器件单元阵列中，栅极62可以最小线宽且以最小间距布置。实施例可涉及闪存器件，其可能是非易失性存储器件。根据实施例，每个栅极62可包括隧道绝缘层52、浮栅54、栅极间介电层56和控制栅极58，可将它们从底部到顶部相继地堆叠。每个栅极62可进一步包括在栅极62的最上层，即在控制栅极58上形成的顶盖绝缘层60。
可提供顶盖绝缘层60，以当可能形成反射防止层和接触插栓时防止在栅极和反射防止层及其次的接触插栓之间发生短路。
根据实施例，可在包括栅极图案的衬底表面，例如整个表面上形成阻挡绝缘层64。为此，可由相应的阻挡绝缘层64覆盖每个栅极62的侧壁和顶部。随后，间隔垫图案66s可在由相应阻挡绝缘层64包围的每个栅极62的侧壁区域处形成。
在形成间隔垫图案66s期间，阻挡绝缘层64作为蚀刻防止层。如果间隔垫图案66s由硅氮化物构成，则阻挡绝缘层64可能还用于将栅极62与硅氮化物的应力隔离。这可能防止捕获和缺陷的发生。
间隔垫图案66s可在相应的栅极62的下端处形成，使得间隔垫图案66s的高度可小于相应的栅极62的高度。因此，由于可能没有形成间隔垫图案66s的残余区域，可能降低总深宽比。根据实施例，间隔垫图案66s可在相应的栅极的侧壁处形成的阻挡绝缘层64上形成；然而，可形成间隔垫图案66s的区域在顶盖绝缘层60下面。
层间绝缘层68可在形成间隔垫图案66s的衬底表面，例如整个表面上形成。
间隙填充易于在层间绝缘层68上实现，尤其是在可能没有形成间隔垫图案66s的栅极62的上部之间。而且，虽然栅极62之间的宽度可能较小，但是由于降低了深宽比，所以间隙填充在可形成间隔垫图案66s的栅极62下部之间也易于实现。
图4到图6是示出根据实施例的制备半导体器件的方法的截面工艺过程图。特别地，实施例可能涉及闪存器件，但实施例不限于闪存器件。
参考图4，包括多个栅极62的栅极图案可在半导体衬底50上形成。
根据实施例，每个栅极62可包括浮栅54、栅极间介电层56、控制栅极58、以及顶盖绝缘层60，其可顺序堆叠在可能为栅极62的最下层的隧道绝缘层52上。
虽然未示出，可将掺杂剂注入到半导体衬底50中以形成阱区，并且随后可形成器件绝缘层以在半导体衬底上限定多个平行有源区域。
根据实施例，可将栅极62布置成跨越有源区和器件绝缘层顶部。根据实施例，可将栅极62布置在单元阵列上，使得栅极62可彼此平行。
可形成阻挡绝缘层64以覆盖栅极62的侧壁和顶部。
阻挡绝缘层64可包括TEOS。TEOS可通过化学气相沉积与在氧化工艺中在每个栅极62侧壁处形成的热氧化物一起沉积，用于修复在栅极62形成期间的蚀刻损伤。
间隔垫绝缘层66可在形成阻挡绝缘层64的衬底表面，例如整个表面上形成。根据实施例，可以间隔垫绝缘层66填充栅极62之间所限定的间隙。
可去除位于栅极62之间中部的部分间隔垫绝缘层66。根据实施例，虽然可在间隔垫绝缘层66形成期间产生孔隙，但是孔隙可在后面被去除。
根据实施例，间隔垫绝缘层66可由具有关于阻挡绝缘层64的蚀刻选择性的材料构成。就是说，间隔垫绝缘层66可由与阻挡绝缘层64不同的材料构成。由于阻挡绝缘层64可由氧化物构成，因此，间隔垫绝缘层66可由氮化物构成。
参考图5，可在间隔垫绝缘层66上形成掩模图案70。可使用掩模图案70作为蚀刻掩模而蚀刻间隔垫绝缘层66。掩模图案70可由光致抗蚀剂构成。
根据实施例，掩模图案70可布置在各自栅极62的顶部并延伸到各自栅极62的相对侧，使得掩模图案70可在间隔垫绝缘层66上形成，同时掩模图案70具有大于栅极62的宽度。
根据实施例，掩模图案70可延伸到包括栅极62和阻挡绝缘层64的栅极62相对侧壁。就是说，可形成掩模图案70，使得掩模图案70具有比在阻挡绝缘层64处的每个栅极62侧壁处形成的部分大的宽度。通过使用掩模图案70的蚀刻工艺，可蚀刻间隔垫绝缘层66，使得间隔垫绝缘层66的宽度在横向方向中比在阻挡绝缘层64处的每个栅极62侧壁处形成的部分大的预定宽度。
根据实施例，可使用掩模图案70作为蚀刻掩模而实施各向异性蚀刻工艺。通过各向异性蚀刻工艺，可留下间隔垫绝缘层66的一部分66a，其在横向方向具有距离阻挡绝缘层64的预定宽度，同时可去除包括在栅极62之间的区域的间隔垫绝缘层66的残余区域。
参考图6，可去除掩模图案70以暴露间隔垫绝缘层66a的顶部。
可以足够覆盖栅极图案顶部的大厚度形成间隔垫绝缘层66a。根据实施例，另一方面，可以较小的厚度形成在栅极62之间的间隔垫绝缘层66a的部分以降低深宽比。
为了去除覆盖栅极图案顶部的间隔垫绝缘层66a，可回蚀可能从其去除掩模图案70的间隔垫绝缘层66a。在去除工艺中，还可回蚀在各自栅极62侧壁处形成的间隔垫绝缘层。为此，可在形成于栅极62下端处的阻挡绝缘层64处形成间隔垫图案66s。
根据实施例，可在临近栅极62下端的位置形成间隔垫图案66s。因此，可降低栅极62之间所限定的间隙区域的深宽比。
根据实施例，间隔垫图案66s覆盖在控制栅极侧壁处形成的阻挡绝缘层64，以执行其自身功能。
根据实施例，可在形成间隔垫图案66s的衬底表面，例如整个表面上形成层间绝缘层68(见图3)。
可扩大在栅极62之间的间隙区域的上部，并且可降低在栅极之间的间隙区域下部的深宽比。为此，可在栅极之间稳定地填充层间绝缘层68，而不产生如图2所示的孔隙。
根据实施例，可在构成栅极图案的栅极之间在具有较小宽度的间隙区域处仅部分地形成间隔垫图案。因此，与现有技术相比，可增加间隙的宽度，并且深宽比在间隙宽度可能没有增加的区域处可能减小，这可易于实现间隙填充。
根据实施例，在间隔垫图案形成之前，可最大程度地减小残余在各自栅极侧壁处的间隔垫绝缘层的宽度，从而进一步增加间隙的宽度。
为此，可防止在栅极之间产生孔隙，并且由此，在接触图案形成期间可防止导电层通过孔隙短路，这可防止器件缺陷和可靠性降低。
对于本领域的普通技术人员，显而易见的是可以对实施例作出各种修改和改变。因此，实施例意欲覆盖在附属权利要求范围内的修改和改变。还应该理解的是，当将层称为在另一层或衬底“上”或“之上”时，其可以直接在该另一层或衬底上，或者可能存在中间层。

Claims (18)

1.一种器件，包括：
在半导体衬底之上形成的包括多个栅极的栅极图案；
在包括所述栅极图案的所述衬底表面之上形成的阻挡绝缘层；以及
在各自栅极的相对侧壁区域处形成且由所述阻挡绝缘层围绕的间隔垫图案，其中该间隔垫图案具有比各自栅极小的高度。
2.如权利要求1所述的器件，其特征在于，所述间隔垫图案包括具有关于所述阻挡绝缘层的蚀刻选择性的材料。
3.如权利要求2所述的器件，其特征在于，所述阻挡绝缘层包括氧化物，且所述间隔垫图案包括氮化物。
4.如权利要求1所述的器件，其特征在于，每个栅极包括隧道绝缘层、浮栅、栅极间介电层、控制栅极和顶盖绝缘层。
5.如权利要求4所述的器件，其特征在于，所述隧道绝缘层、浮栅、栅极间介电层、控制栅极和顶盖绝缘层从底部到顶部相继堆叠。
6.如权利要求5所述的器件，其特征在于，所述间隔垫图案在相应的顶盖绝缘层下面的区域处形成。
7.如权利要求6所述的器件，其特征在于，所述间隔垫图案在所述顶盖绝缘层下面的所述栅极侧壁处形成的所述阻挡绝缘层处形成。
8.一种方法，包括：
在半导体衬底之上形成包括多个栅极的栅极图案；
在包括所述栅极图案的衬底的表面之上形成阻挡绝缘层；
在形成所述阻挡绝缘层的衬底表面之上形成间隔垫绝缘层；以及
在各自栅极的相对侧壁区域处形成间隔垫图案，使得所述间隔垫图案具有小于各自栅极的高度。
9.如权利要求8所述的方法，其特征在于，形成所述间隔垫图案包括：
在所述间隔垫绝缘层上形成掩模图案，使得所述掩模图案以预定宽度从各自栅极侧壁处的阻挡绝缘层延伸；以及
使用掩模图案作为蚀刻掩模各向异性地蚀刻所述间隔垫绝缘层。
10.如权利要求8所述的方法，其特征在于，以所述间隔垫绝缘层填充在所述栅极图案的各自栅极之间所限定的间隙。
11.如权利要求8所述的方法，其特征在于，所述间隔垫绝缘层包括具有关于所述阻挡绝缘层的蚀刻选择性的材料。
12.如权利要求8所述的方法，其特征在于，所述栅极图案的每个栅极通过堆叠隧道绝缘层、浮栅、栅极间介电层、控制栅极和顶盖绝缘层而形成。
13.如权利要求12所述的方法，其特征在于，所述隧道绝缘层、浮栅、栅极间介电层、控制栅极和顶盖绝缘层从底部到顶部相继堆叠。
14.一种器件，包括：
在半导体衬底之上的多个栅极，每个栅极包括隧道绝缘层、浮栅、栅极间介电层、控制栅极和顶盖绝缘层；
在包括所述栅极图案的所述衬底表面之上形成的阻挡绝缘层；以及
在各自栅极的相对侧壁区域处形成且由所述阻挡绝缘层围绕的间隔垫图案。
15.如权利要求14所述的器件，其特征在于，所述间隔垫图案具有小于各自栅极的高度。
16.如权利要求15所述的器件，其特征在于，所述隧道绝缘层、浮栅、栅极间介电层、控制栅极和顶盖绝缘层从底部到顶部相继堆叠。
17.如权利要求16所述的器件，其特征在于，所述间隔垫图案在相应的顶盖绝缘层下面的区域处形成。
18.如权利要求17所述的器件，其特征在于，所述间隔垫图案在所述顶盖绝缘层下面的栅极侧壁处形成的所述阻挡绝缘层处形成。
CNA2007101948923A 2006-12-29 2007-12-27 半导体器件 Pending CN101211919A (zh)

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