CN101211794A - Method for manufacturing a leadframe, packaging method for semiconductor element and semiconductor package product - Google Patents

Method for manufacturing a leadframe, packaging method for semiconductor element and semiconductor package product Download PDF

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Publication number
CN101211794A
CN101211794A CNA2007103011633A CN200710301163A CN101211794A CN 101211794 A CN101211794 A CN 101211794A CN A2007103011633 A CNA2007103011633 A CN A2007103011633A CN 200710301163 A CN200710301163 A CN 200710301163A CN 101211794 A CN101211794 A CN 101211794A
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CN
China
Prior art keywords
semiconductor element
less important
chip base
partitioned portion
important part
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Pending
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CNA2007103011633A
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Chinese (zh)
Inventor
陈南璋
林泓均
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MediaTek Inc
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MediaTek Inc
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Publication of CN101211794A publication Critical patent/CN101211794A/en
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Description

Packaging method for semiconductor element, making lead frame method and semiconductor package product
Technical field
The present invention is relevant for a kind of lead frame structure that is used for semiconductor element, particularly has multiple exposed lead-frame packages member and a method for making thereof of putting crystal cup (exposed die pad) relevant for a kind of.
Background technology
Known to the related personnel of this area, for fear of the interference and the destruction of external environment factor, semiconductor wafer normally is overmolding to a packing component with plastic material.Packing component also provides the circuit between semiconductor wafer and the printed circuit board (PCB) to link.Such integrated circuit packing component generally includes a metal lead wire frame, and is arranged on and the integrated semiconductor wafer of putting on the crystal cup of metal lead wire frame, and the gold thread of the joint sheet on the electrical ties semiconductor wafer and each lead foot of lead frame.Semiconductor wafer and lead frame finally can be enveloped by the mould closure material.
Present encapsulation industry trend is to make the volume of packing component littler but have greater functionality.Because the function of integrated circuit (IC) wafer becomes increasingly complex, and makes the external pins number of lead-frame packages member also increase many.The pin count increase raises the packaging cost of each wafer.Increase for fear of pin count causes the packing component volume to become big, and the practice in past is to reduce the lead foot spacing.Yet too near but being easy to generate mutual inductance (mutual inductance) and mutual capacitance (mutual capacitance), this also is the reason that lead-frame packages often is considered to be not suitable for being applied in the high-speed semiconductor wafer to lead foot each other.Aforesaid mutual inductance and mutual capacitance interfere with the high speed signal that the high-speed semiconductor wafer is transmitted possibly.
Consider such unfavorable factor, many mobile communication devices, as the circuit of taking action, but and to be equipped with the semiconductor wafer in the personal communication device of transmitting high-frequency signal all be to adopt ball-type grid matrix (ball grid array) encapsulation, and do not adopt the lead-frame packages mode.If actually with such high-speed semiconductor wafer with lead-frame packages, the then loss of signal or will obviously have influence on wafer as AC noise etc. and operate usefulness, and become irritating problem.
The shortcoming of aforementioned ball-type grid array package is that its cost is higher and the product friendship phase is longer.In addition, one of challenge of development radio system single-chip is to be difficult to reduce the power consumption of radio frequency and analog circuit and to dwindle passive component and the size of analog electrical crystal.Hence one can see that, this technical field still needs a kind of lead frame structure and lead-frame packages structure of improvement, it has cheaply advantage and needs and can be applied on the high-speed semiconductor wafer, does not have the tangible loss of signal or noise when transmitting high-frequency signal.
Summary of the invention
Main purpose of the present invention is providing a kind of multiple exposed lead-frame packages member and method for making thereof of putting crystal cup that have, to solve the problem of known technology.
The present invention's first specific embodiment is a kind of packaging method for semiconductor element, comprise: semiconductor element is placed on the major part of chip base of lead frame, this chip base has more than one less important part and more than one partitioned portion in addition, and this less important part sees through this partitioned portion with this major part and is connected; One group of holding wire of semiconductor element is connected respectively to a plurality of lead foots of this lead frame; This semiconductor element and this lead frame are carried out the mould packing, and wherein expose to the open air outside the mould packing bottom surface of this chip base; And this partitioned portion is carried out release etch from the bottom surface of chip base, the less important part of this major part and this is electrically separated.
The present invention's second specific embodiment is a kind of method of making lead frame, and this lead frame is used for packaging semiconductor, and this method comprises: make the main pattern of a lead frame on sheet metal; According to the preliminary lead frame of the main design producing of this lead frame; With the chip base zone definitions major part of shade on preliminary lead frame, at least one less important part, and at least one partitioned portion; And this partitioned portion carried out step etching just, be the thin thickness of the thickness of this partitioned portion than this major part and this less important part.
The present invention's the 3rd specific embodiment is a semiconductor package product, and this semiconductor package product comprises: semiconductor element; The chip base has major part and more than one less important part, major part bearing semiconductor element; A plurality of lead foots, a plurality of holding wires of electrical connection semiconductor element; And Encapsulation Moulds, cover the lead foot of semiconductor element, chip base and part, and the bottom surface of exposing the less important part of this chip base to the open air, wherein, this semiconductor element has the plural signal of telecommunication to be connected to less important part, and see through the bottom surface that this less important part exposes to the open air, these signals of telecommunication are connected to the signal of telecommunication contact of circuit board.
See through the special leadframe design of the present invention, utilize the method for packing of new wiring foot design, make the product of encapsulation because save lead foot, shorten signal path etc., and produce better characteristic electron, littler encapsulation volume or hold more signal contact at same encapsulation volume.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, better embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.Yet following better embodiment and graphic only for reference and explanation usefulness are not to be used for to the present invention's limitr in addition.
Description of drawings
The top schematic diagram of a lead-frame packages 10 of Fig. 1 illustration.
Fig. 2 is the top schematic diagram according to the lead-frame packages of the embodiment of the invention.
The side-looking generalized section of Fig. 3 illustration lead-frame packages.
Fig. 4 is separating pad district 14b and generalized section around the hole 40b of separating pad district 14b.
Distortion in the design of Fig. 5 illustration hole.
Fig. 6 is the distortion of the another kind of hole of illustration then.
Fig. 7 illustration according to chip base of the present invention with as the inductor section of example.
Fig. 8 illustration is made the flow chart that has the lead-frame packages that exposes the pad district to the open air according to of the present invention more.
Fig. 9 is for using the generalized section of two-stage etching package lead framework process of the present invention.
Figure 10 is for using the generalized section of two-stage etching package lead framework process of the present invention.
Figure 11 is for using the generalized section of two-stage etching package lead framework process of the present invention.
Figure 12 is for using the generalized section of two-stage etching package lead framework process of the present invention.
Figure 13 is for using the generalized section of two-stage etching package lead framework process of the present invention.
Figure 14 illustration has the assembling schematic diagram of lead-frame packages of the inverted T-shaped perforate of the 4th figure.
Figure 15 illustration has the assembling schematic diagram of lead-frame packages of the inverted T-shaped perforate of the 4th figure.
Figure 16 illustration has the assembling schematic diagram of lead-frame packages of the inverted T-shaped perforate of the 4th figure.
Figure 17 illustration has the assembling schematic diagram of lead-frame packages of the inverted T-shaped perforate of the 4th figure.
The top schematic diagram of Figure 18 illustration SiP lead-frame packages.
Figure 19 illustrates that the present invention is used in and dubs wafer (flip-chip) encapsulating lead encapsulation.
Figure 20 illustrates that the present invention is used in and dubs wafer (flip-chip) encapsulating lead encapsulation.
Embodiment
Below illustrated lead frame (leadframe) encapsulation (packaging) structure, can be used for but be not limited to not conspicuous Siping City packing (Low-Profile Quad Flat Pack, LQFP) encapsulation, thin packing (the Thin Quad Flat Pack of Siping City, TQFP) encapsulation, the non-lead foot in Siping City (Quad Flat Non-leaded, QFN) encapsulation, DFN encapsulation, multizone QFN (multi-zone QFN) encapsulation, and multicore sheet (multi-die) encapsulation, and dub wafer package (flip-chip packaging).
With respect to prior art, through saving or discharging originally is ground mat (ground pad), power source pad (power pad) or the lead foot (lead) of the signal pad of other classes that is used for connecting semiconductor chip, and the present invention can further promote the limit of lead frame structure encapsulation.In addition, see through the separation grounding system of using on the chip base (die pad), the present invention also can be used to improve the electrical performance of integrated circuit (integrated circuit) encapsulating products.
The top schematic diagram of a lead-frame packages 10 of Fig. 1 illustration.Shown in the 1st figure, lead-frame packages 10 comprises as the semiconductor chip (semiconductor die) 12 of semiconductor element (semiconductor device) example, is installed on the chip base (die pad) 14.A plurality of welded gaskets (bondingpad) 13 are placed in the upper surface of semiconductor chip 12.Each welded gasket 13 sees through sealing wire 18 and is electrically connected the lead foot (lead) 13 of leading correspondence.
The welded gasket 13 that is commonly referred to as output input pad (input/output pad) generally can comprise power source pad (power pad) 13a～13f, ground mat (ground pad) 13g and 13f, and other signal pad.The sealing wire (bond wire) 18 that power source pad 13a～13f sees through as holding wire is welded to corresponding lead foot 16a～ 16f.Ground mat 13g and 13h see through sealing wire 26 and are welded to chip base 26.
Can be installed to the lead foot 16 of the socket (socket) of printed circuit board (PCB) (Printed Circuit Board) at last, settle along four limits of chip 14.The inboard of semiconductor chip 12, chip base 14, lead foot 16 and sealing wire 18 see through mould packaging material (molding compound) 20 and get up to envelope.
In this example, chip base 14 is plane domains of single a, rectangle, has four elongated support bars that extend outward from the chip base (supporting bar) 15.But, note that the chip base of other shapes, for example there is not the chip base of four elongated support bars, also can use the notion of introducing of the present invention in fact.The bottom surface of chip base 14 painstakingly exposes package main body (package body), and with the heat that bulk storage semiconductor chip 12 is produced, this is called and exposes formula chip base (be called for short e-pad) design to the open air.In general, the chip 14 bottom surface point that exposes to the open air out connects the ground plane of leading printed circuit board (PCB).
Yet, to use for some single-chips (SoC) that can transmitting high-frequency signal have the analog/digital hybrid circuit, such design may allow the ground connection noise of digital circuit have influence on the signalling channel of analog circuit.
Please refer to Fig. 2 and Fig. 3.Fig. 2 is the top schematic diagram according to the lead-frame packages 10a of the embodiment of the invention.The side-looking generalized section of Fig. 3 illustration lead-frame packages 10a, wherein components identical symbology components identical, zone or layer.
As Fig. 2 and shown in Figure 3, lead-frame packages 10a comprises semiconductor chip 12, and it is placed on the chip base of copper or copper alloys such as C725, A192.A plurality of welded gaskets are placed in the surface, top of semiconductor chip 12.Some welded gasket 13 sees through sealing wire 18 and is connected to corresponding lead foot 16.
Welded gasket 13 comprises power source pad 13a～13f, digital grounding pad 13g～13h, analogue ground pad 13i～13j, and other signal pad.One of them feature of the present invention is exactly that a separating pad district (separate pad segment) 14 is received in the short sealing wire weldering 28 of power source pad 13a～13f tranmittance, rather than receives lead foot 16a～16f.Therefore, originally need to keep the lead foot 16a～16f that is used for connecting power source pad 13a～13f and just can save and be used in other place, for example, be used for connecting other signal pads of semiconductor chip 12, or simply these lead foots are omitted, to reduce size and the cost of lead-frame packages 10a.
From an angle, the usefulness of lead-frame packages 10 is presented on to see through saves the lead foot 16a～16f that originally will be used for connecting power source pad 13a～13f.This is owing to using lead foot number (lead pitch) to increase, also because the signal path attenuating of chip between printed circuit board (PCB).
From another angle, inventive features of the present invention comprises that the separating pad 14a by chip base 14 is separated does not directly touch in the chip mat seated connection, but complete and chip base maintenance separation relation.In addition, separating pad district 14a can directly not contact with any lead foot 16 yet, or is supported by any lead foot 16.Therefore, separating pad district 14 can not take any lead foot 16.Similar to chip base 14, also expose to the open air outside the encapsulation theme bottom surface of separating pad district 14a, makes separating pad district 14a can be directly contact with bus plane on the printed circuit board (PCB), and power supply signal is passed to semiconductor chip 12.
Another feature of the present invention is the digital grounding pad 13g～13h of semiconductor chip 12, see through sealing wire 26 and receive chip base 14, and the analogue ground 13i of semiconductor chip 12 is welded to another separating pad district 14b with 13j through sealing wire 36.
According to the present invention, chip base 14 is connected to the digital grounding signal, and separating pad district 14b then is connected to the analogue ground signal.This separation grounding system on the chip base has been avoided the noise interference simulation signal path of digital circuit.In addition, analogue ground pad 13i and 13j ground connection, and see through sealing wire and be welded to separating pad district 14b, expression is with respect to than seeing through the shorter signal transmission path of lead foot 16.
Similar, separating pad district 14b separates from chip base 14, does not directly contact with chip base 14, and is actually and chip base 14 maintenance released states.
As shown in Figure 3, similar to separating pad district 14a, separating pad district 14b does not directly contact with any lead foot 16.Furthermore, separating pad district 14b need be from the lead foot 16 or the structure upper support of chip base 14.At the hole 40a of 14 of separating pad district 14a and chip bases, and filled with mould packaging material 20 such as epoxy resin at the hole 40b of 14 of separating pad district 14b and chip bases.
Please note on chip base 14, three kinds of different parts are arranged, major part (primaryportion) just, at least one less important part (secondary portion), and at least one partitioned portion (separating portion), wherein partitioned portion is used for separating major part and less important part.In Fig. 2, it is the example of two less important parts that separating pad district 14a and 14b can be considered.As the hole 40a and the 40b of partitioned portion example, then be used for separating pad district 14a and 14b with less important part, separate with the major part on the chip base.
Expose to the open air outside package main body the bottom surface of spacing pad district 14b, makes separating pad district 14b to be connected with analogue ground (AGND) floor on the printed circuit board (PCB).The bottom surface of exposing to the open air of chip base 14 then is connected with digital grounding (DGND) layer.As previously mentioned, the separation grounding system on this chip base avoids the noise of digital circuit to interfere with analog signal path.
Fig. 4 is separating pad district 14b and generalized section around the hole 40b of separating pad district 14b.As shown in Figure 4, a layer of precious metal 52a, for example gold, silver, nickel gold or its combination is placed in the mould top (chip side) of chip base 14 and separating pad district 14b.Chip base 14 and separating pad district 14b expose bottom surface side (printed circuit board (PCB) side) to the open air, then all block up last layer noble metal 52b.Passive component 60 can be placed in 14 in chip base 14 and separating pad district, stride across hole 40b,, prevent static (ESD to connect (decoupling) as removing, Electrostatic Discharge) or other specific circuit design, for example filter or adaptation purposes such as (matching).
Another characteristics of the present invention are that the subregion of hole 40b (or hole 40a) can also be designed to have the structure in inverted T-shaped shape cross section.Epoxy resin mould packaging material 20 are inserted the hole in inverted T-shaped shape cross section, can further increase the stability of encapsulation, and avoid the distortion of lead frame main body.Because the design of the hole 40b of inverted T-shaped shape, the mould packaging material of injecting 20 can clench separating pad district 40b, allow it remain on the fixed position.
Distortion in the another kind design of the another kind of hole 40b of Fig. 5 illustration (or 40a).As shown in Figure 5, the hole 40b of hourglass shape is above mould or say that chip side has scalariform top part.Fig. 6 is the distortion of the another kind of hole 40b of illustration (or 40a) then.As shown in Figure 6, separating pad district 14b has the edge 70 of zigzag fashion.Such design can increase separating pad district 14b and insert adhesive force between mould packaging material among the hole 40b.
Fig. 7 illustration is according to chip base of the present invention 14 and inductor section 82 and 84 as example.Forniciform inductor section 82 and spiral helicine inductor section 84 can be used as the inductance on the base, make together in the time of can being incorporated into the chip base 14 that forms lead frame.Crooked inductor section 82 does not directly contact with chip base 14 with spiral inductance district 84.Furthermore, inductor section 82 and 84 and without any need for from the lead foot 16 or the support of chip base 14.
The epoxy resin mould packaging material are inserted the hole 82a that is positioned at 14 of crooked inductor section 82 and chip bases, also insert the hole 84a that is positioned at 14 of crooked inductor section 84 and chip bases.Hole 82a and 84a also can have the subregion that the cross section of inverted T-shaped shape shown in Figure 4 is arranged.
Because inductor section 82 directly is not connected with lead foot 16 with 84, inductance has high Q parameter, has reduced parasitic capacitance and has reduced response frequency.
Fig. 8 illustration is made the flow chart that has the lead-frame packages that exposes the pad district to the open air according to of the present invention more.From an angle, lead-frame packages of the present invention can use two-stage etching (etching) method to carry out.That is to say that the chip base at first through etching partially (step shown in the label 102) for the first time, is also referred to as first etching, this step that belongs to the stage 100 can be finished in lead frame manufacturing works.In addition, secondary etching partially (step shown in the label 202) is also referred to as release etch, can be carried out behind the mould packet assembler by follow-up maquila in the stage 200.In Fig. 8, except " back side adds pattern (Back-side Mark) ", " removing back side pattern ", and " mould packing " " etching " after (molding), other step can directly use traditional traditional lead-frame packages method for making to carry out.Because it is also few to need to adjust the method for making that changes, make that this embodiment is able to import existing manufacturing process fast, also be one of advantage of the present invention." adding pattern behind " is before the bottom surface will plate the Sn protective layer, earlier to shade on the partitioned portion that will remove in the future.When plating protective layers such as Sn or other noble metals, just can not be plated in the partitioned portion that next preparation will remove to these noble metals.Then, be to remove these to cover shade on the partitioned portion, and etching is carried out in these zones, remove the thickness of remaining partitioned portion.Secondaryly etch partially the action that separating pad district 14a and 14b are separated from the main region of chip base.
Please refer to Fig. 9 to Figure 13, and refer back to Fig. 8.Fig. 9 is to the generalized section of Figure 13 for use two-stage etching package lead framework process of the present invention.Please note the element here or the thickness of layer for convenience of description, do not use actual scale.As shown in Figure 9, at etching or punching press (stamping) and plated film (plating), can obtain lead frame 300.Lead frame 300 comprises one chip base 314 and peripheral lead foot 316.(coat) all plated on the two sides of chip base 314 etching shade 322, is made of noble metal, metal alloy or photoresistance (photoresist).Etching shade 322 has hole opening 324, and the base sample attitude (pad pattern) 350 that its definition separates is to be converted to the described chip base 314 in back.
As shown in figure 10, when the program that etches partially is for the first time carried out, can see through etching shade 322, see through hole opening etching predetermined thickness in the chip side of chip base.As previously mentioned, the program that etches partially for the first time can be made factory at lead frame and finished.Then, be transported to maquila through the lead frame 300 that etches partially.
As shown in figure 11, at maquila, semiconductor chip 312 is arranged on the chip base 314. Sealing wire 318 and 336 is used to provide welded gasket 313 and lead foot 316, and the electric connection between welded gasket on the semiconductor chip 312 313 and the chip base 314.
As shown in figure 12, behind sealing wire, can use thermoplastic material (thermosetting compound) 320 to be packed as the whole assembling of Figure 11.This material can be hardening at subcritical temerature resin (low-temperature hardening resin).Then, the mould encapsulation can be cured (curing) program.As special appointment, bottom surface side or say that the packaging of printed circuit board (PCB) side then has exposed areas.
As shown in figure 13, after packing, the printed circuit board (PCB) side that the encapsulating products of packing exposes to the open air out is through secondary etching, the thickness of left chip base, the hole opening 324 that sees through etching shade 322 is removed, thereby formed separating pad district 314a, it is separated with chip base 314.Separating pad district 314a separates fully with chip base 314, and with chip base 314 direct the contact is not arranged.
Figure 14 has the assembling schematic diagram of lead-frame packages of the inverted T-shaped perforate of Fig. 4 to Figure 17 illustration.As shown in figure 14, after etching or punching press and electroplating, obtain lead frame 300.Lead frame 300 comprises one chip base 314 and peripheral lead foot 316.Two sides of chip base plate etching shade 322.In the bottom surface of exposing to the open air, etching shade 322 comprises support bar (supporting bar) sample attitude, with temporary transient connection separating pad district 314a and chip base 314.Etching shade 322 can be made of noble metal, metal alloy or photoresistance.Etching shade 322 has hole opening 324, and it has defined separating pad district 350, can be converted into the chip base 314 that describes below afterwards.
Next, in Figure 15, etching for the first time (comprising from etching partially of chip direction and etching partially from chip base bottom surface direction) is carried out at the both direction of chip base, hole opening from etching shade 322, remove the whole thickness of chip base, with formation inverted T-shaped hole cross section, and separating pad district 314a.In this stage, above-mentioned support bar still is connected between separating pad district 314a and the chip base 314, drops from chip base 314 to avoid separating pad district 314.This primary etching can be carried out in lead frame factory.Lead frame then is sent to maquila.
As shown in figure 16, in maquila, semiconductor chip 312 is positioned on the chip base 314. Sealing wire 318 and 336 provides between the welded gasket 313 and lead foot 316 of semiconductor chip, and the welded gasket 313 of semiconductor chip and the electric connection of separating pad district 314a.
As shown in figure 17, behind sealing wire, combination shown in Figure 16 is whole to be wired up by thermoplastic material 320 moulds.This material can be the hardening at subcritical temerature resin.Then, mould encapsulates (curing) program of can hardening.As mentioned above, the bottom surface of mould encapsulation or say that the printed circuit board (PCB) face is exposed to the open air out.
According to another embodiment of the present invention, lead-frame packages be polycrystalline sheet module (MCM, multi-chipmodule) or the encapsulation in system (SiP System-in-Package), has comprised a plurality of semiconductor chips and passive component in single encapsulation.The top schematic diagram of Figure 18 illustration SiP lead-frame packages.In Figure 18, the SiP lead-frame packages comprises first semiconductor chip 412, is placed on the main chip base 414.Main chip base 414 has four elongated support bars 415, stretches out from the four direction of main chip base 414.Expose to the open air outside package main body the bottom surface of chip base 414, sheds with the heat that semiconductor chip 412 is produced.Main chip base 414 expose the ground plane that the bottom surface can be electrically connected to printed circuit board (PCB) to the open air.
There are a plurality of welded gaskets 413 top of first semiconductor chip 412, sees through sealing wire 418 and is electrically connected to corresponding lead foot 416.The lead-frame packages 400 of SiP more comprises the second chip base 514.Second semiconductor chip 512 is placed on the second chip base 514.The second chip base 514 separates with main chip base 414, and does not directly contact with main chip base 414.A part of welded gasket 513 of semiconductor chip 512 sees through sealing wire 518 and is electrically connected to corresponding lead foot 416.In this embodiment, first semiconductor chip 412 is digital wafer, and second semiconductor chip is a simulated wafer.
Similar, expose to the open air outside encapsulation the bottom surface of the second chip base 514, gets rid of with the heat that semiconductor chip 512 is produced.The second chip base 514 can directly be electrically connected with the ground planes such as analogue ground of printed circuit board (PCB), to avoid the noise interference simulation signal path of digital circuit.In addition, separating pad district 614 also can have with Fig. 3 to identical separation pad district 14b shown in Figure 6, design is on main chip base 414.
The function in separating pad district 614 can provide high speed signal to semiconductor chip 512, with the short power path of foundation, and has reached less dropout.Separating pad district 614 can separate with main pad district 414, and without any need for from the main chip base 414 or the support structure of lead foot 416.
The another kind of practice is that passive component is settled on the hole 540 that is connected across between the main chip base 414 and the second chip base 514.Some welded gasket 413 sees through sealing wire 618, is connected to the welded gasket 513 of second semiconductor chip 512.The welded gasket 513 of some second semiconductor chip 512 then sees through sealing wire 718 and is connected to separating pad district 614.Whole assembling wires up with mould packaging material 420.
Figure 19 and Figure 20 illustrate that the present invention is used in and dub wafer (flip-chip) encapsulating lead encapsulation 900.Figure 19 is the top floor map that dubs wafer lead-frame packages 900, and Figure 20 then is the generalized section that dubs wafer lead-frame packages 900.As Figure 19 and shown in Figure 20, dub wafer lead-frame packages 900 and comprise chip base 914, have four elongated support bars 915, extend outward from four corners of main region of chip base 914.The bottom surface of exposing to the open air of chip base 914 then is electrically connected to printed circuit digital grounding (DGND) layer partly.Hop (Bump) or solder sphere (solder ball) then are configured in the opposing party, chip side just, and its side of exposing to the open air with chip base 914 is opposite, in order to the wafer that dubs on electric welding main chip base and the chip base.
Dub wafer lead-frame packages 900 and more comprise a plurality of separating pads district 914a～914d, each is connected to a special signal.For instance, separating pad district 914a is connected to V DD1Power supply signal, separating pad district 914b is connected to V DD2Power supply signal, separating pad district 914c is connected to V DD3Power supply signal, separating pad district 914d then is connected to analogue ground signal (AGND).Hop (Bump) 924a～924d then is placed in separating pad district 914a～914d respectively, the separating pad district is provided and dubs means of spot welds between the wafer 912.
Separating pad district 914a～914d keeps separating with chip base 914, and as previously mentioned, does not directly contact with the chip base.Further, separating pad district 914a～914d also keeps separating with lead foot 916.Hole 940a～940d can have inverted T-shaped cross section shown in Figure 4.The bottom surface of separating pad district 914a～914d then exposes to the open air out.
Lead foot 916 disposes around chip base 914.Hop (Bump) 916a settles the lead foot 916 to correspondence, to carry out lead foot 916 and to dub the electric welding of 912 of wafers.Except the bottom surface, dub wafer 912, chip base 914, separating pad district 914a～914d, and lead foot 916 is packaged in the mold materials 920.Mould packaging material 920 are inserted hole 940a～940d, make the original position of maintenance that separating pad district 914a～914d can be more firm.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims (25)

1. packaging method for semiconductor element, this packaging method for semiconductor element comprises:
Semiconductor element is placed on the major part of chip base of lead frame, this chip base has more than one less important part and more than one partitioned portion in addition, and this less important part sees through this partitioned portion with this major part and is connected;
One group of holding wire of semiconductor element is connected respectively to a plurality of lead foots of this lead frame;
This semiconductor element and this lead frame are carried out the mould packing, and wherein expose to the open air outside the mould packing bottom surface of this chip base; And
From the bottom surface of chip base this partitioned portion is carried out release etch, the less important part of this major part and this is electrically separated.
2. packaging method for semiconductor element as claimed in claim 1, the thickness of this partitioned portion is thin than the thickness of this major part and this less important part.
3. packaging method for semiconductor element as claimed in claim 2, this packaging method for semiconductor element more comprise this chip base are carried out step etching just, so that the thickness of this partitioned portion is thin than the thickness of this major part and this less important part.
4. packaging method for semiconductor element as claimed in claim 3 wherein, etches an inverted T-shaped hole by this regional area that is etched in this partitioned portion for the first time, and the mould packaging material are inserted in this T shape hole when mould is packed, to increase the stability of this chip base.
5. packaging method for semiconductor element as claimed in claim 4, wherein, the exposed surface of this chip base is in this place, T shape hole, attached subsides passive component.
6. packaging method for semiconductor element as claimed in claim 3, wherein, etch a hourglass shape hole by this regional area that is etched in this partitioned portion for the first time, the mould packaging material are inserted in this hourglass shape hole when mould is packed, to increase the stability of this chip base.
7. packaging method for semiconductor element as claimed in claim 1, wherein, a regional area of this partitioned portion presents zigzag, to increase the stability of this chip base.
8. packaging method for semiconductor element as claimed in claim 1, another group holding wire that this packaging method for semiconductor element more comprises this semiconductor element is connected to this less important part, is connected to signal contact on the circuit board to see through zone that this less important part is exposed to this mould packing.
9. packaging method for semiconductor element as claimed in claim 6 wherein, surpasses the plural signal of telecommunication and is connected to same this less important part.
10. packaging method for semiconductor element as claimed in claim 6, wherein, the signal of telecommunication that this less important part is used for being connected is a high-frequency signal.
11. packaging method for semiconductor element as claimed in claim 1, this packaging method for semiconductor element more comprises, and second half conductor element is placed on this less important part.
12. packaging method for semiconductor element as claimed in claim 1, this less important part forms wafer external inductance element.
13. packaging method for semiconductor element as claimed in claim 1 wherein, has two less important parts that two ground contacts are provided.
14. packaging method for semiconductor element as claimed in claim 1, wherein, this packaging method for semiconductor element more comprises the earth point that the analog circuit ground signalling of this semiconductor element and the ground connection of numerical digit is connected to different less important parts.
15. a method of making lead frame, this lead frame is used for packaging semiconductor, and this making lead frame method method comprises:
On sheet metal, make the main pattern of a lead frame;
According to the preliminary lead frame of the main design producing of this lead frame;
With the chip base zone definitions major part of shade on preliminary lead frame, at least one less important part, and at least one partitioned portion; And
This partitioned portion is carried out step etching just, and the thickness that is this partitioned portion is than the thin thickness of this major part with this less important part.
16. the method for making lead frame as claimed in claim 15 wherein, etches an inverted T-shaped hole by this regional area that is etched in this partitioned portion for the first time, the mould packaging material are inserted in this T shape hole when mould is packed, to increase the stability of this chip base.
17. the method for making lead frame as claimed in claim 15, etch a hourglass shape by this regional area that is etched in this partitioned portion for the first time, the mould packaging material are inserted in this hourglass shape zone when mould is packed, to increase the stability of this chip base.
18. the method for making lead frame as claimed in claim 15, wherein, a regional area of this partitioned portion presents zigzag, to increase the stability of this chip base.
19. a semiconductor package product is characterized in that, this semiconductor package product comprises:
Semiconductor element;
The chip base has major part and more than one less important part, major part bearing semiconductor element;
A plurality of lead foots, a plurality of holding wires of electrical connection semiconductor element; And
Encapsulation Moulds, cover the lead foot of semiconductor element, chip base and part, and the bottom surface of exposing the less important part of this chip base to the open air, wherein, this semiconductor element has the plural signal of telecommunication to be connected to less important part, and see through the bottom surface that this less important part exposes to the open air, these signals of telecommunication are connected to the signal of telecommunication contact of circuit board.
20. semiconductor package product as claimed in claim 19 is characterized in that, has two less important parts that two ground contacts are provided.
21. semiconductor package product as claimed in claim 19 is characterized in that, this semiconductor package product more comprises the earth point that the analog circuit ground signalling of this semiconductor element and the ground connection of numerical digit is connected to different less important parts.
22. semiconductor package product as claimed in claim 19 is characterized in that, this less important part provides the high-frequency signal that connects this semiconductor element.
23. semiconductor package product as claimed in claim 19 is characterized in that, the partitioned portion by material between major part and this less important part separates, and this partitioned portion has the inverted T-shaped shape.
24. semiconductor package product as claimed in claim 19 is characterized in that, the partitioned portion by material between major part and this less important part separates, and this partitioned portion has hourglass shape.
25. semiconductor package product as claimed in claim 19 is characterized in that, a regional area of this partitioned portion presents zigzag, to increase the stability of this chip base.
CNA2007103011633A 2006-12-27 2007-12-26 Method for manufacturing a leadframe, packaging method for semiconductor element and semiconductor package product Pending CN101211794A (en)

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US60/871,993 2006-12-27

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Application publication date: 20080702