CN101211280B - Asynchronous control transfer method, device and system - Google Patents
Asynchronous control transfer method, device and system Download PDFInfo
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Abstract
Methods and apparatus to perform asynchronous control transfer are described. In one embodiment, upon occurrence of an event (e.g., an architectural event), a service routine data block (SRDB) is accessed to obtain the address of a yield service routine. Other embodiments are also described.
Description
Technical field
The present invention relates to asynchronous control shifts.
Background technology
The disclosure relates generally to electronic applications.More particularly, embodiments of the invention relate to the technology that the selection incident flows with the execution in the asynchronous system processor controls afterwards that takes place.
Number of mechanisms can be used for changing the control stream (processing path or the instruction sequence for example, followed) of processor.For example, can use the control stream that interrupts with in the asynchronous system change processor.In general, trigger conventional the interruption by the external device (ED) on the IC chip different with processor.Then, processor can respond this interruption through jumping to the interrupt handling routine routine.But interrupting generally maybe be by operating system or level of privilege other software programs shielding lower than operating system, under the situation of retouching operation system (OS) not, possibly have no chance to revise this type of control stream change condition.Therefore, the technology with the control stream of asynchronous system change processor of being used at present possibly be to have circumscribedly, and partly cause is that this type of technology possibly rely on the interruption that external device (ED) generates.
Summary of the invention
According to a first aspect of the invention, a kind of equipment that asynchronous transfer control is provided is provided, said equipment comprises:
Incident is kept watch on parts, is used to keep watch on the generation of one or more incidents that maybe be related with can be used for triggering the scheme that defines on the architecture of corresponding output incident;
First parts that are used to respond the generation of said incident and upgrade first storage unit, the data storage corresponding with said incident is in first storage unit; And
Be used to respond the generation of said incident and cause visit to second storage unit to call second parts of output service routine, the address of the said output service routine corresponding with said incident is stored in second storage unit.
According to preferred embodiment, the data corresponding with said incident comprise one or more in the index of gap marker symbol, scheme identifier, count value or the position to said second storage unit.
According to preferred embodiment, the address of the storehouse that the said service routine of said second cell stores will be visited.
According to preferred embodiment, one or more in said first or second storage unit comprise one or more in private cache, shared high-speed cache or the application memory.
According to preferred embodiment, said output service routine is stored in the 3rd storage unit.
According to preferred embodiment, cause that one or more instructions of said incident generation are carried out by performance element.
According to preferred embodiment, said first parts are included in the performance element.
According to preferred embodiment, one or more in said first parts or said first storage unit are included at least in one of them of a plurality of processor cores.
According to preferred embodiment, one or more on identical IC chip in said first parts, said first storage unit, a plurality of processor core or the high-speed cache.
According to a second aspect of the invention, a kind of method that is used for asynchronous transfer control is provided, has comprised:
Supervision maybe be related with can be used for triggering the scheme that defines on the architecture of corresponding output incident the generation of one or more incidents;
Upgrade data corresponding in first storage unit with incident;
The address of output service routine that will be corresponding with said incident is stored in second storage unit; And
Respond the generation of said incident and call said output service routine.
According to preferred embodiment, said method comprises that also definition is used to keep watch on one or more conditions of the generation of said incident.
According to preferred embodiment, after taking place, the incident that said method also is included in supervision generates the signal that said incident has taken place in indication, and the signal that generated of response and visit said second storage unit so that call said output service routine.
According to preferred embodiment, before calling said output service routine, also comprise the data corresponding with said incident are kept among storehouse or the service routine data block SRDB.
According to preferred embodiment, said method also is included in recovers the data corresponding with said incident from storehouse or SRDB when said output service routine finishes.
According to a third aspect of the invention we, a kind of computing system that asynchronous transfer control is provided is provided, said system comprises:
Incident is kept watch on parts, is used to keep watch on the generation of one or more incidents that maybe be related with can be used for triggering the scheme that defines on the architecture of corresponding output incident;
Be used to store first parts of the data corresponding with incident; And
Be used to respond the generation of said incident and cause visit to the service routine data block to call second parts of output service routine, the data storage corresponding with said service routine data block is in storer.
According to preferred embodiment, the data corresponding with said incident comprise one or more in the index of gap marker symbol, scheme identifier, count value or the position to the said storer.
According to preferred embodiment, said output service routine is stored in the said storer.
According to preferred embodiment, cause that one or more instructions of said incident generation are carried out by performance element.
According to preferred embodiment, said second parts are included at least in one of them of a plurality of processor cores, and said a plurality of processor cores are included in the processor.
According to preferred embodiment, said storer is coupled to audio devices.
Description of drawings
With reference to accompanying drawing detailed description is provided.In the accompanying drawings, the accompanying drawing that belongs to appears in the Far Left digit order number of reference signs sign this reference signs first.In different accompanying drawings, use identical reference signs to indicate similar or identical.
The block diagram of the embodiment of Fig. 1,5 and 6 graphic computing systems, this computing system can be used to the various embodiments that realizes that this paper discusses.
Fig. 2 illustrates the block diagram of the several portions of other assemblies of processor core and computing system according to an embodiment of the invention.
Fig. 3 diagram is according to a plurality of parts of the computing system of embodiment.
The process flow diagram of the method that generates output (yield) takes place to cause in Fig. 4 diagram according to the embodiment response events.
Embodiment
In the description hereinafter, many details have been set forth, so that thoroughly understand various embodiments.But, even without these specific detail, various embodiments that still can embodiment of the present invention.In other situation, known method, process, assembly and circuit are not described in detail, with the understanding of obstruction free to specific embodiment of the present invention.And, can use number of mechanisms (for example SIC (semiconductor integrated circuit) (" hardware "), be organized into certain combination of computer-readable instruction (" software ") or hardware and software in one or more programs) to carry out the many aspects of embodiments of the invention.For purposes of this disclosure, the citation to " logic " will mean hardware, software or their certain combination.
Some embodiment that can utilize this paper to discuss carry out the event handling operation.In one embodiment, " incident " is meant and possibly taked certain action or maybe not need be taked the situation of certain action by logic by logic.And, can event classification be become dissimilar based on the action that will take.For example, can some unusual (for example division by 0) be characterized by each synchronous event that takes place when carrying out corresponding instruction.On the other hand, can the interruption that external unit generates be characterized by asynchronous event, partly cause is that they possibly take place at any time.In one embodiment, " architectural events " is meant can be through for example being programmed into the incident or the situation of keeping watch in the passage with the information corresponding with architectural events, and hereinafter with reference Fig. 2 discusses this.In one embodiment, software can collocation channel so that monitoring software and/or hardware maybe otherwise can't observed some architectural events.For example, can miss being defined as of last level cache be used to carry out the architectural events that dynamic-configuration file guide is optimized.Can also the definition system fabric event keep watch on be positioned on the IC chip identical with processor or otherwise with the coprocessor of processor communication on situation about taking place.In one embodiment, " architectural events " generally can be meant event or situation in the processing resource that exists on the IC chip identical with processor or other logics.In certain embodiments, can the support system fabric event in the processor in a plurality of different generations.
In one embodiment, (or be detected and will take place) taking place afterwards in incident (for example architectural events), can utilize the address that is stored in the storage unit to start corresponding respond (for example output).This address can definite object response (for example output button.onrelease routine, hereinafter can be referred to as the output service routine).And storage unit (can be called service routine data block (SRDB)) can canned data be prepared computing system response for example switching storehouse, shift the incident or the situation of control, and/or uses new memory context.Storage unit can also provide the space to come stores processor incident or situation recoverable system context afterwards.
In one embodiment, can use the multiple logic that provides in the processor to carry out the event handling task, the processor of for example discussing with reference to figure 1,2,5 and 6.More particularly, Fig. 1 illustrates the block diagram of computing system 100 according to an embodiment of the invention.System 100 can comprise one or more processor 102-1 to 102-N (being commonly referred to as " a plurality of processor 102 " or " processor 102 ").A plurality of processors 102 can be communicated by letter via interconnection network or bus 104.Each processor can comprise multiple assembly, and only reference processor 102-1 discusses wherein some for the sake of simplicity.Therefore, each processor of remaining processor 102-2 to 102-N can comprise the same or similar assembly that reference processor 102-1 discusses.
In one embodiment, processor 102-1 can comprise one or more processor core 106-1 to 106-M (be commonly referred to as " a plurality of nuclear 106 " or be called " nuclear 106 " more at large), high-speed cache 108 and/or the router one 10 shared.Processor core 106 can be realized on single integrated circuit (IC) chip.And; Chip can comprise one or more shared high-speed caches (for example high-speed cache 108) and/or private cache (for example 1 grade of (L1) high-speed cache 111-1 generally is called " L1 high-speed cache 111 " among this paper), bus or interconnection (for example bus or interconnection network 112), Memory Controller (those Memory Controllers of for example discussing with reference to figure 5 and 6) or other assemblies.
In one embodiment, can use router one 10 between the multiple assembly of processor 102-1 and/or system 100, to communicate.And processor 102-1 can comprise the router one 10 more than.And most routers (110) can be in communications status so that can realize the data route in the processor 102-1 or between the multiple assembly outside the processor 102-1.
The high-speed cache of sharing 108 can storer be processed the data (for example comprising instruction) that one or more assemblies (for example examining 106) of device 102-1 utilize.For example, the data that the high-speed cache of sharing 108 can be stored in local cache storage device 114 are so that be processed the component accesses of device 102 more quickly.In one embodiment, high-speed cache 108 can comprise intermediate-level cache (the for example high-speed cache of 2 grades (L2), 3 grades (L3), 4 grades (L4) or other grades), last level cache (LLC) and/or their combination.And the multiple assembly of processor 102-1 can directly be communicated by letter with shared high-speed cache 108 and/or Memory Controller or hub via bus (for example bus 112).As shown in Figure 1, service routine data block (SRDB) 120 can be stored in the storer 114.And SRDB 120 can be used to the response events generation and cause calling of output service routine by the assembly of nuclear 106, and hereinafter comes reference example such as Fig. 2-4 to this further argumentation.
Fig. 2 illustrates the block diagram of several portions of processor core 106 and other assemblies of computing system according to an embodiment of the invention.In one embodiment, arrow declarative instruction shown in Figure 2 is via the flow direction of examining 106.One or more processor cores (for example processor core 106) can be gone up at single integrated circuit chip (or tube core) and realize, for example discuss with reference to figure 1.And chip can comprise one or more shared and/or private caches (the for example high-speed cache 108 of Fig. 1), interconnection (the for example interconnection 104 and/or 112 of Fig. 1), Memory Controller or other assemblies.
As shown in Figure 2, processor core 106 can comprise and extracts the extraction unit 202 be used to examine 106 instructions carried out.These instructions can be extracted from any memory storage, for example can from storer 114 and/or the storage arrangement with reference to figure 5 and 6 argumentations, extract.Nuclear 106 can also comprise the decoding unit 204 with the instruction decoding of extracting.For example, decoding unit 204 can be decoded into a plurality of uop (microoperation) with the instruction of extracting.In addition, nuclear 106 can also comprise scheduling unit 206.Scheduling unit 206 can carry out the multiple operation related with storing decoded instruction (instruction that for example receives) from decoding unit 204 up to these instruction is ready supply to distribute till, for example only all be already available as up to the active value of decoded instruction.In one embodiment, scheduling unit 206 can and/or send (or distributing) with decoded instruction scheduling and is used for execution to performance element 208.Performance element 208 can be in instruction decoded (for example by the decoding unit 204 decoding) instruction that execution is distributed after also (for example by scheduling unit 206) distributed.In one embodiment, performance element 208 can comprise more than a performance element, for example memory execution unit, Integer Execution Units, performance element of floating point or other performance elements.Performance element 208 can also be carried out multiple arithmetical operation, for example addition, subtraction, multiplication and/or division, and can comprise one or more ALUs (ALU).In one embodiment, the coprocessor (not shown) can combine performance element 208 to carry out multiple arithmetical operation.
And performance element 208 can execute instruction out of orderly.Therefore, in one embodiment, processor core 106 can be an out-of order processor nuclear.Nuclear 106 can also comprise and withdraws from unit 210.Withdrawing from unit 210 can be withdrawed from by the instruction that will carry out after submitting in the instruction of carrying out.In one embodiment, the instruction of carrying out is withdrawed to be caused that physical register cancellation that processor state is submitted to, instruction is used from the execution of instruction distributes.
Nuclear 106 can also comprise the storage microcode and/or extract the trace cache or the microcode ROM (read-only memory) (uROM) 212 of tracking of the instruction of (for example by extraction unit 202 extract).The microcode of storage can be used to dispose the multiple hardwares assembly of nuclear 106 among the uROM 212.In one embodiment, can load the microcode of storage the uROM 212 from another assembly (computer-readable medium or other memory storages for example discussed) of communicating by letter with processor core 106 with reference to figure 5 and 6.Nuclear 106 can also comprise bus unit 214, can communicate by letter via one or more buses (for example bus 104 and/or 112) between the assembly that bus unit 214 makes processor core 106 and other assemblies assembly of figure 1 argumentation (for example with reference to).Nuclear 106 can also comprise one or more registers 216, the data of the multiple component accesses of these one or more register 216 storage nuclears 106.
And processor core 106 shown in Figure 1 can comprise and one group of one or more passage 218 that architecture state is corresponding.The passage that each level of privilege (for example level of privilege 0 or power user's level of privilege (for example high privilege level), level of privilege 3 (for example among the embodiment can corresponding to the relatively low level of privilege of user class privilege) etc.) can have a correspondence.And each passage 218 can also dispose one or more schemes, wherein scheme definition logical condition.Therefore, passage can comprise one group of architecture state, and comprises the logical condition description of configuration.In one embodiment, passage 218 can comprise scheme standard (scenario specification).Then, when logical condition (the being scheme) coupling of the configuration of the architecture state in the passage and this passage or when surpassing the logical condition of this configuration, can pass through signalisation output incident.Therefore, the output incident can be that response scheme takes place.Hereinafter with reference Fig. 3 discusses the further details of the embodiment of relevant passage.
In addition, nuclear 106 can comprise incident watchdog logic 220, and for example watchdog logic 220 is used for keeping watch on the generation of one or more incidents that maybe be related with can be used for triggering the scheme that defines on the architecture of corresponding output incident (for example passage 218).As shown in Figure 2, logic 220 can be provided in performance element 208.But, also can logic 220 be provided other positions in processor core 106.Like this paper reference example such as Fig. 3-4 are further discussed ground; Logic 220 can generate signal after the incident of keeping watch on takes place, and watchdog logic 221 for example can respond based on the data of storage in the passage 218 and upgrades the data of storing in SRDB 120 and/or the storehouse (can be stored in storer 114, L1 high-speed cache 111 and/or the high-speed cache 108 shared in).For example, the incident of supervision (the for example data about storing in the passage 218) possibly take place with respect to the execution of the present instruction sequence on the processor core 106 asynchronously.
And, as shown in Figure 2, can SRDB 120 be stored in wherein one or more high-speed caches of (or being buffered in) high-speed cache 111 and/or 108, and not be stored in (or being buffered in) storer 114 or also be stored in addition in (or being buffered in) storer 114.Storer 114 can also be stored following wherein one or more: output button.onrelease or service routine 222 (but for example response logic 220 detects incident and invoked program), operating system 224 (for example being used to manage the hardware of the computing system that comprises nuclear 106 or the operating system of software resource) and/or device driver 225 (for example be used to make OS 224 with reference to can the communicating devices driver between those multiple devices of figure 5 and 6 argumentations).In one embodiment, make watchdog logic 221 responses detect the incident of supervision and after visiting SRDB 120, can obtain the address of output service routine (222) in logic 220 from SRDB 120.
Fig. 3 diagram is according to a plurality of parts of the computing system of embodiment.For example, the possible information of storage in the passage shown in Fig. 3 218, and can this possible information be delivered to this passage as the parameter that EMONITOR instructs according at least one instruction set architecture.These parameters can comprise scheme specific information, the symbol of the gap marker among the register ecx and/or scheme identifier, the basic pointer (SRDS) among the register edx and the offset value (SRDBP) among the register ebx among the register eax.Scheme specific information among the register eax can index gauge numerical value, and this count value counts down from the initial value that is called beginning sampled value (sample after value), and when it reached zero, its underflow can cause that the output service routine is called.It is big more that this begins sampled value, and then sampling rate is low more.Gap marker symbol can be indicated the passage that will dispose through the execution of instruction.The scheme identifier is designated as the unique identifier that gap marker accords with the scheme of the channel arrangement that identifies.The pointer of the position of the SRDB 120 that SRDS is related with SRDBP conduct sensing jointly.SRDB 120 can comprise service routine stack segment (SRSS), the corresponding output incident storehouse of storage in this service routine stack segment (SRSS) and the service routine stack pointer (SRSP) id memory 114 together.Perhaps, can use single value to point to or index SRDB 120.As shown in Figure 3, SRDB 120 all right stores service routine instructions pointer (SRIP) and service routine code segments (SRCS), they jointly indicate output service (222) routine that is stored in the storer 114.In various embodiments, as alternative, any one field or the whole field that reside among the SRDB 120 can reside in the processor core (106).They are kept at the quantity that can reduce the software thread single user state that need carry out the context switching in the storer.
Therefore, in one embodiment, SRDB 120 can store and can be used for switching storehouse, shifts control and use the contextual information of new data-carrier store.And SRDB 120 can be retained in the application memory (the for example part of storer 114) between context switches, and need not to preserve or recover SRDB 120.And, the output service routine (222) and/or the output incident storehouse that can use single value to point to be stored in the storer 114.Can also with output service routine (222) and/or output incident storehouse be stored in L1 high-speed cache 111 and/or the high-speed cache 108 shared in, except it being stored in storer 114 (for example can be the application memory part of storer 114) or substitute it is stored in the storer 114.Can also by any order with data storage in SRDB 120.Therefore, the structure of SRDB 120 shown in Figure 3 only is giving an example of an embodiment.
Fig. 4 diagram causes the process flow diagram of the method 400 that generates output according to the generation of embodiment response events.In certain embodiments, can utilize wherein one or more operations of carrying out the operation of discussing with reference to figure 4 with reference to the multiple assembly of figure 1-3 and 5-6 argumentation.For example, one of them a little operation of the operation of discussing with reference to figure 4 can be carried out with the SRDB item of 3 argumentations with reference to figure 2 by reference.
With reference to figure 1-4,, can (for example by the programmer) define multiple condition (for example scheme) in operation 402.In one embodiment, can be in passage 218 with the data storage corresponding with the condition of operation 402 definition.Can also for example dispose wherein one or more values of the value in the be stored in passage 218 that will index SRDB 120 in the relevant multiple information of the SRDB of operation 402 configurations and Fig. 2 and 3 120, for example with reference to those values of figure 3 argumentations.In operation 404, the one or more incidents architectural events of scheme (for example corresponding to) have been determined whether to take place.In one embodiment, logic 220 can be in operation 404 one or more incidents of having determined whether to take place in the passage 218.
Confirm that the incident of keeping watch on takes place, and then can confirm target response in operation 406 in case operate 404.For example, can be in the data of operation 406 access stored in passage 218, those data of for example discussing with reference to figure 3.At operation 406 and operation 407a, determine whether to upgrade corresponding state.The some of them of this state can be that passage is special-purpose, Counter Value for example, and some of them can be (the striding channel status) of sharing between the passage, for example point to pointer or the branch history information of it being taked the instruction of output.In operation 408, can determine whether also will the data corresponding with current event to be kept in the storer.In operation 408, can determine whether to cause output.If so talk about, operation 412 can be handled and call the necessary operation of output service routine.For example, when the incident of take place keeping watch on, can current SS, SP, DS, CS, IP and value of statistical indicant be stored among the SRDB 120 at operation 413a, and can from SRDB will be related with this service routine SS, SP, DS, CS and IP be loaded into processor.Need not to switch among the embodiment of storehouse not switching storehouse or discovery, can SS and SP be kept among the SRDB, do not switch to the value of storing among the SRDB.In alternative, but the information that will be kept among the SRDB from the execution context before the output is saved in storehouse, and when service routine finishes, it is recovered.In another embodiment, can this information be placed on the SRDB storehouse pointed.These methods can not accomplished at for example output service routine and carried out and another output service routine realizes nested being easy to of output event handling when being called.
In one embodiment, during the output service routine, can and stride channel status with the passage single user state and read into processor register or storer.Shown in 413B, can handle this state, and can take other actions.Handle in case accomplish output, shown in Figure 41 4, can when the end of output service routine (222), carry out specific instruction and accomplish event handling (415) with indication.Can return to processor with calling the data (for example SS, SP, DS, CS, IP and sign) that before had been kept in SRDB or the storehouse before the output service routine, and continue the execution of instruction stream.
In certain embodiments, can nested a plurality of outputs.That is, when carrying out an output service routine, possibly satisfy the condition of carrying out another output, for example afterwards with a plurality of output releases (for example, through removing output piece position (YBB)) at the output service routine.If allow this type of nested, then in one embodiment, can before removing YBB, carry out following operation:
(1) reads SRDB 120 segment bases (SRDS) and side-play amount (SRDBP) from passage, and use it to find SRDB, revise the SRSP field among the SRDB then.
(2) if knownly have living space availablely, then the SRSP field is lowered to and just is lower than current SRSP, otherwise adjust to another storehouse.Create the link between the storehouse by required strategic point among the SRDB 120.This possibly relate to the information that SRDB or old storehouse are pointed on new storehouse storage, so stack walk (stack walking) routine can be smoothly through the storehouse transfer with debugged program.
And, before withdrawing from the output service routine, can carry out following operation:
(1) YBB is set.
(2) read SRDB 120 segment bases (SRDS) and side-play amount (SRDBP) from passage, and use it to find and revise the SRSP field among the SRDB.
(3) this SRSP field is adjusted back its preceding value, this preceding value can be kept on the storehouse at operation 413a.
Fig. 5 illustrates the block diagram of computing system 500 according to an embodiment of the invention.Computing system 500 can comprise one or more CPU (CPU) 502 or the processor via interconnection network (or bus) 504 communications.Processor 502 can comprise the processor (comprising Reduced Instruction Set Computer (RISC) processor or CISC (CISC)) of general processor, network processing unit (data that this processor processes transmits through computer network 503) or other types.And processor 502 can have monokaryon or multinuclear design.Processor 502 with multinuclear design can be integrated in dissimilar processor cores on identical integrated circuit (IC) tube core.And the processor 502 with multinuclear design can be used as symmetry or asymmetric multiprocessor is realized.In one embodiment, one or more processors 502 can be same or analogous with the processor 102 of Fig. 1.For example, one or more processors 502 can comprise one or more nuclears 106 of discussing with reference to figure 1 and/or 2.Can also carry out the operation of discussing with reference to figure 1-4 by one or more assemblies of system 500.
Chipset 506 also can be communicated by letter with interconnection network 504.Chipset 506 can comprise memory controlling hub (MCH) 508.MCH 508 can comprise the Memory Controller 510 of communicating by letter with storer 512 (storer 512 can be same or similar with the storer 114 of Fig. 1).Storer 512 can be stored can be by the data (comprising instruction sequence) of any other device execution that comprises in CPU 502 or the computing system 500.In one embodiment of the invention; Storer 512 can comprise one or more volatile storage (or storer), for example the memory storage of random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or other types.Can also utilize the for example nonvolatile memory of hard disk etc.Attachment device (for example a plurality of CPU and/or a plurality of system storage) can be communicated by letter via interconnection network 504.
And computing system 500 can comprise volatibility and/or nonvolatile memory (or storage unit).For example; Nonvolatile memory can comprise following wherein one or more: the nonvolatile machine-readable media of ROM (read-only memory) (ROM), programming ROM (PROM), erasable PROM (EPROM), electric EPROM (EEPROM), disc driver (for example, 528), floppy disk, compact disk ROM (CD-ROM), digital versatile disc (DVD), flash memory, magneto-optic disk or other types that can storage of electronic (for example comprising instruction).
Fig. 6 is the computing system 600 that is provided with point-to-point (PtP) configuration according to an embodiment of the invention.Specifically, Fig. 6 illustrates wherein through the system of a plurality of point-to-point interfaces with processor, storer and input/output device interconnection.Can also carry out the operation of discussing with reference to figure 1-5 by one or more assemblies of system 600.
As shown in Figure 6, system 600 can comprise a plurality of processors, and for the sake of simplicity, two processors 602 and 604 only is shown.Processor 602 and 604 all can comprise can realize the local storage controller hub (MCH) 606 and 608 of communicating by letter with 612 with storer 610.Storer 610 and/or 612 can be stored several data, those data of for example discussing with reference to the storer 512 of figure 5.
In one embodiment, processor 602 and 604 can be one of them of the processor 502 discussed with reference to figure 5.Processor 602 and 604 can use PtP interface circuit 616 and 618 to come swap data via point-to-point (PtP) interface 614 respectively.Processor 602 and 604 all can also use point-to-point interface circuit 626,628,630 and 632 via PtP interface 622 separately and 624 with chipset 620 swap datas.Chipset 620 for example can also use PtP interface circuit 637 via graphic interface 636 and graphics circuitry 634 swap datas.
At least one embodiment of the present invention can provide in processor 602 and 604.For example, can one or more nuclears 106 of Fig. 1-2 be located in processor 602 and 604.But other embodiment of the present invention may reside in other circuit, logical block or the device in the system 600 of Fig. 6.And, can other embodiment of the present invention be distributed on a plurality of circuit shown in Figure 6, logical block or the device.
Chipset 620 can use PtP interface circuit 641 to communicate by letter with bus 640.Bus 640 can be communicated by letter with one or more devices (for example bus bridge 642 and I/O device 643).Via bus 644, bus bridge 642 can with other devices of for example keyboard/mouse 645, communicator 646 (for example modulator-demodular unit, Network Interface Unit or other communicators that can communicate by letter with computer network 503), audio frequency I/O device 647 and/or data storage device 648 communications.Data storage device 648 can be stored the code of being carried out by processor 602 and/or 604 649.
In various embodiments of the present invention; The operation that this paper reference example such as Fig. 1-6 discusses can be used as hardware (for example logical circuit), software, firmware or their combination and realizes, can be used as computer program (for example comprise storing on it and be used for machine readable or the computer-readable medium of computer programming with the instruction (or software process) of the process of execution this paper argumentation) provides.Machine readable media can comprise those memory storages of for example discussing with reference to figure 1-6.
In addition; This type of computer-readable medium can be used as computer program and downloads, and wherein this program can be transferred to requesting computer (for example client computer) via communication link (for example bus, modulator-demodular unit or network connect) from remote computer (for example server) through the mode of the data-signal that comprises in carrier wave or other propagation mediums.Therefore, in this article, carrier wave should be regarded as and comprise machine readable media.
In this instructions the citation of " embodiment ", " embodiment " or " some embodiment " is represented that the special characteristic, structure or the characteristics that combine this embodiment to describe can be included at least one realization.Phrase " in one embodiment " appears in a plurality of diverse locations in this manual possibly refer to entirely that same embodiment possibly not be the same embodiment of full finger yet.
In description and the claim, also possibly use term " coupling " and " connection " and their derivation term hereinafter.In some embodiments of the invention, can use " connection " to indicate two or more parts to be in the contact of direct physics each other or electrically contact." coupling " can represent that two or more parts are in the contact of direct physics or electrically contact.But " coupling " can also represent that two or more parts possibly not be in each other directly contact, but still can collaborative work or mutual.
Therefore, though embodiments of the invention are to utilize the language that is exclusively used in architectural feature and/or method action to describe, it should be understood that the subject matter of prescription can be not limited to described these special characteristics or action.On the contrary, these special characteristics are to come disclosed as the sample form of the subject matter that realizes prescription with action.
Claims (20)
1. equipment that asynchronous transfer control is provided, said equipment comprises:
Incident is kept watch on parts, is used to keep watch on the generation of one or more incidents that maybe be related with can be used for triggering the scheme that defines on the architecture of corresponding output incident;
First parts that are used to respond the generation of said incident and upgrade first storage unit, the data storage corresponding with said incident is in first storage unit; And
Be used to respond the generation of said incident and cause that visit to second storage unit is to call second parts of output service routine; The address of the said output service routine corresponding with said incident is stored in said second storage unit and by service routine instruction pointer of storing in the service routine data block in said second storage unit and service routine code segment and jointly indicates said output service routine, and wherein said service routine data block is retained between transfer period in said second storage unit at context need not preserve and recover said service routine data block.
2. equipment as claimed in claim 1 is characterized in that, the data corresponding with said incident comprise one or more in the index of gap marker symbol, scheme identifier, count value or the position to said second storage unit.
3. equipment as claimed in claim 1 is characterized in that, the address of the storehouse that the said output service routine of said second cell stores will be visited.
4. equipment as claimed in claim 1 is characterized in that, one or more in said first or second storage unit comprise one or more in private cache, shared high-speed cache or the application memory.
5. equipment as claimed in claim 1 is characterized in that, said output service routine is stored in the 3rd storage unit.
6. equipment as claimed in claim 1 is characterized in that, causes that one or more instructions of said incident generation are carried out by performance element.
7. equipment as claimed in claim 1 is characterized in that, said first parts are included in the performance element.
8. equipment as claimed in claim 4 is characterized in that, one or more in said first parts or said first storage unit are included at least in one of them of a plurality of processor cores.
9. equipment as claimed in claim 8 is characterized in that, one or more on identical IC chip in said first parts, said first storage unit, a plurality of processor core or the high-speed cache.
10. one kind is used for the method that asynchronous transfer is controlled, and comprising:
Supervision maybe be related with can be used for triggering the scheme that defines on the architecture of corresponding output incident the generation of one or more incidents;
Upgrade data corresponding in first storage unit with incident;
The address of output service routine that will be corresponding with said incident is stored in second storage unit and by service routine instruction pointer of storing in the service routine data block in said second storage unit and service routine code segment and jointly indicates said output service routine, and wherein said service routine data block is retained between transfer period at context need not preserve and recover said service routine data block in said second storage unit; And
Respond the generation of said incident and call said output service routine.
11. method as claimed in claim 10 is characterized in that, comprises that also definition is used to keep watch on one or more conditions of the generation of said incident.
12. method as claimed in claim 11 is characterized in that, generates the signal that said incident has taken place in indication after the incident that also is included in supervision takes place, and the signal that generated of response and visit said second storage unit so that call said output service routine.
13. method as claimed in claim 10, wherein, said first storage unit is a passage.
14. method as claimed in claim 10, wherein, said second storage unit comprises the service routine data block.
15. the computing system that asynchronous transfer control is provided, said system comprises:
Incident is kept watch on parts, is used to keep watch on the generation of one or more incidents that maybe be related with can be used for triggering the scheme that defines on the architecture of corresponding output incident;
Be used to store first parts of the data corresponding with incident; And
Be used to respond the generation of said incident and cause that visit to the service routine data block is to call second parts of output service routine; The data storage corresponding with said service routine data block is in storer and comprise service routine instruction pointer and service routine code segment identifying said output service routine, and wherein said service routine data block is retained between transfer period in the said storer at context and need preserve and recover said service routine data block.
16. system as claimed in claim 15 is characterized in that, the data corresponding with said incident comprise one or more in the index of gap marker symbol, scheme identifier, count value or the position to the said storer.
17. system as claimed in claim 15 is characterized in that, said output service routine is stored in the said storer.
18. system as claimed in claim 15 is characterized in that, causes that one or more instructions of said incident generation are carried out by performance element.
19. system as claimed in claim 15 is characterized in that, said second parts are included at least in one of them of a plurality of processor cores, and said a plurality of processor cores are included in the processor.
20. system as claimed in claim 15 is characterized in that, said storer is coupled to audio devices.
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| US11/648,187 US8171270B2 (en) | 2006-12-29 | 2006-12-29 | Asynchronous control transfer |
| US11/648187 | 2006-12-29 |
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| CN101211280A CN101211280A (en) | 2008-07-02 |
| CN101211280B true CN101211280B (en) | 2012-07-04 |
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| JP (1) | JP5236278B2 (en) |
| CN (1) | CN101211280B (en) |
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| US20080162910A1 (en) | 2008-07-03 |
| CN101211280A (en) | 2008-07-02 |
| US8171270B2 (en) | 2012-05-01 |
| DE102007060783A1 (en) | 2008-07-24 |
| JP2008165793A (en) | 2008-07-17 |
| JP5236278B2 (en) | 2013-07-17 |
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