CN101198049B - Video data processing method and device - Google Patents
Video data processing method and device Download PDFInfo
- Publication number
- CN101198049B CN101198049B CN2007103085637A CN200710308563A CN101198049B CN 101198049 B CN101198049 B CN 101198049B CN 2007103085637 A CN2007103085637 A CN 2007103085637A CN 200710308563 A CN200710308563 A CN 200710308563A CN 101198049 B CN101198049 B CN 101198049B
- Authority
- CN
- China
- Prior art keywords
- component
- video
- video data
- decoding
- data encoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention discloses a video data processing method and a video data processing device. Because video encoding data is divided into three varieties of video components and the video components which belong to the same video encoding data can be respectively sent to three component decoding chips, the three component decoding chips can synchronously decode received video components, thereby image quality which is outputted finally can reach high definition television requirement in DCI criteria, and compared with the prior method and the prior device, data processing capacity can be effectively improved and video effect can be improved.
Description
Technical field
The present invention relates to medium technique, be specifically related to a kind of video data handling procedure and device.
Background technology
At present, medium techniques such as digital movie technology are being widely used, but owing to also be in developing stage, so its actual data-handling capacity, video effect etc. are merely able to reach the requirement of high definition television, and can't really satisfy the requirement of digital movie.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of video data handling procedure and device, to improve data-handling capacity, improves video effect.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of video data handling procedure, this method comprises:
The video data encoder that will meet the JPEG2000 standard is divided into luminance component, tone component and saturation component three class video components, the described three class video components that will belong to same video data encoder again send to three component decoding chips respectively in the synchronizing thread mode, described three component decoding chips carry out synchronous decoding to the video component of receiving to be handled, and described component decoding chip is ADV202; As master unit, two other component decoding chip is followed master unit and is kept synchronous working as from the unit with a described component decoding chip.
Wherein, further described video component is ranked before sending, the described video component of transmission is the video component of dequeue.Divide before the described video component, further described video data encoder is read in the internal memory from server hard disc.
The video component that described video data encoder marked off is finished after the described decoding processing, further notifies the upper layer application of managing internal memory to issue the video component of next video data encoder in the mode of Interrupt Process.
This method further comprises: timing, and do not produce yet after overtime under the situation of Interrupt Process and report error result.
A kind of video data processing apparatus, this device comprise continuous driver element and comprise the video component decoding unit of three component decoding chips that described decoding chip is ADV202; Wherein,
Described driver element, the video data encoder that is used for meeting the JPEG2000 standard is divided into luminance component, tone component and saturation component three class video components, and each video component that will belong to same video data encoder sends to the video component decoding unit respectively;
Described video component decoding unit, be used to control its three component decoding chips that comprise the video component of receiving is carried out the synchronous decoding processing, as master unit, two other component decoding chip is followed master unit and is kept synchronous working as from the unit with a described component decoding chip.
Be provided with request queue and thread in the described driver element at described each decoding chip; Described request formation and thread, each video component that is used for belonging to same video data encoder sends to described three component decoding chips respectively in the synchronizing thread mode.
Described driver element further links to each other with applying unit, and this applying unit is used for described video data encoder is read the internal memory that is provided with described driver element from server hard disc.Linking to each other between described driver element and the described video component decoding unit realizes by pci interface.
As seen, video data handling procedure provided by the present invention and device, because video data encoder is divided into three class video components, and each video component that belongs to same video data encoder can be sent to three component decoding chips respectively, therefore three component decoding chips can carry out the synchronous decoding processing to the video component of receiving.This makes the picture quality of final output can reach the high definition television requirement in the DCI standard, can effectively improve data-handling capacity relatively at present, improves video effect.
Description of drawings
Fig. 1 is the video data processing apparatus figure of one embodiment of the invention;
Fig. 2 is the video data process chart of one embodiment of the invention;
Fig. 3 is a video data handling process sketch of the present invention.
Embodiment
Below in conjunction with accompanying drawing the technology of the present invention is described in detail.
Referring to Fig. 1, Fig. 1 is the video data processing apparatus figure of one embodiment of the invention.Among Fig. 1, applying unit, operating system I/O manager, driver element, pci interface, video component decoding unit link to each other successively.Wherein, be provided with upper level applications in the applying unit; Be provided with three component decoding chips in the video component decoding unit; Main control unit links to each other with other device, is used for each device is comprised that operation is controlled at interior management.
During concrete the application, applying unit can obtain video data encoder from server hard disc, and the video data encoder that gets access to is carried in the DMA request sends to operating system I/O manager, operating system I/O manager then is carried on the video data encoder that is comprised in the DMA request of receiving in the IRP request and sends in the internal memory.Particularly, can video data encoder be transferred in the internal memory in real time by the DMA passage of pci interface.
After the device control cell that is arranged in the driver element (this driver element is to be formed by the driver that operating system I/O manager is loaded into internal memory) of internal memory is received the video data encoder of IRP request, the video data encoder of receiving is divided into three class video components (as: luminance component in the TV domain and chrominance component are reclassified as luminance component, tone component, saturation component), and ready-portioned three class video components is lined up in corresponding D MA request queue respectively according to component decoding chip ID and the FIFO ID in the IRP request.
Afterwards, the DMA passage that is used for video component is sent to decoding chip for the video component application of wanting dequeue, and dequeue and each video component of belonging to same video data encoder sent to three component decoding chips respectively in the synchronizing thread mode, by three component decoding chips the video component of receiving is carried out synchronous decoding and handle.Wherein, the one-component decoding chip can be used as master unit, and two other component decoding chip is followed master unit and kept synchronous working as from the unit.
Particularly, in order to realize high speed, the synchronous transmission of data between driver element and the component decoding chip, can carry out transfer of data in many DMA thread mode of many formations of having synchronization mechanism.As: each component decoding chip comprises several FIFO; Then at each FIFO of each component decoding chip, each uses a DMA request queue and a DMA thread to realize rapid data transmission.Driver element can be supported single CPU or multi-CPU system.
In order to guarantee to transmit the continuation and the stationarity of video data encoder, can use two transfer of data threads to share one group of internal memory, be used for from server hard disc to internal memory transmission of video coded data as: thread, another thread is used for from internal memory to component decoding chip transmission of video component.
When practical application, the Interrupt Process unit that links to each other with the video component decoding unit can also be set, each component decoding chip all can be notified the Interrupt Process unit after receiving video component.When knowing that three component decoding chips have been received all video components that belong to same video data encoder, the Interrupt Process unit is notified applying unit to send modes such as interrupt signal by main control unit, operating system I/O manager, and applying unit issues the video component of next video data encoder at notified back tissue.
Certainly, the timer that links to each other with device control cell can also be set in driver element, and when issuing video component, start this timer by device control cell.When timer expiry, timer issues the video component failure in modes such as transmission level signals by main control unit, operating system I/O manager notice applying unit, and applying unit carries out operations such as video component repeating transmission after notified.
Need to prove that the ADV202 chip can be used as the component decoding chip, the performance of ADV202 chip is mainly:
1) realized JPEG2000 Code And Decode fully to image;
2) 6 layer 9/7 and the positive inverse transformation of 5/3 small echo of support 16bit station accuracy;
3) be 65MS/s to the maximum input rate of irreversible compression;
4) multi-disc ADV202 chip is united use and can be realized real time codec to high-definition picture;
5) by master control interface flexibly can with multiple 16bit and the seamless link of 32bit microcontroller.
This communication interface has, described pci interface can be replaced with the communication interface of other protocol type, as long as can be supported at a high speed, synchronous data transmission.
In addition, also need to carry out in advance some initial parameter settings, as: determine that working method is the decompression mode, the ADV202 chip is carried out BOOT operation, selects to carry out the file that video data handles, the parameter (memory cache, volume of transmitted data, image are play frame information) of carrying out register parameters setting, display data transmissions etc.
In sum, when application device shown in Figure 1 carries out the video data processing, the transmission speed of each DMA thread can satisfy the peak transfer rate (250M bits/s) that DCI requires fully, and can guarantee to be transferred to the synchronism of each component decoding chip, output frame rate was stabilized in for 24 frame/seconds, picture quality reaches the high definition television requirement in the DCI standard, can effectively improve data-handling capacity relatively at present, improves video effect.
If will explain with flow process at the description of Fig. 1, then as shown in Figure 2.Referring to Fig. 2, Fig. 2 is the video data process chart of one embodiment of the invention, and this flow process may further comprise the steps:
Step 201: the video data encoder in the server hard disc is read in internal memory.
Step 202: the video data encoder in the internal memory is divided into three class video components, and every class video component is lined up respectively.
Step 203: dequeue and each video component of belonging to same video data encoder are sent to three component decoding chips respectively in the synchronizing thread mode.
Step 204: judge whether three component decoding chips have received all video components that belong to same video data encoder, if enter step 205; Otherwise, directly enter step 206.
Step 205: three component decoding chips carry out synchronous decoding to the video component of receiving to be handled, and returns step 203 to produce the mode of interrupting when not finishing whole decode operation as yet.
Step 206: judge whether the timer that is started is overtime when the component decoding chip issues video component, if enter step 207; Otherwise, return step 204.
Step 207: report error result.
As seen from Figure 1, Figure 2, the critical workflow in the video data processing procedure of the present invention as shown in Figure 3.Referring to Fig. 3, Fig. 3 is a video data handling process sketch of the present invention, and this flow process may further comprise the steps:
Step 301: video data encoder is divided into three class video components.
Step 302: each video component that will belong to same video data encoder sends to three component decoding chips respectively.
Step 303: three component decoding chips carry out synchronous decoding to the video component of receiving to be handled.
By the above as seen, video data handling procedure provided by the present invention and device, because video data encoder is divided into three class video components, and each video component that belongs to same video data encoder can be sent to three component decoding chips respectively, therefore three component decoding chips can carry out the synchronous decoding processing to the video component of receiving.This makes the picture quality of final output can reach the high definition television requirement in the DCI standard, can effectively improve data-handling capacity relatively at present, improves video effect.
Claims (9)
1. a video data handling procedure is characterized in that, this method comprises:
The video data encoder that will meet the JPEG2000 standard is divided into luminance component, tone component and saturation component three class video components, the described three class video components that will belong to same video data encoder again send to three component decoding chips respectively in the synchronizing thread mode, described three component decoding chips carry out synchronous decoding to the video component of receiving to be handled, and described component decoding chip is ADV202; As master unit, two other component decoding chip is followed master unit and is kept synchronous working as from the unit with a described component decoding chip.
2. method according to claim 1 is characterized in that, further described video component is ranked before sending, and the described video component of transmission is the video component of dequeue.
3. according to each described method of claim 1 to 2, it is characterized in that, divide before the described video component, further described video data encoder is read in the internal memory from server hard disc.
4. method according to claim 3, it is characterized in that, the video component that described video data encoder marked off is finished after the described decoding processing, further notifies the upper layer application of managing internal memory to issue the video component of next video data encoder in the mode of Interrupt Process.
5. method according to claim 4 is characterized in that, this method further comprises:
Timing, and do not produce yet after overtime under the situation of Interrupt Process and report error result.
6. a video data processing apparatus is characterized in that, this device comprises continuous driver element and comprise the video component decoding unit of three component decoding chips that described decoding chip is ADV202; Wherein,
Described driver element, the video data encoder that is used for meeting the JPEG2000 standard is divided into luminance component, tone component and saturation component three class video components, and each video component that will belong to same video data encoder sends to the video component decoding unit respectively;
Described video component decoding unit, be used to control its three component decoding chips that comprise the video component of receiving is carried out the synchronous decoding processing, as master unit, two other component decoding chip is followed master unit and is kept synchronous working as from the unit with a described component decoding chip.
7. device according to claim 6 is characterized in that, is provided with request queue and thread at described each decoding chip in the described driver element; Described request formation and thread, each video component that is used for belonging to same video data encoder sends to described three component decoding chips respectively in the synchronizing thread mode.
8. according to claim 6 or 7 described devices, it is characterized in that described driver element further links to each other with applying unit, this applying unit is used for described video data encoder is read the internal memory that is provided with described driver element from server hard disc.
9. according to claim 6 or 7 described devices, it is characterized in that linking to each other between described driver element and the described video component decoding unit realizes by pci interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007103085637A CN101198049B (en) | 2007-12-29 | 2007-12-29 | Video data processing method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007103085637A CN101198049B (en) | 2007-12-29 | 2007-12-29 | Video data processing method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101198049A CN101198049A (en) | 2008-06-11 |
| CN101198049B true CN101198049B (en) | 2010-06-09 |
Family
ID=39548144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007103085637A Expired - Fee Related CN101198049B (en) | 2007-12-29 | 2007-12-29 | Video data processing method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101198049B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103036804B (en) * | 2011-10-08 | 2016-02-03 | 腾讯科技（深圳）有限公司 | The method and system of net control uploading speed |
| CN105306949B (en) * | 2015-12-04 | 2020-05-26 | 中星技术股份有限公司 | Video encoding method and apparatus |
| CN106502935A (en) * | 2016-11-04 | 2017-03-15 | 郑州云海信息技术有限公司 | FPGA isomery acceleration systems, data transmission method and FPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1193443A (en) * | 1996-05-14 | 1998-09-16 | 三星电子株式会社 | Apparatus for decoding video data |
| CN1341328A (en) * | 1999-10-21 | 2002-03-20 | 皇家菲利浦电子有限公司 | Playback apparatus and method for playback of record carrier |
| CN101076119A (en) * | 2006-05-17 | 2007-11-21 | 株式会社东芝 | Device and method for mpeg video playback |
-
2007
- 2007-12-29 CN CN2007103085637A patent/CN101198049B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1193443A (en) * | 1996-05-14 | 1998-09-16 | 三星电子株式会社 | Apparatus for decoding video data |
| CN1341328A (en) * | 1999-10-21 | 2002-03-20 | 皇家菲利浦电子有限公司 | Playback apparatus and method for playback of record carrier |
| CN101076119A (en) * | 2006-05-17 | 2007-11-21 | 株式会社东芝 | Device and method for mpeg video playback |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101198049A (en) | 2008-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7051110B2 (en) | Data reception/playback method and apparatus and data transmission method and apparatus for providing playback control functions | |
| US7929553B2 (en) | System and method for adjusting compression for computing clients based on a latency level | |
| US20020150123A1 (en) | System and method for network delivery of low bit rate multimedia content | |
| US8300699B2 (en) | System, method, and computer-readable medium for reducing required throughput in an ultra-wideband system | |
| US11258631B2 (en) | Streaming on diverse transports | |
| EP3253052A1 (en) | Data processing apparatus and control method thereof | |
| WO2008021126A2 (en) | Method and apparatus for encoding and distributing media data | |
| US20070104377A1 (en) | IMAGE CAPTURING APPARATUS AND IMAGE CAPTURING METHOD mmmmm | |
| US20110317763A1 (en) | Information processing apparatus and information processing method | |
| CA2326664A1 (en) | Apparatus and method for controlling transfer of data between interconnected data processing elements and processing of data by these data processing elements | |
| WO2010144488A2 (en) | Dual-mode compression of images and videos for reliable real-time transmission | |
| US6446155B1 (en) | Resource bus interface | |
| CN101198049B (en) | Video data processing method and device | |
| CN101365138A (en) | JPEG2000 image compression processing system | |
| CN101198050B (en) | Video data processing method and device | |
| US6108447A (en) | Method and apparatus for estimating frame rate for data rate control | |
| CN103686077A (en) | Double buffering method applied to realtime audio-video data transmission of 3G wireless network | |
| CN113709493B (en) | Video stream data encryption device, method and equipment of KVM system | |
| KR20040111426A (en) | Mixing of multiple streams of audio/video data from multiple sources within a receiving device allowing external control | |
| WO2024051674A1 (en) | Image processing circuit and electronic device | |
| US7496114B2 (en) | IP image transmission apparatus | |
| Costa et al. | Wall screen: an ultra-high definition video-card for the internet of things | |
| US6006300A (en) | System for isolating high-band-width signals transmitted between latency and jitter sensitive devices coupled to a secondary bus from operations on a primary bus | |
| US6389149B1 (en) | Method and apparatus to improve video processing in a computer system or the like | |
| CN109510998A (en) | The method for obtaining unpressed IP Camera initial data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: DADI ORISTAR TECHNOLOGY DEVELOPMENT (BEIJING) CO., Free format text: FORMER OWNER: BEIJING CE OPEN SOURCE INFORMATION TECHNOLOGY CO., LTD. Effective date: 20110720 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100176 BUILDING 2, AREA A, NO. 1, DISHENG NORTH STREET, BEIJING ECONOMIC AND TECHNOLOGICAL DEVELOPMENT ZONE, BEIJING TO: 100176 ROOM 404, BUILDING 2, AREA A, NO. 1, DISHENG NORTH STREET, BEIJING ECONOMIC AND TECHNOLOGICAL DEVELOPMENT ZONE, BEIJING |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20110720 Address after: 404, room 2, building 1, A District, 100176 North Sheng Bei street, Beijing economic and Technological Development Zone, Beijing, China Patentee after: Oristar Technology Development (Beijing)Co., Ltd. Address before: 100176, No. 2, building A, 1 North st, Sheng Bei street, Beijing economic and Technological Development Zone, Beijing Patentee before: Beijing CE Open Source Software Co., Ltd. |
|
| DD01 | Delivery of document by public notice |
Addressee: Oristar Technology Development (Beijing)Co., Ltd. Document name: Notification of Termination of Patent Right |
|
| DD01 | Delivery of document by public notice |
Addressee: Oristar Technology Development (Beijing)Co., Ltd. Document name: Notification to Go Through Formalities Rectification of Restoration of Right |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100609 Termination date: 20111229 |