CN101191925B - LCD display device and its display panel - Google Patents

LCD display device and its display panel Download PDF

Info

Publication number
CN101191925B
CN101191925B CN2006101639484A CN200610163948A CN101191925B CN 101191925 B CN101191925 B CN 101191925B CN 2006101639484 A CN2006101639484 A CN 2006101639484A CN 200610163948 A CN200610163948 A CN 200610163948A CN 101191925 B CN101191925 B CN 101191925B
Authority
CN
China
Prior art keywords
switch
electrically connects
pixel
display
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2006101639484A
Other languages
Chinese (zh)
Other versions
CN101191925A (en
Inventor
杜长庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chunghwa Picture Tubes Ltd
Original Assignee
Chunghwa Picture Tubes Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chunghwa Picture Tubes Ltd filed Critical Chunghwa Picture Tubes Ltd
Priority to CN2006101639484A priority Critical patent/CN101191925B/en
Publication of CN101191925A publication Critical patent/CN101191925A/en
Application granted granted Critical
Publication of CN101191925B publication Critical patent/CN101191925B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The present invention discloses a liquid crystal display and a display panel thereof. The display panel is provided with a common voltage generating circuit added to at least one pixel in an inactive pixel region; the average of positive polarity voltage and negative polarity voltage is acquired in two-frame time according to the display voltage of a drain electrode end of a thin film transistor inside the pixel, so as to be taken as common voltage and sent to every pixel in an active pixel region inside the display panel. Therefore, the present invention can obviously improve the feedthroughvoltage (delta VD) shift of scanning voltage which is caused by the RC delay of parasitic capacitance and parasitic resistance on scan lines, then promotes the gray-scale accuracy of every pixel of the active pixel region inside the display panel, and decreases the flicker noise of the display panel, so as to greatly promote the frame quality shown by the liquid crystal display.

Description

LCD and display panel thereof
Technical field
The present invention is about a kind of display and display panel thereof, and is particularly to a kind of LCD and the display panel thereof that can adjust common voltage automatically.
Background technology
(Liquid Crystal Display LCD) is widely used LCD recently, and (Cathode Ray Tube CRT) becomes one of the main flow of display of future generation to replace cathode-ray tube display.Improvement along with semiconductor technology, make that LCD has low consumption of electric power, slim amount is light, resolution is high, color saturation is high, the life-span is long ... etc. advantage, thereby be widely used on the liquid crystal screen of computer and LCD TV (LCDTV) etc. and the closely bound up electronic product of life.
Fig. 1 is existing Thin Film Transistor-LCD (Thin Film Transistor Liquid CrystalDisplay, pixel structure 100 figure TFT-LCD).Please refer to Fig. 1, pixel structure 100 comprises thin film transistor (TFT) 101, liquid crystal capacitance C LC, memory capacitance Cs, common electrode CE, and stray capacitance Cgd.Wherein, can find out obviously that memory capacitance Cs is the design of on common electrode CE (Cs on common) by the electrical connection of the pixel structure 100 that Fig. 1 disclosed.Fig. 2 is another pixel structure 200 figure of existing Thin Film Transistor-LCD.Please merge with reference to Fig. 1 and Fig. 2, pixel structure 200 and pixel structure 100 maximum different are in the memory capacitance Cs of pixel structure 200 and are the design of (Cs on gate) on grid.
And no matter adopt above-mentioned any pixel structure, as gate drivers (gate driver, not illustrating) scanning voltage (VG) exported promptly reduces to low-potential voltage (VGL) by high-potential voltage (VGH), and when causing thin film transistor (TFT) 101 to be closed, the coupling effect (coupling effect) that is caused because of stray capacitance Cgd is so the drain electrode end d voltage of thin film transistor (TFT) 101 is with a time voltage potential (the Δ V that also can descend D), its value can be expressed as:
Δ V D = C gd C gd + C s + C LC Δ V GP Formula 1
Wherein, the Δ V of formula 1 GPFor noble potential scanning voltage VGH deducts electronegative potential scanning voltage VGL, that is Δ V GP=VGH-VGL, and the voltage potential of this change (Δ V D) be called the feed-trough voltage (feed-through voltage) of scanning voltage, and be not to be a constant.
Yet, what deserves to be mentioned is, because of the physical characteristics of liquid crystal molecule, so cause liquid crystal capacitance C LCCan different capacitances be arranged along with different GTGs (gray level) cross-pressure, thus as can be known be the pixel of each different GTG (pixel), the feed-trough voltage of its scanning voltage (Δ V D) value also can be different.In addition, well known, must have the existence of stray capacitance (parasitic capacitance) and dead resistance (parasitic resistance) on each the bar sweep trace in the display panel (not illustrating), so above-mentioned Δ V GPCan be subjected to the influence of stray capacitance and dead resistance on the sweep trace, also be that so-called RC postpones (RC delay), and cause Δ V GPFrom scanning voltage input end position far away more, its value can be more little at display panel.In addition, the RC of each bar sweep trace postpones to be not quite similar again in the display panel, so feed-trough voltage (the Δ V of same delegation (column) pixel in the display panel D) value also might be different.
By above-mentioned mentioned feed-trough voltage (the Δ V that causes scanning voltage D) being worth two different factors, no matter which factor all can promote the flicker noise (flicker noise) of display panel for it, and the frame flicker that causes TFT-LCD to present.So feed-trough voltage (Δ V in order to alleviate above-mentioned scanning voltage D) problem, the correlation technique that also corresponding now development goes out to solve, it comprises:
1. according to feed-trough voltage (the Δ V of scanning voltage D) value, and adjust the common voltage provide to the display panel interior pixel (common voltage, Vcom).
2. use the Driving technique of the scanning voltage on 3 rank or 4 rank.
Be applicable to above-mentioned pixel structure that discloses 100 (Cs oncommon) and pixel structure 200 (Cs on gate) in the above-mentioned solution correlation technique 1 that develops, it utilizes the measurement of optics by a deviser, observation is also adjusted the common voltage Vcom that provides to the display panel interior pixel, so that the flicker noise of display panel central part is reduced to minimum.Then, with the above-mentioned common voltage of adjusting fixing after, finely tune the outside gamma (gamma) of source electrode driver (sourcedriver) again and revise voltage, cause liquid crystal capacitance Cu value to change feed-trough voltage (the Δ V of the scanning voltage that causes because of different GTG cross-pressures with compensation D) drift.And what deserves to be mentioned is that though it is minimum in the above-mentioned solution correlation technique 1 that develops the flicker noise of display panel central part to be reduced to, the flicker noise of display panel both sides is not resolved fully.
Fig. 3 is the analog waveform figure of above-mentioned solution correlation technique 1.Please merge with reference to Fig. 1～Fig. 3, by finding out among the analog waveform figure that Fig. 3 disclosed, it comprises the waveform (also being the display voltage of the drain electrode end d of thin film transistor (TFT) 101) of the waveform of scanning voltage VG, the waveform of data voltage Vs (also being the data voltage that the source terminal s reception sources driver of thin film transistor (TFT) 101 is provided), display voltage VD, and the waveform of common voltage Vcom.Wherein, by display voltage V DWaveform in can obviously find out the above-mentioned coupling effect that stray capacitance Cgd caused, and the feed-trough voltage Δ V of the scanning voltage that produces D
According to the above, use the feed-trough voltage Δ V that above-mentioned solution correlation technique 1 alleviates scanning voltage DProblem the time, it must carry out complicated manual measurement, provides common voltage Vcom to the display panel interior pixel to find the best.In addition, the characteristic of each sheet display panel is not quite similar, so the gamma correction voltage of above-mentioned best common voltage Vcom that determines and fine setting source electrode driver outside might not meet each sheet display panel fully.
In addition, be only applicable to above-mentioned disclosed pixel structure 200 (Cs on gate) in the above-mentioned solution correlation technique 2 that develops.Fig. 4 is above-mentioned solution correlation technique 2, and it adopts the analog waveform figure of the Driving technique of 3 rank scanning voltages.Please merge with reference to Fig. 2 and Fig. 4, solving correlation technique 2 and be by the scanning voltage VG at last sweep trace Gm-1 is electronegative potential, also is electronegative potential scanning voltage VGL1 (m-1), and at the scanning voltage VG of sweep trace Gm feed-trough voltage Δ V takes place DAfter, promote a voltage potential Vp to electronegative potential scanning voltage VGL2 (m-1) at the electronegative potential scanning voltage VGL1 (m-1) of sweep trace Gm-1, and after seeing through the voltage coupling effect of memory capacitance Cs, add a sweep trace Gm voltage potential Vp who is promoted in electronegative potential scanning voltage VGL1 (m) to electronegative potential scanning voltage VGL2 (m), and compensate the feed-trough voltage Δ V of the scanning voltage VG of sweep trace Gm through the voltage coupling effect of stray capacitance Cgd simultaneously DDrifting problem.
About the mentioned lifting one voltage potential Vp of above-mentioned solution correlation technique 2, can calculate generation according to following two formula in theory, it comprises:
Δ V D = C gd C gd + C s + C LC Δ V GP Formula 2
Δ V D = C s C gd + C s + C LC Δ V GP Formula 3
Yet, when the deviser desires to want to design the Driving technique of multistage (for example being 3 rank or 4 rank) scanning voltage of above-mentioned solution correlation technique 2, what well imagine is, the design complexities of gate drivers (gate driver) will increase, and when gate drivers can accurately not produce above-mentioned this voltage potential Vp that promotes, the feed-trough voltage Δ V of the scanning voltage VG of sweep trace Gm DWill be compensated or overcompensation by deficiency, so more increase design and the uncertainty that measures.In addition, above-mentioned solution correlation technique 2 also must cooperate the gamma correction voltage of fine setting source electrode driver outside, causes liquid crystal capacitance C with compensation because of different GTG cross-pressures LCValue changes, feed-trough voltage (the Δ V of the scanning voltage that causes D) drift.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of display panel, it uses voltage generation circuit at least one pixel of non-active pixel region altogether by adding, and in N frame (N is a positive integer, for example being 2 frame) time adjusts the common voltage of the one-row pixels in the corresponding display panel of this pixel automatically, can save by this that prior art is described must to carry out complicated manual correction common voltage formality, can guarantee more that so the common voltage that provided is the required optimum voltage current potential of this row pixel in the display panel instantly.
Another object of the present invention just provides a kind of display, spirit according to the invention described above display panel, can be used in the display of the present invention, not only can reach outside the advantage of the invention described above display panel by this, and more can reduce the flicker noise (flicker noise) of display panel, promote the frame quality that display was presented to reach.
Based on above-mentioned and other purpose, display panel provided by the present invention comprises first pixel region, second pixel region, and common voltage produces circuit.Wherein, first pixel region has a plurality of first pixels, arranges with array way.Second pixel region has a plurality of second pixels, is configured in the previous column of next-door neighbour's first pixel region, next column or previous column and next column pixel part.Common voltage produces circuit and electrically connects at least one second pixel, and wherein one-row pixels in corresponding first pixel region of each second pixel.Wherein, common voltage produces the display voltage of circuit according to this second pixel, and all first pixels in common voltage to the first pixel region are provided, and this common voltage is the mean value of the display voltage of the display voltage of positive polarity and negative polarity.
From another viewpoint, the invention provides a kind of display, comprise display panel and gate drivers, and this display panel comprises first pixel region, second pixel region, and common voltage produces circuit.Wherein, first pixel region has a plurality of first pixels, arranges with array way.Second pixel region has a plurality of second pixels, is configured in the previous column of next-door neighbour's first pixel region, next column or previous column and next column part.Common voltage produces circuit and electrically connects at least one second pixel, and wherein one-row pixels in corresponding first pixel region of each second pixel.
Gate drivers electrically connects display panel, and this gate drivers has many gate wirings, in order to foundation one basic sequential, and in regular turn to first pixel and the second pixel corresponding scanning beam of each bar gate wirings output scanning voltage to correspondence.Wherein, common voltage produces the display voltage of circuit according to this second pixel, and all first pixels in common voltage to the first pixel region are provided, and this common voltage is the mean value of the display voltage of the display voltage of positive polarity and negative polarity.
According to the described display of preferred embodiment of the present invention, also comprise source electrode driver, it electrically connects display panel, this source electrode driver has many source electrode distributions, in order to foundation one image data, and utilize each bar source electrode distribution output display voltage to the first corresponding pixel corresponding data lines.
In an embodiment of the invention described above, each first and second pixel comprises the transistor AND gate memory capacitance.Wherein, transistorized gate terminal electrically connects a sweep trace, and its first leakage/source terminal then electrically connects a data line.Memory capacitance has first end and second end, and wherein first end electrically connects the transistorized second leakage/source terminal, and its second end is then in order to receive common voltage.
In an embodiment of the invention described above, each first and second pixel also comprises stray capacitance and liquid crystal capacitance.Wherein, stray capacitance has first end and second end, and wherein first end electrically connects above-mentioned sweep trace, and its second end then electrically connects the transistorized second leakage/source terminal.Liquid crystal capacitance has first end and second end, and wherein first end electrically connects the transistorized second leakage/source terminal, and its second end is then in order to receive common voltage.
In an embodiment of the invention described above, transistor comprises thin film transistor (TFT).
In an embodiment of the invention described above, common voltage produces circuit and comprises first operational amplifier, first switch, second switch, the 3rd switch, the 4th switch, first electric capacity, second electric capacity, the 5th switch, second operational amplifier, the 6th switch, the 3rd electric capacity, and the 3rd operational amplifier.Wherein, first operational amplifier has positive input terminal, negative input end and output terminal, and wherein positive input terminal electrically connects the transistorized second leakage/source terminal, and its negative input end and output terminal then are electrically connected to each other together.First switch has first end, second end and control end, and wherein first end electrically connects the output terminal of first operational amplifier.
Second switch has first end, second end and control end, and wherein first end electrically connects first end of first switch.The 3rd switch has first end, second end and control end, and wherein first end electrically connects first end of second switch.The 4th switch has first end, second end and control end, and wherein first end electrically connects second end of first switch, and its second end is ground connection then.
First electric capacity has first end and second end, and wherein first end electrically connects second end of first switch, and second end then electrically connects second end of second switch.Second electric capacity has first end and second end, and wherein first end electrically connects second end of second switch, and its second end then electrically connects second end of the 3rd switch.The 5th switch has first end, second end and control end, and wherein first end electrically connects second end of the 3rd switch, and its second end is ground connection then.
Second operational amplifier has positive input terminal, negative input end and output terminal, and wherein positive input terminal electrically connects second end of second switch, and its negative input end and output terminal then are electrically connected to each other together.The 6th switch has first end, second end and control end, and wherein first end electrically connects the output terminal of second operational amplifier.The 3rd electric capacity has first end and second end, and wherein first end electrically connects second end of the 6th switch, and its second end is ground connection then.The 3rd operational amplifier has positive input terminal, negative input end and output terminal, wherein positive input terminal electrically connects first end of the 3rd electric capacity, after its negative input end and output terminal then are electrically connected to each other together, with each first pixel in output common voltage to the first pixel region.
In an embodiment of the invention described above, the control end of the first, second, third, fourth, the 5th and the 6th switch is in order to foundation one control signal of correspondence, to determine its whether conducting.
In an embodiment of the invention described above, when above-mentioned control signal during in the phase one, first, second, third, fourth, the 5th and the 6th not conducting of switch, and when above-mentioned control signal during in subordinate phase, first, second and the 5th switch conduction, and the 3rd, the 4th and the 6th not conducting of switch.
In an embodiment of the invention described above, when above-mentioned control signal during in the phase III, first, second, third, fourth, the 5th and the 6th not conducting of switch, and when above-mentioned control signal during in the quadravalence section, the 4th switch conduction, and the first, second, third, the 5th and the 6th not conducting of switch.
In an embodiment of the invention described above, when above-mentioned control signal during in five-stage, the the 3rd and the 4th switch conduction, and first, second, the 5th and the 6th not conducting of switch, and when above-mentioned control signal during in the 6th stage, the the 4th and the 6th switch conduction, and the first, second, third and the 5th not conducting of switch.
In an embodiment of the invention described above, this above-mentioned row pixel is the middle position of putting of first pixel region.
In an embodiment of the invention described above, above-mentioned display panel comprises a display panels, and above-mentioned display comprises a LCD.
Display provided by the present invention and display panel thereof, because by adding at display panel altogether with voltage generation circuit at least one second pixel in second pixel region (also being non-active pixel region), and according to the display voltage of the drain electrode end of thin film transistor (TFT) in this second pixel, (N is a positive integer in N frame time, for example be 2 frame) get the mean value of its positive polarity and reverse voltage, provide each first pixel of first pixel region to the display panel (also promptly initiatively pixel region) again to be used as common voltage.By this, can save not only that prior art is described must carry out complicated manual correction common voltage formality, can guarantee more that so the common voltage that provided is the required optimum voltage current potential of this row pixel in the display panel instantly.
In addition, if being produced circuit, above-mentioned common voltage is incorporated in second pixel region (also being non-active pixel region) when interior two second pixels are above, the RC that can significantly improve because of stray capacitance on the sweep trace and dead resistance postpones (RC delay), feed-trough voltage (the Δ V of the scanning voltage that causes D) drift.By this, can significantly promote GTG (gray level) accuracy of each first pixel of first pixel region in the display panel, and the flicker noise (flicker noise) that reduces display panel, the frame quality that display was presented promoted to reach.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the pixel structure figure of existing Thin Film Transistor-LCD.
Fig. 2 is another pixel structure figure of existing Thin Film Transistor-LCD.
Fig. 3 is the analog waveform figure of above-mentioned solution correlation technique 1.
Fig. 4 is above-mentioned solution correlation technique 2, and it adopts the analog waveform figure of the Driving technique of 3 rank scanning voltages.
Fig. 5 is the calcspar according to the described display of preferred embodiment of the present invention.
Fig. 6 is the pixel structure figure of present embodiment second pixel.
Fig. 7 produces the circuit diagram of circuit for the present embodiment common voltage.
Fig. 8 produces the sequential chart of circuit inner control first～the 6th pairing control signal of switch for the present embodiment common voltage.
Fig. 9～Figure 13 is the calcspar according to the display of another embodiment of the present invention.
Embodiment
Fig. 5 is the calcspar according to the described display 500 of preferred embodiment of the present invention.Please refer to Fig. 5, display 500 (for example can be LCD) comprises display panel (for example can be display panels) 501, gate drivers (gate driver) 503, and source electrode driver (source driver) 505.In present embodiment, display panel 501 comprises first pixel region 507, second pixel region 509, and common voltage produces circuit 511.Wherein, first pixel region 507 has a plurality of first pixels (not illustrating), arranges (i, j are positive integer) with the i*j array way and comes in order to show image.Second pixel region 509 has a plurality of second pixel 509a, and it is configured in the periphery of first pixel region 507.
Common voltage produces circuit 511 can electrically connect one second pixel 509a in second pixel region 509, and this second pixel 509a must corresponding first pixel region 507 in certain delegation (column) pixel wherein.In addition, common voltage produces the drain electrode end display voltage (V of circuit 511 meetings according to thin film transistor (TFT) (not illustrating) in the second pixel 509a that is electrically connected D), and each first pixel in common voltage (common voltage) Vcom to the first pixel region 507 is provided.Wherein, common voltage Vcom is that the display voltage of positive polarity (also is that display voltage is noble potential V DHThe time) (also display voltage is electronegative potential V with the display voltage of negative polarity DLThe time) mean value, also can be expressed as:
Vcom=(V DH+ V DL)/2 formula 4
In present embodiment, do not limit several second pixel 509a that common voltage generation circuit 511 electrically connects in second pixel region 509, but only be limited to the second pixel 509a that is electrically connected, it is necessary for the second pixel 509a that is configured in previous column (row) pixel of contiguous first pixel region 507 or next column pixel.For instance, if being i*j, the display panel resolution of present embodiment (for example is 1024*768, and i, j is a positive integer), then common voltage produces the second pixel 509a in circuit 511 electric connections second pixel region 509, will occur on the 0th row pixel (also promptly being close to second pixel region 509 of the 1st row pixel of first pixel region 507) or the 769th row pixel (also promptly being close to second pixel region 509 of the 768th row pixel of first pixel region 507), and with present embodiment, the second pixel 509a that one-row pixels in corresponding first pixel region 507, its position is approximately that regional location gets final product in the putting of first pixel region 507.
And what deserves to be mentioned is, with this field that the present invention belongs to have know usually the knowledgeable when can know above-mentioned first pixel region 507 serve as the active pixel region (active pixels region), and above-mentioned second pixel region 509 is dummy pixel areas (dummy pixels region), so as can be known be, the gate drivers 503 of present embodiment is given each first pixel of first pixel region 507 except scanning voltage (scan voltage) and data voltage (datavoltage) distinctly are provided with source electrode driver 505, pairing that row pixel to the second pixel 509a also need be provided, but because gate drivers 503 is not to be emphasis of the present invention with source electrode driver 505, and the drive principle of gate drivers 503 and source electrode driver 505 belongs to this invention field to be had and knows that usually the knowledgeable knows as can be known, so, also no longer given unnecessary details it at this in order not obscure spirit of the present invention.
Fig. 6 is the pixel structure figure of the present embodiment second pixel 509a.Fig. 7 produces the circuit diagram of circuit 511 for the present embodiment common voltage.Please merge with reference to Fig. 5～7, the pixel structure of the second pixel 509a that Fig. 6 illustrated is for adopting the pixel structure of memory capacitance Cs on common electrode (Cs on common), and common voltage (common voltage) Vcom that offers first pixel and the second pixel 509a is provided by the common voltage generation circuit 511 that Fig. 7 disclosed.
Please earlier with reference to Fig. 7, the common voltage of present embodiment produces circuit 511 and comprises operational amplifier 701,703 and 705, switch SW 1～SW6, and capacitor C 1～C3.Wherein, can find out by operational amplifier 701 that Fig. 7 disclosed and 703 electrical connection, it is to be used as single gain amplifier (unit gain buffer), in order to increase the driving force of the voltage that is received, drive capacitor C 1, C2 respectively, and the peak sensing device of being formed by operational amplifier 705 and capacitor C 3 (peak detector).In addition, switch SW 1～SW6 all has a control end, in order to the control signal C according to correspondence S1～C S6, and determine whether conducting.
Fig. 8 produces the pairing control signal C of circuit 511 inner control switch SW, 1～SW6 for the present embodiment common voltage S1～C S6Sequential chart.Please merge with reference to Fig. 5～8, can find out, as control signal C by the sequential chart that Fig. 8 disclosed S1～C S6When noble potential (high pulse) occurring, the corresponding conducting of switch SW 1～SW6 meeting is so when sequential t1 (also being that common voltage generation circuit 511 is in original state), so the neither conducting of switch SW 1～SW6 is node voltage Va=Vb=Vc=0V; And at sequential t2, and the drain electrode end display voltage V of the interior thin film transistor (TFT) of second pixel 509a this moment DFor noble potential (also is V DH) time, switch SW 1,2 and 5 can conductings, and switch SW 3,4 and 6 not conductings, and switch SW 1 and SW2 can see through operational amplifier 701 and receive positive noble potential display voltage V DHSo, node voltage Va=Vb=V DH, and node voltage Vc=0V.
Then, when sequential t3, the neither conducting of switch SW 1～SW6, so as can be known be that node voltage Va, Vb and Vc are in suspension joint (floating) state, so it is constant that the voltage difference between node voltage Va, Vb and Vc are relative is kept, so but inference is learnt node voltage Va=Vb, and node voltage Va-Vc=V DHAfterwards, when sequential t4, switch SW 4 meeting conductings, and rest switch SW1～SW3, SW5 and not conducting of SW6, so what can know by inference is that this moment, node voltage Vb and Vc were in floating, so can learn node voltage Va=Vb=0V according to the charge conservation theory, and node voltage Vc=-V DH
In addition, at sequential t5, and the drain electrode end display voltage V of the interior thin film transistor (TFT) of second pixel 509a this moment DFor electronegative potential (also is V DL) time, switch SW 3 and switch SW 4 can conductings, and switch SW 1,2,5 and 6 not conductings, so the time node voltage Va=0V, and because capacitor C 1, C2 voltage divider principle, node voltage Vb will be pulled up to [(V by 0V DH+ V DL)/2] V.In addition, node voltage Vc can be by negative noble potential display voltage-V DHBe pulled up to positive electronegative potential display voltage V DLAt last, when sequential t6, switch SW 4 and 6 meeting conductings, and switch SW 1,2,3 and 5 not conductings, so the time node voltage Vb can see through operational amplifier 703, and the peak sensing device of being formed to by operational amplifier 705 and capacitor C 3 is provided, to export each first pixel in more stable voltage to the first pixel region 507, be used as the required common voltage Vcom of each first pixel in first pixel region 507.
And it should be noted that, its value of input capacitance (inputcapacitance) in the operational amplifier 701 of present embodiment and 703 is the smaller the better, and the capacitance of capacitor C 1 and C2 must be identical and its capacitance is big more, so can reduce the error amount of the above-mentioned common voltage Vcom that calculates.
And what deserves to be mentioned is, can find out from the sequential chart that Fig. 8 disclosed, the common voltage of present embodiment produces circuit 511 and needs the common voltage Vcom that cost 2 frame (frame) times are exported to calculate it, also promptly can find out from the sequential of sweep signal (scan signal) GS.Wherein, in first frame time, common voltage produces the display voltage V of circuit 511 memory noble potentials DH, and in second frame time, common voltage produces the display voltage V of circuit 511 memory electronegative potentials DLSo at the switching sequence that sees through control signal CS gauge tap SW1～SW6, can obtain node voltage Vb and each first pixel to first pixel region 507 is provided, to be used as the required common voltage Vcom of each first pixel in first pixel region 507.
The principle of work that is produced circuit 511 by the described common voltage of the foregoing description can find out that it is that two voltage signals of being imported are got its average voltage level in different time, also promptly get its noble potential display voltage V DHWith electronegative potential display voltage V DLAverage voltage, so produce the spirit of circuit 511 according to common voltage of the present invention, the common voltage of present embodiment produces circuit 511 can be used in different time, and gets in the correlative technology field of its average voltage.
In present embodiment, produce the required common voltage Vcom of this row pixel in the pairing display panel 501 of circuit 511 calculating because adopt second pixel (also being dummy pixel areas) 509a to be used as common voltage, so according to as can be known above-mentioned, pairing that row pixel of the second pixel 509a, gate drivers 503 need provide scanning voltage to enable this row pixel, and the data voltage that its source electrode driver 505 is provided, must be according to the type of drive of display panel 501, also be normal whitening (normally white) or normal apparent black (normally black), and provide correct data voltage (also being white signal or black signal) to give this row pixel accordingly, and its GTG of the data voltage that is provided (gray level) must be identical.
For instance, when the type of drive of display panel 501 was normal whitening, source electrode driver 505 provided to the data voltage of pairing this row pixel of the second pixel 509a, just must provide white signal; Otherwise, when the type of drive of display panel 501 is that source electrode driver 505 provides to the data voltage of pairing this row pixel of the second pixel 509a, just must provide black signal when normally showing black.By this, after using common voltage of the present invention to produce circuit 511, should be noted that, display panel 501 is not originally used pairing this row pixel of the second pixel 509a, must consider the data voltage state that scanning voltage state that its gate drivers 503 is exported and source electrode driver 505 are exported yet.
And it will be further appreciated that, the common voltage of present embodiment produces circuit 511 because adopt the second pixel 509a to calculate the required common voltage Vcom of this row pixel in the pairing display panel 501, event is confirmable to be, this row pixel can suppress fully prior art mentioned it, display panel 501 interscan lines postpone (RC delay) influence, feed-trough voltage (the Δ V of the scanning voltage that causes because of the RC of stray capacitance and dead resistance D) problem, and then cause the generation of the flicker noise (flicker noise) of display panel 501.
In addition, in present embodiment, the second pixel 509a the first contiguous pixel of these row pixels in the corresponding display panel 501, it also can be reduced by sweep trace RC delayed impact, but first pixel away from display panel 501 middle positions, it may still can be promoted by sweep trace RC delayed impact, so also might produce the flicker noise in two sides, first pixel of display panel 501.
And be stressed that in above-mentioned present embodiment, though two sides, first pixel of its display panel 501 may still have the flicker noise, but in display panel 501 flicker noises contiguous or pairing first pixel of the second pixel 509a itself is can be repressed, and what deserves to be mentioned is, present embodiment provides to the common voltage Vcom of display panel 501 interior each first pixel, it is to produce circuit 511 dynamic auto generations by common voltage, not needing is provided by the outside, and so that liquid crystal capacitance C LCKeep stable with the cross-pressure that memory capacitance Cs goes up, and then effectively promote GTG (gray level) accuracy of each first pixel in first pixel region 507, so can solve and existingly must carry out complicated manual correction common voltage Vcom formality, just can obtain the required best common voltage Vcom of first pixel in the display panel 501.
It is example that the foregoing description has been stated common voltage generation circuit 511 electric connections second pixel region 509 interior one second pixel 509a clearly, after this embodiment gives an example, the common voltage of below will giving an example again produces the embodiment that circuit 511 electrically connects a plurality of second pixel 509a in second pixel region 509, further solves the flicker noise of two sides, first pixel of display panel 501.
Fig. 9 is the calcspar according to the display 900 of another embodiment of the present invention.Please merge with reference to Fig. 5 and Fig. 9, the display 900 that Fig. 9 disclosed is with the maximum difference of display 500, it is to electrically connect second pixel region, 509 interior 4 second pixel 509a that common voltage produces circuit 511, the previous column pixel of 2 second adjacent first pixel regions 507 of pixel 509a and disposing wherein, the next column pixel of then adjacent first pixel region 507 of all the other 2 second pixel 509a and disposing, its allocation position is as position that Fig. 9 illustrated, but do not limit its position at this, the deviser can be according to the state of display panel 501 instantly, and its allocation position of in good time change.
In present embodiment, display panel 501 is used the principle of work of voltage generation circuit 511 together, and the display 500 of itself and a last embodiment is similar, so at this and no longer given unnecessary details.And what deserves to be mentioned is, the common voltage of present embodiment produces circuit 511 because of electrically connecting second pixel region, 509 interior 4 second pixel 509a, so expected is that the flicker noise of display panel 501 will be suppressed greatly, so the display quality that display 900 is presented also can promote.
Figure 10 is the calcspar according to the display 1000 of another embodiment of the present invention.Please refer to Figure 10, the display 1000 that Figure 10 disclosed, its common voltage produces circuit 511 and electrically connects second pixel region, 509 interior 10 second pixel 509a, the previous column pixel of 5 second adjacent first pixel regions 507 of pixel 509a and disposing wherein, the next column pixel of then adjacent first pixel region 507 of all the other 5 second pixel 509a and disposing, its allocation position is as position that Figure 10 illustrated, but do not limit its position at this, the deviser can be according to the state of display panel 501 instantly, and its allocation position of in good time change.
In present embodiment, display panel 501 is used the principle of work of voltage generation circuit 511 together, and the display 500 of itself and a last embodiment is similar, so at this and no longer given unnecessary details.The common voltage of present embodiment produces circuit 511 because of electrically connecting second pixel region, 509 interior 10 second pixel 509a, event is expected to be, the flicker noise of display panel 501 will more can be suppressed greatly, so the display quality that display 1000 is presented also can be better than the display quality that display 500 and display 900 are presented.
So as can be known according to the foregoing description, when common voltage produces number that circuit 511 is electrically connected to the second pixel 509a second pixel region 509 in more for a long time, its applied display panel can suppress feed-trough voltage (the Δ V of scanning voltage on the sweep trace that its sweep trace RC delay caused D) problem of drift, and then suppress the flicker noise of display panel 501, to promote the display quality of display.
In addition, spirit according to the invention described above embodiment, below again for its three embodiment, it is with the mask that opens the light on the colored filter (color filter) again, display panel is divided into a plurality of zones, using the common voltage of the invention described above to produce circuit 511 by this again provides each regional interior pixel required common voltage, the same described effect of the foregoing description that also can reach.
Figure 11 is the calcspar of the display 1100 of another embodiment of the present invention.Please refer to Figure 11, display 1100 is divided 3 zones with photomask at colored filter (not illustrating), also is about to display panel 501 and is divided into 3 zones, and it is regional A, area B and zone C.Wherein, zone A, B and C respectively have the second corresponding pixel 509a and its common voltage produces the utility voltage Vcom that circuit 511 is provided, so it is described according to the foregoing description, the principle of work of its display 1100 and display 500 are similar, so also no longer given unnecessary details, so feed-trough voltage (Δ V of scanning voltage on the sweep trace that the sweep trace RC of regional A, B and C postpones to be caused at this D) problem of drift can solve, and then more can suppress the flicker noise of display panel 501, to promote the display quality of display 1100.
Figure 12, Figure 13 are the calcspar of the display 1200,1300 of another embodiment of the present invention.Please merge with reference to Figure 11～13, display 1200 is similar with display 1100 with display 1300, only difference is in display 1200 for divide 5 zones on colored filter, and display 1300 is to divide 10 zones on colored filter, so the display panel of display 1200 can be divided into 5 regional A～E, and the display panel of display 1300 can be divided into 10 regional A～J.So what well imagine is, when multizone is got in division on colored filter, its display panel also can be divided into multizone more, then adding common voltage generation circuit 511 of the present invention provides its each zone required common voltage Vcom, so can solve the flicker noise of display panel fully, to promote the display quality of display.
In sum, the present invention provides a kind of display and display panel thereof.According to spirit of the present invention, have the following points advantage and narrate:
1. produce circuit according at least one second pixel in second pixel region by common voltage, and in N frame (N is a positive integer, for example being 2 frame) time adjusts the common voltage of the one-row pixels in the corresponding display panel of this pixel automatically, can save by this that prior art is described must carry out complicated manual correction common voltage formality, can guarantee more that so the common voltage that provided is the required optimum voltage current potential of this row pixel in the display panel instantly.
2. can divide a plurality of zones at colored filter by photomask,, improve feed-trough voltage (the Δ V of scanning voltage on the sweep trace that sweep trace RC postpones to be caused by this display panel is divided into a plurality of zones D) problem of drift, and then more can suppress the flicker noise of display panel, to promote the display quality of display.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.

Claims (20)

1. display panel comprises:
One first pixel region has a plurality of first pixels, arranges with array way;
One second pixel region has a plurality of second pixels, is configured in the previous column of this first pixel region of next-door neighbour, next column or previous column and next column pixel part; And
Uses voltage generation circuit altogether, electrically connect at least one second pixel, and each second pixel is to wherein one-row pixels in should first pixel region,
Wherein, this common voltage produces the display voltage of circuit according to this second pixel, and electricity consumption is depressed into those all first pixels and provide altogether, and this common voltage is the mean value of this display voltage of this display voltage of positive polarity and negative polarity.
2. display panel as claimed in claim 1 is characterized in that, each those first and second pixel comprises:
One transistor, its gate terminal electrically connects the one scan line, and the first leakage/source terminal then electrically connects a data line; And
One memory capacitance has one first end and one second end, and wherein this first end electrically connects the transistorized second leakage/source terminal, and this second end is then in order to receive this common voltage.
3. display panel as claimed in claim 2 is characterized in that this transistor comprises a thin film transistor (TFT).
4. display panel as claimed in claim 2 is characterized in that, each those first and second pixel also comprises:
One stray capacitance has one first end and one second end, and wherein this first end electrically connects this sweep trace, and this second end then electrically connects the transistorized second leakage/source terminal; And
One liquid crystal capacitance has one first end and one second end, and wherein this first end electrically connects the transistorized second leakage/source terminal, and this second end is then in order to receive this common voltage.
5. display panel as claimed in claim 4 is characterized in that, this common voltage produces circuit and comprises:
One first operational amplifier, have a positive input terminal, a negative input end and an output terminal, wherein this positive input terminal of this first operational amplifier electrically connects the transistorized second leakage/source terminal, and this negative input end of this first operational amplifier and this output terminal of this first operational amplifier then are electrically connected to each other together;
One first switch has one first end, one second end and a control end, and wherein this first end of this first switch electrically connects this output terminal of this first operational amplifier;
One second switch has one first end, one second end and a control end, and wherein this of this second switch first end electrically connects this first end of this first switch;
One the 3rd switch has one first end, one second end and a control end, and wherein this first end of the 3rd switch electrically connects this first end of this second switch;
One the 4th switch has one first end, one second end and a control end, and wherein this first end of the 4th switch electrically connects this second end of this first switch, and this second end of the 4th switch is ground connection then;
One first electric capacity has one first end and one second end, and wherein this first end of this first electric capacity electrically connects this second end of this first switch, and this second end of this first electric capacity then electrically connects this second end of this second switch;
One second electric capacity has one first end and one second end, and wherein this first end of this second electric capacity electrically connects this second end of this second switch, and this second end of this second electric capacity then electrically connects this second end of the 3rd switch;
One the 5th switch has one first end, one second end and a control end, and wherein this first end of the 5th switch electrically connects this second end of the 3rd switch, and this second end of the 5th switch is ground connection then;
One second operational amplifier, have a positive input terminal, a negative input end and an output terminal, wherein this positive input terminal of this second operational amplifier electrically connects this second end of this second switch, and this negative input end of this second operational amplifier and this output terminal of this second operational amplifier then are electrically connected to each other together;
One the 6th switch has one first end, one second end and a control end, and wherein this first end of the 6th switch electrically connects this output terminal of this second operational amplifier;
One the 3rd electric capacity has one first end and one second end, and wherein this first end of the 3rd electric capacity electrically connects this second end of the 6th switch, and this second end of the 3rd electric capacity is ground connection then; And
One the 3rd operational amplifier, have a positive input terminal, a negative input end and an output terminal, wherein this positive input terminal of the 3rd operational amplifier electrically connects this first end of the 3rd electric capacity, after this negative input end of the 3rd operational amplifier and this output terminal of the 3rd operational amplifier then are electrically connected to each other together, to export this common voltage
Wherein, this control end of this first, second, third, fourth, the 5th and the 6th switch in order to accordingly according to a control signal, to determine the whether conducting of this first, second, third, fourth, the 5th and the 6th switch.
6. display panel as claimed in claim 5, it is characterized in that, when this control signal during in a phase one, this the first, second, third, fourth, the 5th and the 6th not conducting of open relation, and when this control signal during in a subordinate phase, this first, second and the 5th switch conduction, and the 3rd, the 4th and the 6th not conducting of open relation.
7. display panel as claimed in claim 5, it is characterized in that, when this control signal during in a phase III, this the first, second, third, fourth, the 5th and the 6th not conducting of open relation, and when this control signal during in a quadravalence section, the 4th switch conduction, and this first, second, third, the 5th and the 6th not conducting of open relation.
8. display panel as claimed in claim 5, it is characterized in that, when this control signal during in a five-stage, the the 3rd and the 4th switch conduction, and this first, second, the 5th and the 6th not conducting of open relation, and when this control signal during in one the 6th stage, the 4th and the 6th switch conduction, and this first, second, third and the 5th not conducting of open relation.
9. display panel as claimed in claim 1 is characterized in that this display panel comprises a display panels.
10. display comprises:
One display panel comprises:
One first pixel region has a plurality of first pixels, arranges with array way;
One second pixel region has a plurality of second pixels, is configured in the previous column of this first pixel region of next-door neighbour, next column or previous column and next column pixel part; And
Use voltage generation circuit altogether, electrically connect at least one second pixel, and each second pixel is to one of them row pixel in should first pixel region; And
One gate drivers, electrically connect this display panel, this gate drivers has many gate wirings, in order to foundation one basic sequential, and in regular turn to those first pixels and those the second pixel pairing one scan line of each those gate wirings output scan voltage to correspondence
Wherein, this common voltage produces the display voltage of circuit according to this second pixel, and electricity consumption is depressed into those all first pixels and provide altogether, and this common voltage is the mean value of this display voltage of this display voltage of positive polarity and negative polarity.
11. display as claimed in claim 10, it is characterized in that, also comprise the one source pole driver, electrically connect this display panel, this source electrode driver has many source electrode distributions, in order to foundation one image data, and utilize those source electrode distributions to export this display voltage to the corresponding pairing data line of those first pixels.
12. display as claimed in claim 11, wherein each those first and second pixel comprises:
One transistor, its gate terminal electrically connects this sweep trace, this data line of electric connection that the first leakage/source terminal is then corresponding; And
One memory capacitance has one first end and one second end, and wherein this first end electrically connects the transistorized second leakage/source terminal, and this second end is then in order to receive this common voltage.
13. display as claimed in claim 12, wherein this transistor comprises a thin film transistor (TFT).
14. display as claimed in claim 12, wherein each those first and second pixel also comprises:
One stray capacitance has one first end and one second end, and wherein this first end electrically connects above-mentioned this sweep trace, and this second end then electrically connects the transistorized second leakage/source terminal; And
One liquid crystal capacitance has one first end and one second end, and wherein this first end electrically connects the transistorized second leakage/source terminal, and this second end is then in order to receive this common voltage.
15. display as claimed in claim 14, wherein this common voltage generation circuit comprises:
One first operational amplifier, have a positive input terminal, a negative input end and an output terminal, wherein this positive input terminal of this first operational amplifier electrically connects the transistorized second leakage/source terminal, and this negative input end of this first operational amplifier and this output terminal of this first operational amplifier then are electrically connected to each other together;
One first switch has one first end, one second end and a control end, and wherein this first end of this first switch electrically connects this output terminal of this first operational amplifier;
One second switch has one first end, one second end and a control end, and wherein this of this second switch first end electrically connects this first end of this first switch;
One the 3rd switch has one first end, one second end and a control end, and wherein this first end of the 3rd switch electrically connects this first end of this second switch;
One the 4th switch has one first end, one second end and a control end, and wherein this first end of the 4th switch electrically connects this second end of this first switch, and this second end of the 4th switch is ground connection then;
One first electric capacity has one first end and one second end, and wherein this first end of this first electric capacity electrically connects this second end of this first switch, and this second end of this first electric capacity then electrically connects this second end of this second switch;
One second electric capacity has one first end and one second end, and wherein this first end of this second electric capacity electrically connects this second end of this second switch, and this second end of this second electric capacity then electrically connects this second end of the 3rd switch;
One the 5th switch has one first end, one second end and a control end, and wherein this first end of the 5th switch electrically connects this second end of the 3rd switch, and this second end of the 5th switch is ground connection then;
One second operational amplifier, have a positive input terminal, a negative input end and an output terminal, wherein this positive input terminal of this second operational amplifier electrically connects this second end of this second switch, and this negative input end of this second operational amplifier and this output terminal of this second operational amplifier then are electrically connected to each other together;
One the 6th switch has one first end, one second end and a control end, and wherein this first end of the 6th switch electrically connects this output terminal of this second operational amplifier;
One the 3rd electric capacity has one first end and one second end, and wherein this first end of the 3rd electric capacity electrically connects this second end of this 6th switch, and this second end of the 3rd electric capacity is ground connection then; And
One the 3rd operational amplifier, have a positive input terminal, a negative input end and an output terminal, wherein this positive input terminal of the 3rd operational amplifier electrically connects this first end of the 3rd electric capacity, after this negative input end of the 3rd operational amplifier and this output terminal of the 3rd operational amplifier then are electrically connected to each other together, to export this common voltage
Wherein, this control end of this first, second, third, fourth, the 5th and the 6th switch in order to accordingly according to a control signal, to determine the whether conducting of this first, second, third, fourth, the 5th and the 6th switch.
16. display as claimed in claim 15, wherein when this control signal during in a phase one, this the first, second, third, fourth, the 5th and the 6th not conducting of open relation, and when this control signal during in a subordinate phase, this first, second and the 5th switch conduction, and the 3rd, the 4th and the 6th not conducting of open relation.
17. display as claimed in claim 15, wherein when this control signal during in a phase III, this the first, second, third, fourth, the 5th and the 6th not conducting of open relation, and when this control signal during in a quadravalence section, the 4th switch conduction, and this first, second, third, the 5th and the 6th not conducting of open relation.
18. display panel as claimed in claim 15, wherein when this control signal during in a five-stage, the the 3rd and the 4th switch conduction, and this first, second, the 5th and the 6th not conducting of open relation, and when this control signal during in one the 6th stage, the the 4th and the 6th switch conduction, and this first, second, third and the 5th not conducting of open relation.
19. display as claimed in claim 10, wherein this display panel comprises a display panels.
20. display as claimed in claim 10, wherein this display comprises a LCD.
CN2006101639484A 2006-11-29 2006-11-29 LCD display device and its display panel Expired - Fee Related CN101191925B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2006101639484A CN101191925B (en) 2006-11-29 2006-11-29 LCD display device and its display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2006101639484A CN101191925B (en) 2006-11-29 2006-11-29 LCD display device and its display panel

Publications (2)

Publication Number Publication Date
CN101191925A CN101191925A (en) 2008-06-04
CN101191925B true CN101191925B (en) 2010-08-11

Family

ID=39487007

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2006101639484A Expired - Fee Related CN101191925B (en) 2006-11-29 2006-11-29 LCD display device and its display panel

Country Status (1)

Country Link
CN (1) CN101191925B (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635133B (en) * 2008-07-21 2013-10-16 群创光电股份有限公司 Liquid crystal display device and pixel driving method
JP5290307B2 (en) * 2008-09-24 2013-09-18 シャープ株式会社 Liquid crystal display device, active matrix substrate, electronic equipment
CN101587700B (en) * 2009-06-26 2011-11-09 友达光电股份有限公司 Liquid crystal display and method for driving same
TWI425493B (en) * 2010-12-28 2014-02-01 Au Optronics Corp Flat panel display device and operating voltage adjusting method thereof
TWI415100B (en) * 2010-12-30 2013-11-11 Au Optronics Corp Lcd panel for compensating the feed-through voltage
CN102097061B (en) * 2011-02-24 2013-08-07 华映视讯（吴江）有限公司 Method for driving electrophoretic display and measuring feed-through voltages
CN102157138B (en) * 2011-04-14 2013-01-02 深圳市华星光电技术有限公司 Liquid crystal display and driving method thereof
TWI448885B (en) * 2011-12-13 2014-08-11 Au Optronics Corp Common voltage supply circuit of display, method of supplying common voltage and liquied crystal display thereof
CN102608817B (en) * 2012-03-26 2015-07-01 深圳市华星光电技术有限公司 Liquid crystal display (LCD) device
CN102610205A (en) * 2012-03-29 2012-07-25 深圳市华星光电技术有限公司 Feed-through voltage compensation circuit, liquid crystal display device and feed-through voltage compensation method
TWI443626B (en) * 2012-04-12 2014-07-01 Au Optronics Corp Common voltage supply circuit of display
CN103295540B (en) * 2012-06-07 2015-06-10 上海天马微电子有限公司 Driving method, driving device and display for active matrix display panel
CN104376823B (en) * 2014-09-30 2017-03-29 南京中电熊猫液晶显示科技有限公司 Gamma electric voltage adjusting means and method
TWI550591B (en) * 2015-06-04 2016-09-21 友達光電股份有限公司 Display device and method thereof
CN104932165B (en) * 2015-07-20 2018-05-25 深圳市华星光电技术有限公司 A kind of liquid crystal panel and voltage adjusting method
CN108510941A (en) * 2017-02-24 2018-09-07 昆山国显光电有限公司 A kind of driving method and display panel of display panel
CN107610646B (en) 2017-10-31 2019-07-26 云谷（固安）科技有限公司 A kind of display screen, image element driving method and display device
CN109192170B (en) * 2018-10-23 2021-07-06 惠科股份有限公司 Feed-through compensation method and device of display panel and display device
CN111402830A (en) * 2020-04-20 2020-07-10 合肥京东方显示技术有限公司 Circuit board for signal transmission, display device and driving method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1253303A (en) * 1998-11-06 2000-05-17 三星电子株式会社 Liquid crystal displayer having different common voltage
CN1527271A (en) * 2003-03-03 2004-09-08 ��ʽ����������ʾ�� Image display device
CN1573898A (en) * 2003-06-05 2005-02-02 株式会社瑞萨科技 Liquid crystal drive method, liquid crystal display system and liquid crystal drive control device
US6989808B2 (en) * 1998-12-28 2006-01-24 Fujitsu Display Technologies Corporation Driving of a liquid crystal display device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1253303A (en) * 1998-11-06 2000-05-17 三星电子株式会社 Liquid crystal displayer having different common voltage
US6989808B2 (en) * 1998-12-28 2006-01-24 Fujitsu Display Technologies Corporation Driving of a liquid crystal display device
CN1527271A (en) * 2003-03-03 2004-09-08 ��ʽ����������ʾ�� Image display device
CN1573898A (en) * 2003-06-05 2005-02-02 株式会社瑞萨科技 Liquid crystal drive method, liquid crystal display system and liquid crystal drive control device

Also Published As

Publication number Publication date
CN101191925A (en) 2008-06-04

Similar Documents

Publication Publication Date Title
CN101191925B (en) LCD display device and its display panel
TWI473066B (en) Display panel and its drive circuit
KR100323117B1 (en) Driving circuit and liquid crystal display of liquid crystal display
CN109491158B (en) Display panel and display device
KR101318043B1 (en) Liquid Crystal Display And Driving Method Thereof
US8310470B2 (en) Display apparatus and electronic equipment
US8089435B2 (en) Liquid crystal display and display panel thereof
CN100476557C (en) Liquid crystal panel, liquid crystal display device having the same and method for driving the same
CN100460939C (en) Crystal-liquid display device and its pulse-wave adjusting circuit
US20090096735A1 (en) Liquid crystal display having compensation circuit for reducing gate delay
KR20050054215A (en) The liquid crystal display device
US9230497B2 (en) Display device having each pixel divided into sub pixels for improved view angle characteristic
US8665196B2 (en) Display apparatus and display method
CN100504557C (en) LCD structure
US8169392B2 (en) Liquid crystal display with low flicker and driving method thereof
KR20150071360A (en) Liquid Crystal Display
CN101281330B (en) LCD and display panel thereof
KR20030084301A (en) A liquid crystal display for compensating for kickback voltage
JP3366437B2 (en) Driving method of liquid crystal display device
CN101727854B (en) Output stage circuit, grid electrode drive module and control method of scanning line
CN102568419A (en) Driver circuit
US8878832B2 (en) Pixel circuit, display device, and method for driving display device
CN113870806A (en) Compensation system and method for dual gate display
JP3587829B2 (en) Liquid crystal display device and driving method thereof
CN102436788B (en) Grid driving module and control method of scan line

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100811

Termination date: 20191129

CF01 Termination of patent right due to non-payment of annual fee