CN101191818A - Chip test method, system and apparatus - Google Patents
Chip test method, system and apparatus Download PDFInfo
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- CN101191818A CN101191818A CNA2007101793231A CN200710179323A CN101191818A CN 101191818 A CN101191818 A CN 101191818A CN A2007101793231 A CNA2007101793231 A CN A2007101793231A CN 200710179323 A CN200710179323 A CN 200710179323A CN 101191818 A CN101191818 A CN 101191818A
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Abstract
The invention discloses a method for testing chips which comprises the following steps of: preestimating the possible errors in a functional module to be tested of a chip to be tested; setting the test logic for testing the errors and arranging the test logic in a test device arranged outside the chip to be tested. The method also comprises the following steps that: the test device is used to test the functional module by means of the test logic and converts the test result into one of the two states which respectively indicate that errors exist in the functional module and that errors do not exist in the functional module. The invention also discloses a chip testing system and the test device. With the invention, the test logic can be changed according to new test proposal, thereby increasing the test speed.
Description
Technical field
The present invention relates to measuring technology, particularly a kind of method of chip testing, system and a kind of testing apparatus.
Background technology
At present, the validation test of chip and debugging occupy the time more than 70% in the whole performance history of chip.Generally, the test of chip mainly contains two kinds of methods.First kind is software test, promptly by the various test and excitations of computer programming generation at chip to be measured.Like this, can compare by various test and excitations result who produces and the result that expectation chip to be measured produces, and then verify the function of chip to be measured.Second kind is hardware testing, promptly is similar to the actual working environment of chip to be measured by building hardware test platform.Like this, can be more the function of real proofing chip.Adopt second method validation test chip to be measured to be described to prior art below.
Referring to Fig. 1, Fig. 1 is the structure composition diagram of test chip to be measured in the prior art.As shown in Figure 1, this structure mainly comprises: chip 101 to be measured, aided verification daughter board 102 and signal analyzer 103.
Wherein, chip 101 to be measured mainly comprises functional module 1011, test port 1012 and the function port one 013 of desire test.Generally, the functional module 1011 that has a desire test on the chip 101 to be measured at least.Simple for narrating, suppose that the number of the functional module 1011 of desire test is one.In Fig. 1,1014 pairs of chips 101 to be measured of test module are tested just the functional module 1011 of the test of the desire on the chip 101 to be measured are tested.Under some exceptions, the signal more complicated that the functional module 1011 of desire test produces, only confirm with the observation from signal analyzer 103 very intuitive and convenient ground whether it produces mistake, this just need analyze the signal that the functional module 1011 of desire test produces at chip 101 inner some extra test logics that increase to be measured, will send to signal analyzer 103 by the signal that being easy to behind the aforementioned test logic observed and analyzed again.Like this, chip internal to be measured also should comprise test module 1014.
Generally, test module 1014 can not be tested the functional module 1011 on the chip 101 to be measured separately, and this just needs, and aided verification daughter board 102 is auxiliary finishes test.
Aided verification daughter board 102 is connected to the functional module 1011 of assisting desire to test on the functional module 1011 of desire test and carries out its corresponding functions by function port one 013.The function that the functional module 1011 of 1014 pairs of desire tests of test module is carried out is tested, and the signal of test is connected on the signal analyzer 103 by test port 1012.
Generally, signal analyzer 103 can be oscillograph, also can be logic analyser.Signal analyzer 103 is used to observe the test signal that produces with analytical test module 1014.There is not mistake in the time of like this, just can determining the functional module 1011 of desire test by the display result on the signal analyzer 103.And, when the functional module 1011 of desire test produces mistake, also can be by the demonstration of signal analyzer 103, the error reason that the functional module 1011 of derivation desire test produces, and the functional module 1011 of this desire test debugged, so that remove the mistake that the functional module 1011 of this desire test produces.
This shows, such scheme can be tested the functional module of chip internal desire test to be measured by the test module of chip internal to be measured, and the test signal that produces is observed and analyzed by logic analyser or oscillograph, and then the functional module of desire test debugged, root locates errors.But this mode need add logic module or the test module with functional test in chip, will increase area of chip like this, and test module at first needs to be fixed up when carrying out test function.Like this, no matter in the performance history of chip, or after the chip manufacturing, all can not revise test logic, thereby influence test speed according to new debugging scheme.
Summary of the invention
The embodiment of the invention provides a kind of method, system and equipment of chip testing, can revise test logic according to new debugging scheme, improves test speed.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of method of chip testing comprises the mistake that the desire test function module estimated on the chip to be measured can occur; The test logic of the described mistake of test is set, and described test logic is set in place in the testing apparatus of chip exterior to be measured; This method comprises:
Described testing apparatus is tested described functional module by described test logic;
The test result that obtains is converted to one of two opposite states, and described two opposite states indicate described functional module whether to have mistake respectively.
Preferably, this method further comprises: one of described state is shown by the LED display lamp or show by LCDs LCD.
Preferably, described one of state is shown as by the LED display lamp:
When there was mistake in the described functional module of one of described state indication, the LED display lamp was bright; Otherwise the LED display lamp goes out.
Preferably, this method further comprises: when there is mistake in the described functional module of one of described state indication, the described error functional module that exists is debugged.
A kind of system of chip testing comprises chip to be measured and testing apparatus; Wherein,
Described chip to be measured comprises desires the test function module;
Described testing apparatus, be provided with the test logic of desiring the test function module on the test for external chip to be measured, described test logic is used for the mistake that described functional module can occur is tested, and test result is converted to one of two opposite states, described two opposite states indicate described functional module whether to have mistake respectively.
Preferably, this system also comprises: display device, and wherein, described display device is arranged on the described testing apparatus, perhaps, is independent of described testing apparatus;
Described display device is used for one of described state is shown.
Preferably, this system also comprises:
Commissioning device is used for one of the state that shows at the described display device described functional module of indication and exists when wrong, and the described error functional module that exists is debugged.
A kind of testing apparatus comprises: receiving element and test cell; Wherein,
Described receiving element is used for the signal of desire test function module of the chip to be measured of acceptance test device external, and this signal is sent to test cell;
Described test cell, be used for described desire test function module being tested by the test logic that is arranged on himself, and test result is converted to one of two opposite states, described two opposite states indicate described functional module whether to have mistake respectively.
Preferably, this equipment also comprises: display unit;
Described display unit is used for one of described state is shown.
Preferably, described display unit is LED display lamp or LCDs LCD.
Preferably, described display unit is the LED display lamp, and when there was mistake in described LED display lamp in the described functional module of one of described state indication, lamp was bright; Otherwise lamp goes out.
Preferably, described test cell is realized by programmable logic device (PLD).
As seen from the above technical solutions, the method for this chip testing of the present invention, system and equipment have the following advantages:
First: among the present invention, testing apparatus can be by programmable logic device (PLD) such as on-site programmable gate array FPGA; Perhaps realize for complex programmable logic device (CPLD).Like this, can reduce the cost of proving installation, so that produce proving installation in batches.And this testing apparatus is arranged on the outside of chip to be measured, can be at any time according to debugging scheme modifying or increase and decrease test logic, thereby the test function of realization testing apparatus that can be convenient, flexible improves test speed.
Second: the present invention like this, can dispense the test module in the chip to be measured in the prior art by test logic being written in the testing apparatus that is arranged on chip exterior to be measured, reduces area of chip to be measured, and then reduces the cost of chipware.
The 3rd: the present invention can allow under the situation that does not have oscillograph or logic analyser chip to be measured to be tested, and has reduced and has tested the cost that chip to be measured spends.
Description of drawings
Fig. 1 is the structure composition diagram of test chip to be measured in the prior art;
The process flow diagram of the chip detecting method that Fig. 2 provides for the embodiment of the invention;
The chip test system figure that Fig. 3 provides for the embodiment of the invention;
The composition diagram of the testing apparatus that Fig. 4 provides for the embodiment of the invention;
Fig. 5 be in the embodiment of the invention testing apparatus at different wrong structural drawing.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Unlike the prior art be that the embodiment of the invention is to estimate the mistake that the desire test function module on the chip to be measured can occur earlier; The test logic of the described mistake of test is set, and described test logic is set in place in the testing apparatus of chip exterior to be measured.Like this, the method that the embodiment of the invention is tested chip to be measured is mainly: described testing apparatus is tested described functional module by described test logic; The test result that obtains is converted to one of two opposite states, and described two opposite states indicate described functional module whether to have mistake respectively, so that can revise test logic according to new debugging scheme, improve test speed.
Referring to Fig. 2, the process flow diagram of the chip detecting method that Fig. 2 provides for the embodiment of the invention.In Fig. 2, this flow process comprises:
In this step, the functional module of desire test can have a plurality of, and present embodiment is simple for describing, and supposes that the functional module of desire test is one.
Above-mentioned test port is used to connect the functional module and the testing apparatus of desire test, and the signal that the functional module that corresponding desire is tested produces sends to testing apparatus.
Testing apparatus in the present embodiment can be by realizations such as programmable logic device (PLD) such as FPGA, CPLD.And in this step, testing apparatus is tested the functional module of desire test and is specially: testing apparatus is not by putting the issuable mistake of functional module of the above-mentioned desire test of estimating of test logic test in himself.
If the mistake that the functional module of the above-mentioned desire test of estimating may occur is wrong A, then the test logic in the testing apparatus is the test logic of corresponding this mistake of test A in this step.That is, in this step, testing apparatus is tested the functional module of desire test by the test logic of the wrong A of correspondence.
In this step, two opposite states indicate described functional module whether to have mistake respectively.For the test logic of above-mentioned test errors A,, show that promptly wrong A has appearred in the functional module of desire test if the described functional module of one of two opposite states of test result conversion indication exists when wrong; Otherwise the functional module of desire test may not have mistake, and perhaps the mistake of Chu Xianing is not wrong A.
Afterwards, when wrong A occurring, can debug the functional module that has above-mentioned wrong A.
Generally, estimating the mistake that the functional module of desire test occurs may be for a plurality of.Like this, above-mentioned when the wrong A that remove to produce by debugging, can continue to carry out the operation that other mistakes of the functional module of desire test are tested.Certainly, also can to the institute of the functional module of desire test wrong test finish after, debug.
In the present embodiment, if the functional module of desire test is more than 1 in the chip to be measured, and each functional module all identical mistake may occur, then in order to improve test speed, a plurality of test logics of the same mistake of corresponding difference in functionality module respectively can be set simultaneously in testing apparatus also.Equally, in the present embodiment, if the issuable mistake of functional module of the desire of estimating test more than 1, then in order to improve test speed, also can be provided with corresponding respectively different wrong a plurality of test logics at this functional module simultaneously in testing apparatus.This just needs the concrete condition concrete analysis.
The user can find error source intuitively for convenience, and present embodiment can show one of above-mentioned state by light emitting diode (LED:Light-Emitting Diode) display lamp or by LCDs (LCD:Liquid Crystal Display).
If one of above-mentioned state is shown by the LED display lamp, then when there is mistake in the functional module of the above-mentioned desire test of one of described state indication, the LED display lamp is bright, then the user further can debug error functional module occurring, up to remove the mistake that produces by debugging, otherwise the LED display lamp goes out, and there is not the mistake of this test logic correspondence in the functional module of then definite above-mentioned desire test.
The system of the chip testing that the embodiment of the invention is provided is described below.
Referring to Fig. 3, the system diagram of the chip testing that Fig. 3 provides for the embodiment of the invention.As shown in Figure 3, this system mainly comprises: chip 301 to be measured and testing apparatus 302.
Wherein, chip 301 to be measured comprises desire test function module 3011.
In the application, chip 301 to be measured can also comprise the test port 3012 that is used to connect testing apparatus 302.
This system also comprises: display device 303.
Wherein, display device 303 is arranged on the testing apparatus 302, perhaps, is independent of testing apparatus 302; Supposition display device 303 is independent of testing apparatus 302 in the present embodiment.
This system can also comprise commissioning device 304.
Wherein, commissioning device 304 is used for debugging there being error functional module when test function module 3011 existence mistakes are desired in the indication of one of the state of above-mentioned display device demonstration.
In the present embodiment, testing apparatus 302 can be by realizations such as programmable logic device (PLD) such as FPGA, CPLD.
The structure composition diagram of testing apparatus 302 is referring to Fig. 4, the composition diagram of the testing apparatus that Fig. 4 provides for the embodiment of the invention.As shown in Figure 4, this equipment comprises: receiving element 401 and test cell 402.
Wherein, receiving element 401 is used for receiving the signal of the desire test function module of the chip to be measured that is arranged on the testing apparatus outside, and this signal is sent to test cell 402.
This equipment also comprises: display unit 403.
Wherein, display unit 403 is LED display lamp or LCD display;
In the present embodiment, display unit 403 adopts the LED display lamp.When there was mistake in one of above-mentioned state indication above-mentioned functions module, the LED display lamp was bright; Otherwise the LED display lamp goes out.
In the present embodiment, if the issuable mistake of functional module of the desire of estimating test more than 1, like this, is the raising test speed, also can be in testing apparatus at this functional module corresponding different wrong test logic subelement more than 1 be set simultaneously, concrete structure is referring to Fig. 5.
In addition, if the functional module of desire test is more than 1 in the chip to be measured, and each functional module all identical mistake may occur, then in order to improve test speed, a plurality of test logics of the same mistake of corresponding difference in functionality module respectively can be set simultaneously in testing apparatus also.
By the above embodiments as seen, this testing apparatus of the embodiment of the invention can be waited by programmable logic device (PLD) such as FPGA, CPLD and realize that like this, proving installation is with low cost, can produce in batches.And this testing apparatus is arranged on the outside of chip to be measured, can revise or increase and decrease test logic at any time as required, thereby the test function of testing apparatus that can convenient, flexible realization improves test speed.In addition, the embodiment of the invention is by being written to test logic in the testing apparatus that is arranged on chip exterior to be measured, like this, by testing apparatus being arranged on chip exterior to be measured, can remove the test module in the prior art chips, reduce area of chip to be measured, reduce the chipware cost.And the present invention can allow under the situation that does not have oscillograph or logic analyser chip to be measured to be tested, and has reduced the cost of testing chip to be measured.
Institute is understood that; the above is a better embodiment of the present invention only, and is not intended to limit the scope of the invention, and is within the spirit and principles in the present invention all; any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. the method for a chip testing is characterized in that, estimates the mistake that the desire test function module on the chip to be measured can occur; The test logic of the described mistake of test is set, and described test logic is set in place in the testing apparatus of chip exterior to be measured;
This method comprises:
Described testing apparatus is tested described functional module by described test logic;
The test result that obtains is converted to one of two opposite states, and described two opposite states indicate described functional module whether to have mistake respectively.
2. the method for claim 1 is characterized in that, this method further comprises: one of described state is shown by the LED display lamp or show by LCDs LCD.
3. method as claimed in claim 2 is characterized in that, described one of state is shown as by the LED display lamp:
When there was mistake in the described functional module of one of described state indication, the LED display lamp was bright; Otherwise the LED display lamp goes out.
4. as each described method among the claim 1-3, it is characterized in that this method further comprises: when there is mistake in the described functional module of one of described state indication, the described error functional module that exists is debugged.
5. the system of a chip testing is characterized in that, this system comprises chip to be measured and testing apparatus; Wherein,
Described chip to be measured comprises desires the test function module;
Described testing apparatus, be provided with the test logic of desiring the test function module on the test for external chip to be measured, described test logic is used for the mistake that described functional module can occur is tested, and test result is converted to one of two opposite states, described two opposite states indicate described functional module whether to have mistake respectively.
6. system as claimed in claim 5 is characterized in that, this system also comprises: display device, and wherein, described display device is arranged on the described testing apparatus, perhaps, is independent of described testing apparatus;
Described display device is used for one of described state is shown.
7. system as claimed in claim 6 is characterized in that, this system also comprises:
Commissioning device is used for one of the state that shows at the described display device described functional module of indication and exists when wrong, and the described error functional module that exists is debugged.
8. a testing apparatus is characterized in that, this equipment comprises: receiving element and test cell; Wherein,
Described receiving element is used for the signal of desire test function module of the chip to be measured of acceptance test device external, and this signal is sent to test cell;
Described test cell, be used for described desire test function module being tested by the test logic that is arranged on himself, and test result is converted to one of two opposite states, described two opposite states indicate described functional module whether to have mistake respectively.
9. equipment as claimed in claim 8 is characterized in that this equipment also comprises: display unit;
Described display unit is used for one of described state is shown.
10. equipment as claimed in claim 9 is characterized in that, described display unit is LED display lamp or LCDs LCD.
11. equipment as claimed in claim 9 is characterized in that, described display unit is the LED display lamp, and when there was mistake in described LED display lamp in the described functional module of one of described state indication, lamp was bright; Otherwise lamp goes out.
12. equipment as claimed in claim 8 is characterized in that, described test cell is realized by programmable logic device (PLD).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101793231A CN101191818A (en) | 2007-12-12 | 2007-12-12 | Chip test method, system and apparatus |
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| CNA2007101793231A CN101191818A (en) | 2007-12-12 | 2007-12-12 | Chip test method, system and apparatus |
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| CN101191818A true CN101191818A (en) | 2008-06-04 |
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| CNA2007101793231A Pending CN101191818A (en) | 2007-12-12 | 2007-12-12 | Chip test method, system and apparatus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645435A (en) * | 2013-12-13 | 2014-03-19 | 电子科技大学 | Software module testability design method of multi-signal model programming logic device |
| CN105629153A (en) * | 2015-12-24 | 2016-06-01 | 大唐微电子技术有限公司 | Chip testing method |
| CN114384400A (en) * | 2022-01-13 | 2022-04-22 | 集睿致远(厦门)科技有限公司 | Positioning system and positioning method for chip abnormal signals |
-
2007
- 2007-12-12 CN CNA2007101793231A patent/CN101191818A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103645435A (en) * | 2013-12-13 | 2014-03-19 | 电子科技大学 | Software module testability design method of multi-signal model programming logic device |
| CN103645435B (en) * | 2013-12-13 | 2016-03-23 | 电子科技大学 | The software module design for Measurability method of multi-signal model programmable logic device (PLD) |
| CN105629153A (en) * | 2015-12-24 | 2016-06-01 | 大唐微电子技术有限公司 | Chip testing method |
| CN105629153B (en) * | 2015-12-24 | 2018-10-09 | 大唐微电子技术有限公司 | A kind of method of chip testing |
| CN114384400A (en) * | 2022-01-13 | 2022-04-22 | 集睿致远(厦门)科技有限公司 | Positioning system and positioning method for chip abnormal signals |
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