CN101183871B - Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus - Google Patents
Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus Download PDFInfo
- Publication number
- CN101183871B CN101183871B CN2007101984807A CN200710198480A CN101183871B CN 101183871 B CN101183871 B CN 101183871B CN 2007101984807 A CN2007101984807 A CN 2007101984807A CN 200710198480 A CN200710198480 A CN 200710198480A CN 101183871 B CN101183871 B CN 101183871B
- Authority
- CN
- China
- Prior art keywords
- clock
- frequency
- phase
- frequency clock
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention provides an implementation method of transforming an input clock into a high frequency clock, comprising that an input clock is received; the jitter of the input clock is filtered out by using a first order phase locked loop to obtain a low-frequency clock; the low-frequency clock is transformed to a high-frequency clock by using a second order phase locked loop. The invention also provides a phase locked loop device. The phase locked loops both in transforming the input clock to the low-frequency clock and the low-frequency clock to the high-frequency clock are of high reliability, and also capable in accomplishment of transforming the input clock to the high-frequency clock. Therefore, the success rate of the clock transformation in the invention is higher than the prior technology.
Description
Technical field
The present invention relates to the communication technology, relate in particular to phase-locked loop (PLL, Phase Locked Loop) technology.
Background technology
Along with development of Communication Technique, people are more and more higher to the requirement of communication bandwidth, for this reason, the communications field is used and has been developed multiple high-speed interface, SDH (Synchronous Digital Hierarchy) (SDH for example, Synchronous DigitalHierarchy) framer, high speed serialization/separate serial (SERDES, Serializer/Deserializer) interface etc.Be to guarantee the performance of high-speed interface, the frequency of reference clock and performance all need the requirement that reaches certain, and the interface reference clock of hundreds of MHz has been the reference clock that is in daily use.Simultaneously, wireless communication technology develops into 3G from 2G, and progressively 3G evolution backward, and multi-transceiver technology is used widely, these all require the sample rate of modulus (AD)/digital-to-analogue (DA) more and more higher, AD/DA sampling performance is except outside the Pass having with self device technology, also with the jitter performance strong correlation of its reference clock.
At present, all use the reference clock benchmark of high frequency crystal oscillator in the application scenario of high-speed interface, that is, use the shake of high frequency crystal oscillator phase-locked loop filtering input clock, obtain high frequency clock as high-speed interface.But the inventor is through scrutinizing, finding after the serious analysis, high frequency crystal oscillator is limit owing to self technology, reliability is relatively poor relatively, will cause the reliability of high frequency crystal oscillator phase-locked loop relatively poor relatively like this, and then causes the chance of success of clock frequency conversion lower.
Concrete, as shown in Figure 1, high frequency VCXO (VCXO, Voltage Control CrystalOscillator) phase-locked loop 11 is converted to high frequency clock with the input clock that receives, and high frequency clock is as the reference clock of SDH framer 12.In actual applications, high frequency VCXO phase-locked loop 11 really can the filtering input clock shake, but high frequency VCXO phase-locked loop 11 comprises the high frequency VCXO, and the wafer of high frequency VCXO itself is thinner, for this reason, the failure rate of high frequency VCXO is higher, will directly cause the reliability of high frequency VCXO phase-locked loop 11 relatively poor like this.
Summary of the invention
The implementation method and the phase-locked loop apparatus that provide a kind of input clock to be converted to high frequency clock is provided the technical problem that the embodiment of the invention will solve, in order to improve the chance of success of clock frequency conversion.
For solving the problems of the technologies described above, the invention provides the implementation method embodiment that a kind of input clock is converted to high frequency clock, comprising: receive input clock; Use the shake of the described input clock of first order phase-locked loop filtering, obtain low-frequency clock;
Described first order phase-locked loop is a low frequency VCXO phase-locked loop;
The low-frequency clock that input clock and the low frequency VCXO in the low frequency VCXO phase-locked loop are exported carries out bit comparison mutually, produces the error voltage corresponding to phase difference between input clock and the low-frequency clock;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of low-frequency clock is controlled;
Use second level phase-locked loop that low-frequency clock is converted to high frequency clock.
The present invention also provides a kind of input clock to be converted to the implementation method embodiment of high frequency clock, comprising:
Receive input clock;
Use the shake of the described input clock of first order phase-locked loop filtering, obtain low-frequency clock, described first order phase-locked loop is a low frequency VCXO phase-locked loop;
Respectively the low-frequency clock of the low frequency VCXO in input clock and low frequency VCXO phase-locked loop output is carried out frequency division and handle, obtain input clock and low-frequency clock behind the frequency division;
Low-frequency clock behind input clock behind the described frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of the low-frequency clock of described output is controlled;
Use second level phase-locked loop that low-frequency clock is converted to high frequency clock.
The present invention also provides a kind of phase-locked loop apparatus embodiment, comprising: first order phase-locked loop, be used for the shake of the input clock that filtering receives, and obtain low-frequency clock; Second level phase-locked loop is used for described low-frequency clock is converted to high frequency clock;
Also comprise:
First phase discriminator is used for input clock is carried out bit comparison mutually with low-frequency clock, produces the error voltage corresponding to phase difference;
First loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
The first low frequency VCXO is used for the control voltage that obtains according to described loop filter, and the frequency of described low-frequency clock is controlled.
The present invention also provides a kind of phase-locked loop apparatus embodiment, comprising: first order phase-locked loop, be used for the shake of the input clock that filtering receives, and obtain low-frequency clock;
Second level phase-locked loop is used for low-frequency clock is converted to high frequency clock;
Also comprise:
First phase discriminator, being used for that input clock is carried out frequency division handles, obtain the input clock behind the frequency division, low-frequency clock to the output of low frequency VCXO carries out the frequency division processing, obtain the low-frequency clock behind the frequency division, low-frequency clock behind input clock behind the described frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
First loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
The first low frequency VCXO is used for the control voltage that obtains according to described loop filter, and the frequency of the low-frequency clock of output is controlled.
In an embodiment of the present invention, with the shake of a phase-locked loop filtering input clock, obtain low-frequency clock earlier, with a phase-locked loop low-frequency clock is converted to high frequency clock again.Because the reliability of phase-locked loop that input clock is converted to the phase-locked loop of low-frequency clock and low-frequency clock is converted to high frequency clock is all than higher, and can finish the task of input clock being converted to high frequency clock equally, so the clock of the embodiment of the invention is changed successful probability than prior art height.
In addition, in the prior art, high frequency VCXO cost height, especially the cost of the high frequency VCXO of hundreds of MHz is quite high, will directly cause the cost of high frequency VCXO phase-locked loop higher like this, and two phase-locked loops that the embodiment of the invention is used are not owing to need directly input clock to be converted to high frequency clock, thus do not need to comprise the high frequency VCXO, thus reduced the cost of phase-locked loop.
Description of drawings
Fig. 1 is converted to the implementation method schematic diagram of high frequency clock for existing input clock;
Fig. 2 is converted to the flow chart of the implementation method embodiment of high frequency clock for input clock of the present invention;
Fig. 3 obtains the method flow diagram of low-frequency clock for the shake of the use first order phase-locked loop filtering input clock of the embodiment of the invention;
Fig. 4 is converted to low-frequency clock for the use second level phase-locked loop of the embodiment of the invention method flow diagram of high frequency clock;
Fig. 5 is the structural representation of first embodiment of phase-locked loop apparatus of the present invention;
Fig. 6 is the structural representation of the first order phase-locked loop of the embodiment of the invention;
Fig. 7 is the structural representation of the second level phase-locked loop of the embodiment of the invention;
Fig. 8 is the structural representation of second embodiment of phase-locked loop apparatus of the present invention;
Fig. 9 is the existing method schematic diagram that different frequent points is provided for high-speed equipment;
Figure 10 provides the method schematic diagram of different frequent points for the embodiment of the invention for high-speed equipment.
Embodiment
At first method embodiment of the present invention is described.As shown in Figure 2, comprising:
Step S201: receive input clock.
Described input clock can be serial/separate the reference clock of serial line interface, also can be the clock that passes over by the backboard connecting line, can also be the circuit clock recovered.Certainly, described input clock has certain shake.
Step S202: use the shake of the described input clock of first order phase-locked loop filtering, obtain low-frequency clock.
First order phase-locked loop can be a low frequency VCXO phase-locked loop, also can be other can the filtering input clock shake, obtain the phase-locked loop of low-frequency clock, first order phase-locked loop can adopt narrow loop bandwidth.Concrete, can use the shake of first order phase-locked loop filtering input clock to obtain low-frequency clock according to flow process shown in Figure 3:
Step S2021: input clock is carried out bit comparison mutually with the low-frequency clock of output, produce error voltage corresponding to phase difference.
General, can there be frequency difference between the low-frequency clock of input clock and output and differs.For the frequency of the low-frequency clock of the frequency that makes input clock and output reaches synchronously, the phase place of the low-frequency clock of input clock and output can be compared, obtain phase signal, afterwards, again phase signal is converted to error voltage.
Step S2022: described error voltage is carried out Filtering Processing, controlled voltage.
After obtaining error voltage, error voltage can be carried out Filtering Processing, mainly be the interference component and the noise of filtering error voltage, obtains a control voltage.
Step S2023:, the frequency of low-frequency clock of output is controlled according to described control voltage.
Behind the controlled voltage, can make the frequency of the low-frequency clock of output try one's best approaching according to control voltage with the frequency of input clock.
Step S2021-2023 can be the process of a circulation, so that the frequency of the low-frequency clock of output is gradually consistent with frequency input clock.
In addition, in step S2021, if necessary, can be earlier respectively the low-frequency clock of input clock and output being carried out frequency division handles, obtain input clock and low-frequency clock behind the frequency division respectively, again the input clock behind the frequency division is carried out bit comparison mutually with low-frequency clock afterwards, produce error voltage corresponding to phase difference.Certainly, also can only carry out frequency division and handle, again clock behind the frequency division and another one not had the clock of frequency division to carry out bit comparison mutually a clock in the low-frequency clock of input clock and output.At this moment, in step S2023, can be according to control voltage, make the frequency of the low-frequency clock of output reach expected frequency with respect to the frequency of input clock as far as possible.
Behind the completing steps S202, execution in step S203: use second level phase-locked loop that described low-frequency clock is converted to high frequency clock.
Second level phase-locked loop can be voltage controlled oscillator (VCO, a Voltage Control Oscillator) phase-locked loop, also can be other the phase-locked loop that low-frequency clock can be converted to high frequency clock, and second level phase-locked loop can adopt wide loop bandwidth.Concrete, can use second level phase-locked loop that low-frequency clock is converted to high frequency clock according to flow process shown in Figure 4:
Step S2031: the high frequency clock of voltage controlled oscillator output is carried out frequency division handle, obtain the high frequency clock behind the frequency division, the high frequency clock behind low-frequency clock and the frequency division is carried out bit comparison mutually, generation is corresponding to the error voltage of phase difference.
Because the frequency of high frequency clock is than the frequency height of low-frequency clock, thus when carrying out frequency inverted, approaching as far as possible for the frequency of two clocks making second level phase-locked loop input input, generally all can carry out frequency division and handle high frequency clock.
Step S2032: described error voltage is carried out Filtering Processing, controlled voltage.
After obtaining error voltage, error voltage can be carried out Filtering Processing, mainly be interference component and noise in the filtering error voltage, obtains a control voltage.
Step S2033:, the frequency of high frequency clock of output is controlled according to described control voltage.
Behind the controlled voltage, can be according to control voltage, make the frequency of the high frequency clock of output reach expected frequency with respect to the frequency of low-frequency clock as far as possible.
Step S2031-2033 can be the process of a circulation, so that the frequency of the high frequency clock of output reaches the expected frequency with respect to the frequency of low-frequency clock as far as possible.
In addition, in step S2031, if necessary, can be respectively the high frequency clock of low-frequency clock and output being carried out frequency division handles, obtain low-frequency clock behind the frequency division and the high frequency clock behind the frequency division respectively, again the high frequency clock behind the low-frequency clock behind the frequency division and the frequency division is carried out bit comparison mutually afterwards, produce error voltage corresponding to phase difference.
Behind step S203, if follow-up high-speed interface does not need the frequency of the high frequency clock that step S203 obtains, then can carry out frequency division to the high frequency clock that step S203 obtains and handle, divide ratio can be decided according to the actual requirements.For example, the frequency of supposing the high frequency clock that step S203 obtains is 2GHz, and follow-up high-speed interface only needs the high frequency clock of 1GHz, can carry out frequency division so to the high frequency clock of 2GHz and handle, and divide ratio is 2, obtains the high frequency clock of 1GHz; If follow-up high-speed interface only needs the high frequency clock of 500GHz, divide ratio is exactly 4 so.
Said method embodiment can be realized that for this reason, the present invention also provides a kind of embodiment of phase-locked loop apparatus by the device of various ways.As shown in Figure 5, phase-locked loop apparatus 51 comprises: first order phase-locked loop 501, be used for the shake of the input clock that filtering receives, and obtain low-frequency clock; Second level phase-locked loop 502 is used for described low-frequency clock is converted to high frequency clock.
Described input clock can be serial/separate the reference clock of serial line interface, also can be the clock that passes over by the backboard connecting line, can also be the circuit clock recovered.Certainly, described input clock has certain shake.
First order phase-locked loop 501 can be a low frequency VCXO phase-locked loop, also can be other can the filtering input clock shake, obtain the phase-locked loop of low-frequency clock, first order phase-locked loop 501 can adopt narrow loop bandwidth.Concrete, as shown in Figure 6, first order phase-locked loop 501 comprises: phase discriminator 5011, be used for input clock is carried out bit comparison mutually with low-frequency clock, and produce error voltage corresponding to phase difference; Loop filter 5012 is used for the error voltage that phase discriminator 5011 produces is carried out Filtering Processing, controlled voltage; Low frequency VCXO 5013 is used for the control voltage that obtains according to loop filter 5012, and the frequency of described low-frequency clock is controlled.Wherein, after loop filter 5012 obtains error voltage, error voltage can be carried out Filtering Processing, mainly be the interference component and the noise of filtering error voltage, obtains a control voltage; Behind the low frequency VCXO 5013 controlled voltages, can make the frequency of the low-frequency clock of output try one's best approaching according to control voltage with the frequency of input clock.
Can constitute a loop between phase discriminator 5011, loop filter 5012 and the low frequency VCXO 5013, so that the frequency of the low-frequency clock of output is gradually consistent with frequency input clock.
In addition, if necessary, phase discriminator 5011 can be earlier carries out frequency division to the low-frequency clock of input clock and output respectively to be handled, obtain input clock and low-frequency clock behind the frequency division respectively, again the input clock behind the frequency division is carried out bit comparison mutually with low-frequency clock afterwards, produce error voltage corresponding to phase difference.Certainly, phase discriminator 5011 also can only carry out frequency division to a clock in the low-frequency clock of input clock and output to be handled, and clock behind the frequency division and another one is not had the clock of frequency division to carry out bit comparison mutually again.At this moment, low frequency VCXO 5013 can be according to control voltage, makes the frequency of the low-frequency clock of output reach expected frequency with respect to the frequency of input clock as far as possible.
Referring again to Fig. 5, second level phase-locked loop 502 can be the voltage controlled oscillator phase-locked loop, the mode that for example adopts LMX2306/AD4001 or AD9510/CDCM7005 class phase discriminator to add voltage controlled oscillator realizes, also can directly adopt the phase-locked loop device of integrated voltage controlled oscillator, as AD9516/AD9517/AD9518/CDCE72010 etc., comparatively speaking, the latter's realization cost is lower, application is more flexible, certainly, second level phase-locked loop 502 also can be other the phase-locked loop that low-frequency clock can be converted to high frequency clock.Second level phase-locked loop 502 can adopt wide loop bandwidth, specifically can be according to practical situations from several KHz to hundreds of KHz.Concrete, as shown in Figure 7, second level phase-locked loop 502 comprises: phase discriminator 5021, be used for the high frequency clock of voltage controlled oscillator output is carried out the frequency division processing, obtain the high frequency clock behind the frequency division, high frequency clock behind low-frequency clock and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference; Loop filter 5022 is used for the error voltage that phase discriminator 5021 produces is carried out Filtering Processing, controlled voltage; Voltage controlled oscillator 5023 is used for the control voltage that obtains according to loop filter 5022, and the frequency of the high frequency clock of output is controlled.After loop filter 5022 obtains error voltage, error voltage can be carried out Filtering Processing, mainly be interference component and noise in the filtering error voltage, obtains a control voltage.Behind the voltage controlled oscillator 5023 controlled voltages, can be according to control voltage, make the frequency of the high frequency clock of output reach expected frequency with respect to the frequency of low-frequency clock as far as possible.
In addition, if necessary, phase discriminator 5021 can be respectively carries out frequency division to the high frequency clock of low-frequency clock and output to be handled, obtain low-frequency clock behind the frequency division and the high frequency clock behind the frequency division respectively, again the high frequency clock behind the low-frequency clock behind the frequency division and the frequency division is carried out bit comparison mutually afterwards, produce error voltage corresponding to phase difference.
Referring again to Fig. 5, behind the second level phase-locked loop 502 output high frequency clocks,, then can carry out frequency division and handle described high frequency clock if follow-up high-speed equipment 503 does not need the frequency of described high frequency clock, divide ratio can be decided according to the actual requirements.Concrete, shown in Figure 8, phase-locked loop apparatus 81 also comprises the frequency divider 803 that is arranged between second level phase-locked loop 802 and the high-speed equipment 804 except that comprising first order phase-locked loop 801 and second level phase-locked loop 802, be used for the high frequency clock of second level phase-locked loop 802 outputs is carried out the frequency division processing.For example, the frequency of supposing the high frequency clock of second level phase-locked loop 802 outputs is 2GHz, and 804 high frequency clocks that need 1GHz of high-speed equipment, after the high frequency clock of the 2GHz of second level phase-locked loop 802 outputs is handled through frequency divider 803 frequency divisions so, can obtain the high frequency clock of 1GHz, and then satisfy the demand of high-speed equipment 804.
In all embodiment of the present invention, be not to use high frequency VCXO phase-locked loop that input clock is converted to high frequency clock, but with a phase-locked loop input clock is converted to low-frequency clock earlier, with a phase-locked loop low-frequency clock is converted to high frequency clock again, owing to input clock is converted to the oscillator in the phase-locked loop of low-frequency clock and low-frequency clock is converted to the reliability of the oscillator in the phase-locked loop of high frequency clock all very high, so the reliability of two phase-locked loops is also all very high, the probability that the clock conversion is successful also can thereby improve.
In all embodiment of the present invention, owing to input clock is converted to the oscillator in the phase-locked loop of low-frequency clock and low-frequency clock is converted to the process characteristic of the oscillator in the phase-locked loop of high frequency clock, the cost of manufacture of two kinds of oscillators is lower, so the cost of two phase-locked loops is also lower.
In all embodiment of the present invention, because the capture range of voltage controlled oscillator is than broad, so can satisfy the demand of different frequent points.For example, in the prior art, satisfy the demand of different frequent points if desired, then need to adopt different high frequency VCXOs to realize.As shown in Figure 9, if high-speed equipment 92 needs the clock of three different frequencies, then because the frequency pulling scope of high frequency VCXO is smaller, generally all in 200ppm, so need to use three high frequency VCXO phase-locked loops 91,91 ' and 91 " export the clock of three different frequencies.Certainly, high-speed equipment 93 may not require high frequency VCXO phase-locked loop 91,91 ' and 91 " export the clock of different frequency simultaneously; and just at the clock that requires a frequency sometime; but high frequency VCXO phase-locked loop 91,91 ' and 91 " must exist simultaneously, could satisfy high-speed equipment 92 in difference constantly to the demand of different frequency clock.Mentioned above, reasons such as process characteristic owing to the high frequency VCXO, the cost height of high frequency VCXO phase-locked loop, reliability is low, so, use a plurality of high frequency VCXO phase-locked loops to realize that the output of different frequency clock can make the cost of realization higher, reliability also can be lower.And in an embodiment of the present invention, because the capture range of voltage controlled oscillator compares broad, so often only need a phase-locked loop apparatus that comprises the voltage controlled oscillator phase-locked loop, carry out different configurations by software, just can satisfy high-speed equipment in difference constantly to the demand of different frequent points, with respect to prior art, realize that cost is lower, reliability is higher.As shown in figure 10, if high-speed equipment 1003 needs three different frequency f1, f2 and f3 in the different moment, use a device 101 that comprises low frequency VCXO phase-locked loop 1001 and voltage controlled oscillator phase-locked loop 1002 so, by constantly voltage controlled oscillator phase-locked loop 1002 being carried out different configurations, promptly exportable different frequency in difference.
In all embodiment of the present invention, because the characteristic of making an uproar mutually of low frequency VCXO itself is better, making an uproar mutually of general low frequency VCXO can both reach-90dBc/Hz@100Hz ,-110dBc/Hz@1kHz ,-130dBc/Hz@10kHz ,-140dBc/Hz@1MHz, so, the low frequency VCXO phase-locked loop that uses narrow loop bandwidth is as first order phase-locked loop, can carry out good filtering to input clock, guarantee the near-end phase noise; Use the voltage controlled oscillator phase-locked loop easily the frequency of low-frequency clock to be brought up to higher frequency, and, can export the clock of different frequency because adjustable extent is very big.
In addition, if only use a high frequency voltage controlled oscillator phase-locked loop that input clock is converted to high frequency clock, then since the high frequency voltage controlled oscillator near-end make an uproar mutually poor, so the conversion after high frequency clock often can not satisfy the requirement of communication system to high-performance clock.And in all embodiment of the present invention, adopt the two-stage phase-locked loop earlier input clock to be carried out filtering, and again the low-frequency clock that obtains after the filtering is converted to high frequency clock, just can satisfy the requirement of communication system to high-performance clock.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (14)
1. an input clock is converted to the implementation method of high frequency clock, it is characterized in that, comprising:
Receive input clock;
Use the shake of the described input clock of first order phase-locked loop filtering, obtain low-frequency clock;
Described first order phase-locked loop is a low frequency VCXO phase-locked loop;
The low-frequency clock that input clock and the low frequency VCXO in the low frequency VCXO phase-locked loop are exported carries out bit comparison mutually, produces the error voltage corresponding to phase difference between input clock and the low-frequency clock;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of low-frequency clock is controlled;
Use second level phase-locked loop that low-frequency clock is converted to high frequency clock.
2. input clock as claimed in claim 1 is converted to the implementation method of high frequency clock, it is characterized in that, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, uses the voltage controlled oscillator phase-locked loop that described low-frequency clock is converted to high frequency clock and is specially:
The high frequency clock of the voltage controlled oscillator in voltage controlled oscillator phase-locked loop output is carried out frequency division handle, obtain the high frequency clock behind the frequency division;
High frequency clock behind low-frequency clock and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of the high frequency clock of voltage controlled oscillator output is controlled.
3. input clock as claimed in claim 1 is converted to the implementation method of high frequency clock, it is characterized in that, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, uses the voltage controlled oscillator phase-locked loop that described low-frequency clock is converted to high frequency clock and is specially:
Respectively the high frequency clock of the voltage controlled oscillator in low-frequency clock and voltage controlled oscillator phase-locked loop output is carried out frequency division and handle, obtain low-frequency clock and high frequency clock behind the frequency division;
High frequency clock behind low-frequency clock behind the frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of the high frequency clock of voltage controlled oscillator output is controlled.
4. an input clock is converted to the implementation method of high frequency clock, it is characterized in that, comprising:
Receive input clock;
Use the shake of the described input clock of first order phase-locked loop filtering, obtain low-frequency clock, described first order phase-locked loop is a low frequency VCXO phase-locked loop;
Respectively the low-frequency clock of the low frequency VCXO in input clock and low frequency VCXO phase-locked loop output is carried out frequency division and handle, obtain input clock and low-frequency clock behind the frequency division;
Low-frequency clock behind input clock behind the described frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of the low-frequency clock of described output is controlled;
Use second level phase-locked loop that low-frequency clock is converted to high frequency clock.
5. input clock as claimed in claim 4 is converted to the implementation method of high frequency clock, and its feature exists
In, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, uses the voltage controlled oscillator phase-locked loop with described
Low-frequency clock is converted to high frequency clock and is specially:
The high frequency clock of the voltage controlled oscillator in voltage controlled oscillator phase-locked loop output is carried out frequency division handle, obtain the high frequency clock behind the frequency division;
High frequency clock behind low-frequency clock and the frequency division is carried out bit comparison mutually, produce mistake corresponding to phase difference
Potential difference;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of the high frequency clock of voltage controlled oscillator output is controlled.
6. input clock as claimed in claim 4 is converted to the implementation method of high frequency clock, and its feature exists
In, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, uses the voltage controlled oscillator phase-locked loop with described
Low-frequency clock is converted to high frequency clock and is specially:
Respectively the high frequency clock of the voltage controlled oscillator in low-frequency clock and voltage controlled oscillator phase-locked loop output is carried out frequency division and handle, obtain low-frequency clock and high frequency clock behind the frequency division;
High frequency clock behind low-frequency clock behind the frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
Described error voltage is carried out Filtering Processing, controlled voltage;
According to described control voltage, the frequency of the high frequency clock of voltage controlled oscillator output is controlled.
7. a phase-locked loop apparatus is characterized in that, comprising:
First order phase-locked loop is used for the shake of the input clock that filtering receives, and obtains low-frequency clock;
Second level phase-locked loop is used for low-frequency clock is converted to high frequency clock;
Also comprise:
First phase discriminator is used for input clock is carried out bit comparison mutually with low-frequency clock, produces the error voltage corresponding to phase difference;
First loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
The first low frequency VCXO is used for the control voltage that obtains according to described loop filter, and the frequency of described low-frequency clock is controlled.
8. phase-locked loop apparatus as claimed in claim 7 is characterized in that, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, comprising:
Second phase discriminator is used for high frequency clock to voltage controlled oscillator output and carries out frequency division and handle, and obtains the high frequency clock behind the frequency division, and the high frequency clock behind low-frequency clock and the frequency division is carried out bit comparison mutually, and generation is corresponding to the error voltage of phase difference;
Second loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
Second voltage controlled oscillator is used for the control voltage that obtains according to described loop filter, and the frequency of the high frequency clock of output is controlled.
9. phase-locked loop apparatus as claimed in claim 7 is characterized in that, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, comprising:
Second phase discriminator, being used for that low-frequency clock is carried out frequency division handles, obtain the low-frequency clock behind the frequency division, high frequency clock to voltage controlled oscillator output carries out the frequency division processing, obtain the high frequency clock behind the frequency division, high frequency clock behind low-frequency clock behind the frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
Second loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
Second voltage controlled oscillator is used for the control voltage that obtains according to described loop filter, and the frequency of the high frequency clock of output is controlled.
10. phase-locked loop apparatus as claimed in claim 8 or 9 is characterized in that, also comprises: frequency divider is used for that the high frequency clock that described second level phase-locked loop obtains is carried out frequency division and handles.
11. a phase-locked loop apparatus is characterized in that, comprising:
First order phase-locked loop is used for the shake of the input clock that filtering receives, and obtains low-frequency clock;
Second level phase-locked loop is used for low-frequency clock is converted to high frequency clock;
Also comprise:
First phase discriminator, being used for that input clock is carried out frequency division handles, obtain the input clock behind the frequency division, low-frequency clock to the output of low frequency VCXO carries out the frequency division processing, obtain the low-frequency clock behind the frequency division, low-frequency clock behind input clock behind the described frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
First loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
The first low frequency VCXO is used for the control voltage that obtains according to described loop filter, and the frequency of the low-frequency clock of output is controlled.
12. phase-locked loop apparatus as claimed in claim 11 is characterized in that, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, comprising:
Second phase discriminator is used for high frequency clock to voltage controlled oscillator output and carries out frequency division and handle, and obtains the high frequency clock behind the frequency division, and the high frequency clock behind low-frequency clock and the frequency division is carried out bit comparison mutually, and generation is corresponding to the error voltage of phase difference;
Second loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
Second voltage controlled oscillator is used for the control voltage that obtains according to described loop filter, and the frequency of the high frequency clock of output is controlled.
13. phase-locked loop apparatus as claimed in claim 11 is characterized in that, described second level phase-locked loop is the voltage controlled oscillator phase-locked loop, comprising:
Second phase discriminator, being used for that low-frequency clock is carried out frequency division handles, obtain the low-frequency clock behind the frequency division, high frequency clock to voltage controlled oscillator output carries out the frequency division processing, obtain the high frequency clock behind the frequency division, high frequency clock behind low-frequency clock behind the frequency division and the frequency division is carried out bit comparison mutually, produce error voltage corresponding to phase difference;
Second loop filter is used for the error voltage that described phase discriminator produces is carried out Filtering Processing, controlled voltage;
Second voltage controlled oscillator is used for the control voltage that obtains according to described loop filter, and the frequency of the high frequency clock of output is controlled.
14. as claim 12 or 13 described phase-locked loop apparatus, it is characterized in that, also comprise: frequency divider is used for that the high frequency clock that described second level phase-locked loop obtains is carried out frequency division and handles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101984807A CN101183871B (en) | 2007-12-17 | 2007-12-17 | Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101984807A CN101183871B (en) | 2007-12-17 | 2007-12-17 | Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101183871A CN101183871A (en) | 2008-05-21 |
| CN101183871B true CN101183871B (en) | 2010-12-08 |
Family
ID=39448974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101984807A Expired - Fee Related CN101183871B (en) | 2007-12-17 | 2007-12-17 | Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101183871B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8217696B2 (en) | 2009-12-17 | 2012-07-10 | Intel Corporation | Adaptive digital phase locked loop |
| CN102457274A (en) * | 2010-10-21 | 2012-05-16 | 钰宝科技股份有限公司 | Digital frequency synthesizer having phase-locking loop |
| US8461885B2 (en) * | 2011-06-08 | 2013-06-11 | Analog Devices, Inc. | Hybrid digital-analog phase locked loops |
| CN102307048A (en) * | 2011-07-15 | 2012-01-04 | 大唐移动通信设备有限公司 | Clock based on Pico (pine composer) RRU (radio remote unit) and implementation method thereof |
| CN106209342B (en) * | 2016-08-25 | 2022-10-18 | 四川灵通电讯有限公司 | System for realizing low-frequency clock transmission in xDSL transmission system |
| CN106656460A (en) * | 2016-11-22 | 2017-05-10 | 浙江大学 | Defense device for electromagnetic pulse fault analysis of password chip |
| CN116527024B (en) * | 2023-07-05 | 2023-09-01 | 中国电子科技集团公司第十四研究所 | Clock circuit based on broadband RFSoC chip |
-
2007
- 2007-12-17 CN CN2007101984807A patent/CN101183871B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101183871A (en) | 2008-05-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101183871B (en) | Method of implementing conversion of input clock to high-frequency clock and phase-locked loop apparatus | |
| CN101321294B (en) | Audio clock regenerator with precisely tracking mechanism | |
| US8243867B2 (en) | Receiver and communication system having the same | |
| CN101098220A (en) | Digital phase-locked loop based clock synchronization method and system thereof | |
| US9130736B2 (en) | Transceiver system having phase and frequency detector and method thereof | |
| CN101136631B (en) | Frequency synthesizer and frequency synthesis method | |
| US7782104B2 (en) | Delay element array for time-to-digital converters | |
| CA2851843A1 (en) | Systems and methods for tracking a received data signal in a clock and data recovery circuit | |
| US6333678B1 (en) | Method and apparatus for agile phase noise filtering using phase locked loops | |
| CN105024692A (en) | Clock generation circuit with dual phase-locked loops | |
| CN115694477B (en) | Subsampled phase-locked loop based on small-range dead zone generation module architecture | |
| US10574242B2 (en) | Phase locked loop sampler and restorer | |
| EP1876712A1 (en) | Clock generating circuit and audio system | |
| US10256827B2 (en) | Reference-frequency-insensitive phase locked loop | |
| US7443251B2 (en) | Digital phase and frequency detector | |
| US7847641B2 (en) | Digital phase and frequency detector | |
| US20230344615A1 (en) | Circuit and Method for Removing Spread Spectrum | |
| CN113472347B (en) | Electronic device and sampling method | |
| CN102307048A (en) | Clock based on Pico (pine composer) RRU (radio remote unit) and implementation method thereof | |
| CN111837339B (en) | Phase-locked loop circuit and device using the same | |
| US6707343B2 (en) | Frequency synthesis apparatus, systems, and methods | |
| CN101521508B (en) | Multi-loop phase-locked loop device and phase-locked method | |
| US6647079B1 (en) | Surface acoustic wave-based clock and data recovery circuit | |
| Qin et al. | An all-digital clock-smoothing technique-counting-prognostication | |
| Gupta | C DOT |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101208 Termination date: 20171217 |