CN101180709A - 非对称双向瞬态电压抑制器及其形成方法 - Google Patents
非对称双向瞬态电压抑制器及其形成方法 Download PDFInfo
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Abstract
提供一种双向瞬态电压抑制装置和制造该装置的方法。该方法开始于提供第一导电类型的半导体衬底,并在衬底上淀积与第一导电类型相反的第二导电类型的第一外延层。衬底和第一外延层形成第一p-n结。在第一外延层上淀积具有第二导电类型的第二外延层。第二外延层比第一外延层具有更高的掺杂剂浓度。在第二外延层上形成具有第一导电类型的第三层。第二外延层和第三层形成第二p-n结。
Description
技术领域
本发明总的来说涉及瞬态电压抑制器(TVS),更具体而言涉及非对称双向瞬态电压抑制器。
背景技术
通信设备、计算机、家庭立体声放大器、电视和其他电子装置越来越多地使用小电子元件制造,这些小电子元件极易受到电子能量浪涌(即瞬态过电压)的损害。电源和传输线电压中的浪涌变化会严重损害和/或破坏电子装置。而且修复和更换这些电子装置可能是非常昂贵的。因此需要保护这些元件免受电源浪涌损害的成本有效的方法。开发了被称为瞬态电压抑制器(TVS)的装置来保护这些类型的设备免受这种电源浪涌或过电压瞬变。采用这些装置(典型地是类似于分立式基准电压二极管的分立式装置),以便在达到瞬变和潜在地损害集成电路或类似结构之前抑制电源等中的高电压的瞬变。
一种用于过电压保护的传统装置是反偏p+n+齐纳二极管。为了提供保护以免受任一极性过电压,经常采用双向瞬态电压抑制器,其具有两个结而不是单个结。然而这种双向TVS经常是对称的,因为它们为两极提供同样的闭锁电压。图1的横截面图示意性地示出了传统非对称双向TVS 100的实例。该装置在n衬底110上形成。n型外延层120在n衬底110的上表面形成。其次,p型掺杂剂扩散进入衬底110两侧以形成p+扩散层130和104。这种装置包含两个结:(1)在p+扩散层130和n型外延层120的界面处形成的结,和(2)在n衬底110和p+扩散层104之间的界面处形成的结。通过在p+扩散层130和n型外延层120的界面处形成的结支持较大的闭锁电压,而通过在n衬底110和p+扩散层104之间的界面处形成的结支持较小的闭锁电压。
如图2所示,对于结终端,图1的非对称双向TVS典型地在衬底两侧具有台面结构。
关于图1和2示出的非对称双向TVS出现了许多问题。第一,因为扩散层在衬底110的两侧形成,必须在两侧提供钝化以保护两个结。得到的双边斜面终端结构降低了该装置的机械完整度。第二,因为必需的高掺杂的衬底的原因,制造该装置是相当昂贵的,这是因为其掺杂剂浓度必须被精确地控制。
因此,希望提供克服了上述问题的非对称双向TVS。
发明内容
根据本发明,提供了双向瞬态电压抑制装置及其制造方法。该方法开始于提供第一导电类型的半导体衬底,并在衬底上淀积与第一导电类型相反的第二导电类型的第一外延层。衬底和第一外延层形成第一p-n结。具有第二导电类型的第二外延层淀积在第一外延层上。第二外延层与第一外延层相比有更高的掺杂剂浓度。具有第一导电类型的第三层在第二外延层上形成。第二外延层和第三层形成第二p-n结。
根据本发明的一个方面,第三层通过第一导电类型的掺杂剂扩散进入第二外延层而形成。
根据本发明的另一个方面,第一导电类型是p型导电类型,并且第二导电类型是n型导电类型。
根据本发明的另一个方面,衬底是p+衬底,第一外延层是n型外延层,第二外延层是n外延层,第三层是p+层。
根据本发明的另一个方面,第一外延层的掺杂浓度在大约1.80×1014cm-3到大约2.82×1014cm-3变化。
根据本发明的另一个方面,第一外延层生长至大约57.6到70.4微米的厚度。
根据本发明的另一个方面,第一导电类型是n型导电类型,并且第二导电类型是p型导电类型。
根据本发明的另一个方面,提供一种双向瞬态电压抑制装置。该装置包括第一导电类型的半导体衬底和在衬底上形成的与第一导电类型相反的第二导电类型的第一外延层。衬底和第一外延层形成第一p-n结。具有第二导电类型的第二外延层在第一外延层上形成。第二外延层比第一外延层具有更高的掺杂剂浓度。具有第一导电类型的第三层在第二外延层上形成。第二外延层和第三层形成第二p-n结。
附图说明
图1用示意性的横截面图示出传统的非对称双向TVS。
图2示出具有台面结构的图1的非对称双向TVS。
图3示出根据本发明的非对称双向TVS的示意性横截面图。
图4A-4C示出可用于制造图3中示出的TVS的代表性工艺流程。
图5示出本发明的一个特定实施例在硼扩散前的仿真掺杂分布。
图6示出图5所示结构在硼扩散后的仿真掺杂分布。
图7示出图5的结构中两极的仿真反向击穿电压曲线。
图8示出本发明的一个替代实施例,其中仅采用单个外延层。
图9示出图8所示装置在磷退火后的仿真掺杂分布。
图10示出图8所示装置在硼退火后的仿真掺杂分布。
具体实施方式
本领域的技术人员会认识到:本发明的下列描述仅具有说明性而不以任何方式限制。这些技术人员会容易地想到本发明的其他实施例。
现在参看图3,其示出根据本发明的非对称双向TVS 300的示意性横截面图。该装置在p+衬底310上形成。n型第一外延层320在p+衬底310的上表面形成。n型第二外延层330在n型第一外延层320上形成。其次,p型掺杂剂扩散进入n型第二外延层,以形成p+扩散层340。这种装置包含两个结:(1)在p+扩散层340和n型第二外延层330的界面处形成的结,和(2)在p+衬底310和n型第一外延层320之间的界面处形成的结。通过在p+扩散层340和n型第二外延层330的界面处形成的结支持较小的闭锁电压,而通过在p+衬底310和n型第一外延层320之间的界面处形成的结支持较大的闭锁电压。
基于许多原因,图3所示结构是有优势的。首先,通过在p+衬底310和n型第一外延层320之间的界面处形成的结所支持的闭锁电压可以被更精确地控制,因为它是通过外延生长工艺而不是扩散工艺决定的。其次,通过同样的钝化和该装置上侧的单个台面结构可以保护这两个结。通过消除对双边斜面终端结构的需要(如传统非对称双向TVS所需的),能够保持机械完整度,从而减少破坏的可能性。此外,因为采用了具有相对高的掺杂剂浓度的衬底,该装置能够支持所期望的电压,同时维持更好的反向浪涌性能。
本发明的双向瞬态电压抑制器可以使用标准硅片制造技术制造。典型的工艺流程如下面参考图4A到4C所示。本领域的技术人员会容易地认识到:这里公开的工艺流程绝不意味着是限制性的,因为有许多替代方案来制造该双向瞬态电压抑制器。
现在参看图4A,用于本发明的双向瞬态电压抑制装置的起始衬底材料是具有尽可能低电阻率的(典型的从大约0.01到0.002ohm-cm-3)p型(p+)硅。然后,使用常规外延生长技术,掺杂浓度在大约1.80×1014到大约2.82×1014原子/cm3(击穿电压越高,所需的浓度越低)范围之内的n型(n-)外延层420在衬底410上生长至在大约57.6和大约70.4微米(n+掺杂浓度越高,所需的厚度越小)之间的厚度。同样使用常规外延生长技术,掺杂浓度在大约4.88×1016到大约6.46e×1016原子/cm3(击穿电压越高,所需的浓度越低)范围之内的n型外延层430在n型外延层420上生长至在大约26.68和大约31.32微米(击穿电压越高,所需的厚度越大)之间的厚度。于是,p型(p+)层440通过扩散在n型外延层430中形成。
在本发明的一个特定实施例中,对于不同的极性,非对称双向TVS被设计在30V和300V的击穿电压范围内工作。p+衬底410有大约0.004ohm-cm-3的电阻率,第一n型外延层420为65微米厚,其具有1×1015cm-3的掺杂剂浓度。第二n型外延层430为30微米厚,其具有5.5×1016cm-3的掺杂剂浓度。该结构的仿真掺杂分布在图5中示出。p+扩散层440通过使用圆盘源(disk source)的硼扩散而形成。如果想得到更精确的击穿电压的控制,可以在多步内实行硼的驱入(drive in)。硼扩散后的该结构的仿真掺杂分布在图6中示出。两极的仿真反向击穿电压曲线在图7中示出。
现在参考图4B,然后使用常规技术,例如低压化学汽相淀积,在整个表面淀积氮化硅层450。使用常规光刻胶掩模和蚀刻工艺,在氮化硅层450中形成期望的图案。然后,使用形成图案的氮化硅层450作为掩模,使用标准化学蚀刻技术形成沟槽460。沟槽460延伸足够的深度进入衬底(即在两个结之外的阱),以提供隔离并构建台面结构。图4B显示完成氮化硅掩模和沟槽蚀刻步骤之后所得到的结构。
现在参看图4C,根据本发明的实施例,在图4B的结构上生长厚的、钝化氧化硅层470(优选地大约1/2微米厚)。因为在衬底中任何附加的扩散将影响掺杂分布,在该工艺中高温和长时间的扩散步骤应该在这一点最小化。因此,对于热氧化物钝化,在一些情况下玻璃钝化可能更优选的。最后,通过去除氮化物层450而形成接触窗口,并且使用常规技术利用p+扩散层340和p+衬底310形成触点(没有显示)。
图8示出了本发明的一个替代实施例,其中仅采用单个外延层。在这种情况下,提供晶片,其包括衬底810,在衬底上形成n型外延层820。通过合适的n型掺杂剂(例如磷)的离子注入,接着进行退火,而在n型外延层820上形成n层830。在本发明的一个特定实施例中,以剂量3×1015cm-2和能量80Kev注入磷。在大约1265℃的温度进行退火15小时。磷退火后的仿真掺杂分布在图9中示出。通过合适的p型掺杂剂(例如硼)的离子注入可以形成p+层840。在本发明的一个特定实施例中,以剂量2×1015cm-2和能量80Kev注入硼。在大约1265℃的温度进行退火2小时。硼退火后的仿真掺杂分布在图10中示出。在所得到的装置中对于两极的仿真反向击穿电压曲线与图7中示出的那些相似。
Claims (14)
1.一种制造双向瞬态电压抑制装置的方法,包括:
提供第一导电类型的半导体衬底;
在所述衬底上淀积与所述第一导电类型相反的第二导电类型的第一外延层,所述衬底与所述第一外延层形成第一p-n结。
在第一外延层上淀积具有所述第二导电类型的第二外延层,所述第二外延层具有比所述第一外延层更高的掺杂剂浓度;和
在所述第二外延层上形成具有所述第一导电类型的第三层,所述第二外延层与所述第三层形成第二p-n结。
2.根据权利要求1的方法,其中所述第三层通过所述第一导电类型的掺杂剂扩散进入所述第二外延层而形成。
3.根据权利要求1的方法,其中所述第一导电类型是p型导电类型,并且所述第二导电类型是n型导电类型。
4.根据权利要求3的方法,其中所述衬底是p+衬底,其中所述第一外延层是n型外延层,其中所述第二外延层是n外延层,其中所述第三层是p+层。
5.根据权利要求1的方法,其中第一外延层的掺杂浓度范围从大约1.80×1014cm-3到大约2.82×1014cm-3。
6.根据权利要求5的方法,其中第一外延层生长至从大约57.6到大约70.4微米的厚度。
7.根据权利要求1的方法,其中所述第一导电类型是n型导电类型,并且所述第二导电类型是p型导电类型。
8.一种双向瞬态电压抑制装置,包括:
第一导电类型的半导体衬底;
在所述衬底上形成的与所述第一导电类型相反的第二导电类型的第一外延层,所述衬底与所述第一外延层形成第一p-n结;
在第一外延层上形成的具有所述第二导电类型的第二外延层,所述第二外延层具有比所述第一外延层更高的掺杂剂浓度;和
在所述第二外延层上形成的具有所述第一导电类型的第三层,所述第二外延层和所述第三层形成第二p-n结。
9.根据权利要求8的双向瞬态电压抑制装置,其中所述第三层通过所述第一导电类型的掺杂剂扩散进入所述第二外延层而形成。
10.根据权利要求8的双向瞬态电压抑制装置,其中所述第一导电类型是p型导电类型,并且所述第二导电类型是n型导电类型。
11.根据权利要求4的双向瞬态电压抑制装置,其中所述衬底是p+衬底,其中所述第一外延层是n型外延层,其中所述第二外延层是n外延层,其中所述第三层是p+层。
12.根据权利要求8的双向瞬态电压抑制装置,其中第一外延层的掺杂浓度范围从大约1.80×1014cm-3到大约2.82×1014cm-3。
13.根据权利要求12的双向瞬态电压抑制装置,其中第一外延层生长至从大约57.6到大约70.4微米的厚度。
14.根据权利要求8的双向瞬态电压抑制装置,其中所述第一导电类型是n型导电类型,并且所述第二导电类型是p型导电类型。
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US11/090,897 US20060216913A1 (en) | 2005-03-25 | 2005-03-25 | Asymmetric bidirectional transient voltage suppressor and method of forming same |
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JP2008536301A (ja) | 2008-09-04 |
EP1864318A4 (en) | 2013-12-25 |
TW200644087A (en) | 2006-12-16 |
KR20070118659A (ko) | 2007-12-17 |
EP1864318A2 (en) | 2007-12-12 |
WO2006104926A3 (en) | 2006-12-21 |
US20060216913A1 (en) | 2006-09-28 |
WO2006104926A2 (en) | 2006-10-05 |
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