CN101179029A - Film transistor and its making method - Google Patents
Film transistor and its making method Download PDFInfo
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- CN101179029A CN101179029A CNA2006101484407A CN200610148440A CN101179029A CN 101179029 A CN101179029 A CN 101179029A CN A2006101484407 A CNA2006101484407 A CN A2006101484407A CN 200610148440 A CN200610148440 A CN 200610148440A CN 101179029 A CN101179029 A CN 101179029A
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Abstract
The invention discloses a thin film transistor and a manufacturing method thereof. Firstly, a gate is formed on a substrate. Then, a gate insulation layer is formed to cover the gate, and a channel layer is formed on the part of the gate insulation layer upon the gate. Later, a source and a drain are formed on the channel layer. The method for forming the gate comprises can be that a nitrogen-containing copper alloy layer and a copper layer are orderly formed and the nitrogen-containing copper alloy layer and the copper layer are partially removed. The method for forming the source and drain can be the same.
Description
Technical field
The present invention is relevant for a kind of active member and manufacture method thereof, and is particularly to a kind of thin-film transistor and manufacture method thereof.
Background technology
In the intraconnections of general display panels (liquid crystal display panel), generally be to select metals such as molybdenum, tantalum, chromium, tungsten or its alloy material for use as metal level, be the most frequently used with aluminium again wherein.Yet, to compare with aluminium, copper has less electromigration (electromigration) problem, and has Low ESR (resistivity), so copper becomes the research and development subject matter that haves a great attraction in recent years.
But, as intraconnections actual difficulty is arranged with copper.The thermal stability of copper is not good.For example, in the processing procedure of thin-film transistor, be easy to Yin Gaowen and melting phenomenon takes place as the copper of grid, and then diffusion and pass through the interface of copper and silicon or the interface of copper and silicon dioxide.The diffusion phenomena of copper can change the electrical of thin-film transistor, or reduce the reliability of thin-film transistor.Moreover, because copper is not good to the adhesive force (adhesion) of silicon, so that copper starts the problem of (peeling) is of common occurrence.Therefore, the product yield can't promote.
Summary of the invention
The invention provides a kind of method of manufacturing thin film transistor, to improve the problem of ions diffusion.
The invention provides a kind of thin-film transistor, it has higher reliability.
The present invention proposes a kind of method of manufacturing thin film transistor.Form the first nitrogenous copper alloy layer and the first bronze medal layer at first in regular turn on substrate, remove the part first nitrogenous copper alloy layer and the first bronze medal layer then, to form grid on substrate.Then, form gate insulation layer, and form one deck channel layer on the part gate insulation layer of grid top with cover gate.Afterwards, form source electrode and drain on channel layer, wherein the formation method of source electrode and drain electrode for example is to form the second nitrogenous copper alloy layer and the second bronze medal layer in regular turn prior to the substrate top.Afterwards, remove the part second nitrogenous copper alloy layer and the second bronze medal layer.
In one embodiment of this invention, the formation method of the first nitrogenous copper alloy layer for example is the physical vapor deposition processing procedure.Sputter target of this physical vapor deposition processing procedure (sputtering target) or vapor deposition source (evaporationsource) comprise copper and be selected from group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form one of them.
In one embodiment of this invention, the formation method of the second nitrogenous copper alloy layer for example is the physical vapor deposition processing procedure.The sputter target of this physical vapor deposition processing procedure or vapor deposition source comprise copper and be selected from group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form one of them.
In one embodiment of this invention, the gas that the physical vapor deposition processing procedure feeds comprises nitrogenous gas, and the flow rate ratio of this nitrogenous gas and all gas for example is 5% to 50%.
In one embodiment of this invention, nitrogenous gas for example is ammonia or nitrogen.
The present invention proposes a kind of thin-film transistor again, and it comprises grid, gate insulation layer, channel layer, source electrode and drain electrode.Gate configuration is on substrate, and grid comprises the first nitrogenous copper alloy layer and the first bronze medal layer.The first bronze medal layer is disposed on the first nitrogenous copper alloy layer.The gate insulation layer cover gate, and channel layer is disposed on the part gate insulation layer of grid top.In addition, source electrode and drain configuration are on channel layer, and wherein source electrode and drain electrode comprise the second nitrogenous copper alloy layer and the second bronze medal layer.The second nitrogenous copper alloy layer is disposed on the channel layer, and the second bronze medal layer is disposed on the second nitrogenous copper alloy layer.。
In one embodiment of this invention, the first nitrogenous copper alloy layer comprises copper and is selected from one of them nitro-alloy of group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form.
In one embodiment of this invention, the second nitrogenous copper alloy layer comprises copper and is selected from one of them nitro-alloy of group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form.
In one embodiment of this invention, the thickness of the first nitrogenous copper alloy layer is between 200 to 500 dusts.
In one embodiment of this invention, the thickness of the second nitrogenous copper alloy layer is between 200 to 500 dusts.
In one embodiment of this invention, the thickness of the first bronze medal layer is between 1500 to 4000 dusts.
In one embodiment of this invention, the thickness of the second bronze medal layer is between 1500 to 4000 dusts.
In one embodiment of this invention, the thickness ratio of the first bronze medal layer and the first nitrogenous copper alloy layer is between 5 to 15.
In one embodiment of this invention, the thickness ratio of the second bronze medal layer and the second nitrogenous copper alloy layer is between 5 to 15.
In one embodiment of this invention, the gross thickness of the first bronze medal layer and the first nitrogenous copper alloy layer is between 2000 to 4000 dusts.
In one embodiment of this invention, the gross thickness of the second bronze medal layer and the second nitrogenous copper alloy layer is between 2000 to 4000 dusts.
Because thin-film transistor of the present invention as barrier layer, therefore can improve the ions diffusion problem between the second bronze medal layer and the channel layer with the second nitrogenous copper alloy layer.Moreover the first nitrogenous copper alloy layer can also be used to being used as adhesion layer, promoting the bond strength between the first bronze medal layer and the substrate, and then reduces the possibility that the copper layer is peeled off or copper starts takes place.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, an embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process top view of the thin-film transistor of one embodiment of the invention.
Fig. 2 A to Fig. 2 D is respectively the profile along the hatching I-I of Figure 1A to Fig. 1 D.
Embodiment
Because the shortcoming of prior art, the present invention proposes double-decker with nitrogenous copper alloy layer/copper layer and comes grid, source electrode and drain electrode as thin-film transistor, with the phenomenon of improving the copper diffusion simultaneously and increase the adhesive force of copper to silicon.
Figure 1A to Fig. 1 D is the manufacturing process top view of the thin-film transistor of one embodiment of the invention; Fig. 2 A to Fig. 2 D is respectively the profile along the hatching I-I of Figure 1A to Fig. 1 D.The scope that Figure 1A to Fig. 1 D is illustrated is the scope of a dot structure (pixel structure) of thin-film transistor array base-plate (TFT array substrate).Below utilize Fig. 1 D and Fig. 2 D that thin-film transistor of the present invention is described earlier, its manufacture method is described again.
Please be simultaneously with reference to Fig. 1 D and Fig. 2 D, thin-film transistor of the present invention comprises grid 20g, gate insulation layer 12, channel layer 14, source electrode 30s and drain electrode 32d, wherein grid 20g is disposed on the substrate 10.Grid 20g comprises the first nitrogenous copper alloy layer 22 and the first bronze medal layer 24, and wherein the first bronze medal layer 24 is disposed on the first nitrogenous copper alloy layer 22.In the present embodiment, the first nitrogenous copper alloy layer 22 is to comprise copper and be selected from one of them nitro-alloy of group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form, as copper nitride molybdenum alloy, copper nitride molybdenum and tungsten alloy.In addition, grid 20g for example is the part of a scan wiring 20, and therefore the first nitrogenous copper alloy layer 22 and the first bronze medal layer 24 also can constitute lead.The first nitrogenous copper alloy layer 22 is to be used for being used as barrier layer (barrier), to reduce the ions diffusion between the first bronze medal layer 24 and the substrate 10.In addition, the first nitrogenous copper alloy layer 22 is again to be used for being used as adhesion layer (adhesion layer), to prevent that the first bronze medal layer 24 is from substrate 10 sur-face peelings.
More specifically, the thickness of the first nitrogenous copper alloy layer 22 can be between 200 to 500 dusts, and the thickness of the first bronze medal layer 24 can be between 1500 to 4000 dusts.Perhaps, the thickness ratio of the first bronze medal layer 24 and the first nitrogenous copper alloy layer 22 can be between 5 to 15.Perhaps, the gross thickness of the first bronze medal layer 24 and the first nitrogenous copper alloy layer 22 can be between 2000 to 4000 dusts.
In addition, in the present embodiment, source electrode 30s and drain electrode 32d also comprise the second nitrogenous copper alloy layer 34 and the second bronze medal layer 36.The second nitrogenous copper alloy layer 34 is disposed on the channel layer 14, and the second bronze medal layer 36 is disposed on the second nitrogenous copper alloy layer 34.The second nitrogenous copper alloy layer 34 also can comprise copper and be selected from one of them nitro-alloy of group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form.The second nitrogenous copper alloy layer 34 is to be used for being used as barrier layer, to reduce the ions diffusion between the second bronze medal layer 36 and the channel layer 14.
More specifically, the thickness of the second nitrogenous copper alloy layer 34 can be between 200 to 500 dusts, and the thickness of the second bronze medal layer 36 can be between 1500 to 4000 dusts.Perhaps, the thickness ratio of the second bronze medal layer 36 and the second nitrogenous copper alloy layer 34 can be between 5 to 15.Perhaps, the gross thickness of the second bronze medal layer 36 and the second nitrogenous copper alloy layer 34 can be between 2000 to 4000 dusts.
In addition; in Fig. 1 D; when if this thin-film transistor is applied in the dot structure of thin-film transistor array base-plate; then this dot structure also comprises a pixel electrode (pixel electrode) 40 and protective layer 50; wherein protective layer 50 has a contact hole 50a, and pixel electrode 40 electrically connects drain electrode 32d via contact hole 50a.
Because thin-film transistor of the present invention as barrier layer, so can reduce the copper layer of grid and the ions diffusion between the substrate, also can reduce the copper layer of source electrode and drain electrode and the ions diffusion between ohmic contact layer and the channel layer with nitrogenous copper alloy layer.Moreover nitrogenous copper alloy layer can also be used to being used as adhesion layer, with the problem that prevents that the copper layer from peeling off or copper starts.Therefore, thin-film transistor of the present invention just has higher yield and reliability.
Below utilize Figure 1A to Fig. 1 D and Fig. 2 A to Fig. 2 D that above-mentioned method of manufacturing thin film transistor is described.Mandatory declaration be that above-mentioned thin-film transistor is not limited to make in this way.
Please at first provide substrate 10 simultaneously with reference to Figure 1A and Fig. 2 A, on substrate 10, form one deck first nitrogenous copper alloy material bed of material (not shown) and one deck first copper material bed of material (not shown) then in regular turn.In the present embodiment, the formation method of the first nitrogenous copper alloy material bed of material is the physical vapor deposition processing procedure, and it comprises sputter (sputteringdeposition) and evaporation (evaporation).The sputter target of physical vapor deposition processing procedure or vapor deposition source comprise copper and be selected from group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form one of them, as copper molybdenum alloy, copper molybdenum and tungsten alloy.In sputter target or vapor deposition source, the scope of the molar ratio of copper for example is from 90% to 99.9%.
In addition, the gas that this physical vapor deposition processing procedure feeds comprises nitrogenous gas, and the flow rate ratio of nitrogenous gas and all gas for example is 5% to 50%.In addition, nitrogenous gas for example is ammonia or nitrogen.On the other hand, the formation method of the first copper material bed of material for example also is the physical vapor deposition processing procedure.Then, remove the part first nitrogenous copper alloy material bed of material and the part first copper material bed of material, forming the first nitrogenous copper alloy layer 22 and the first bronze medal layer 24, thereby constitute grid 20g.In addition, the method that removes the part first nitrogenous copper alloy material bed of material and the part first copper material bed of material for example is to carry out lithographic process earlier, carries out the wet etching processing procedure afterwards.In the present embodiment, when forming grid 20g, scan wiring 20 has also formed simultaneously.
Continue it, please form one deck gate insulation layer 12 with cover gate 20g simultaneously with reference to Figure 1B and Fig. 2 B.The material of gate insulation layer 12 for example is silica or silicon nitride, and the formation method of gate insulation layer 12 for example be the plasma-enhanced chemical vapor deposition method (plasma enhanced chemical vapor deposition, PECVD).Subsequently, on the part gate insulation layer 12 of grid 20g top, form one deck channel layer 14.The material of channel layer 14 for example is amorphous silicon or polysilicon.
The formation method of the channel layer 14 of amorphous silicon for example is to form one deck amorphous silicon layer with the chemical vapor deposition processing procedure earlier, carries out lithographic process and etch process then, and forms it.The formation method of the channel layer 14 of polysilicon and the channel layer 14 of amorphous silicon are similar, but before lithographic process, also comprise amorphous silicon layer anneal (annealing).In addition, in the present embodiment, after above-mentioned chemical vapor deposition processing procedure, after above-mentioned chemical vapor deposition processing procedure or after the annealing, also comprise and carry out dopping process (doping), form one deck ohmic contact layer 14a with surface at channel layer 14.
Then, please on channel layer 14, form source electrode 30s and drain electrode 32d simultaneously with reference to Fig. 1 C and Fig. 2 C.The formation method of source electrode 30s and drain electrode 32d for example is to form the second nitrogenous copper alloy material bed of material (not shown) and the second copper material bed of material (not shown) in regular turn prior to substrate 10 tops.In the present embodiment, the formation method of the second nitrogenous copper alloy second layer is the physical vapor deposition processing procedure, and it comprises sputter and evaporation.The sputter target of physical vapor deposition processing procedure or vapor deposition source comprise copper and be selected from group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form one of them, as copper molybdenum alloy, copper molybdenum and tungsten alloy.
In sputter target or vapor deposition source, the scope of the molar ratio of copper for example is from 90% to 99.9%.In addition, the gas that this physical vapor deposition processing procedure feeds comprises nitrogenous gas, and the flow rate ratio of nitrogenous gas and all gas for example is 5% to 50%.In addition, nitrogenous gas for example is ammonia or nitrogen.On the other hand, the formation method of the second copper material bed of material for example also is the physical vapor deposition processing procedure.Afterwards, the method that removes the part second nitrogenous copper alloy material bed of material and the part second copper material bed of material for example is to carry out lithographic process earlier, carries out the wet etching processing procedure afterwards, to form source electrode 30s and drain electrode 32d.In the present embodiment, when forming source electrode 30s and drain electrode 32d, data wiring 30 has also formed simultaneously.Processing procedure carries out so far, and the thin-film transistor of one embodiment of the invention is finished.
Subsequently; please be simultaneously with reference to Fig. 1 D and Fig. 2 D; when thin-film transistor is when being applied to thin-film transistor array base-plate; successive process also is included in and forms protective layer 50 and pixel electrode 40 on the substrate 10 in regular turn; wherein protective layer 50 has a contact hole 50a; it exposes part drain electrode 32d, and pixel electrode 40 electrically connects via contact hole 50a and drain electrode 32d.Usually know the knowledgeable to having in the art, material of protective layer 50 and pixel electrode 40 and forming method thereof is well-known, so repeat no more in this.
In sum, manufacture method of the present invention can form nitrogenous copper alloy layer and copper layer in the step of a physical vapor deposition, make the copper layer of grid and the copper layer of source electrode and drain electrode be difficult for the problem that generation ions diffusion and copper start, thereby form the thin-film transistor of high yield and high-reliability.In addition, the degree of difficulty of the processing procedure of nitrogenous copper alloy layer is not high, so the present invention can realize with existing equipment and technology.
Though the present invention discloses as above with a preferable embodiment; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (18)
1. method of manufacturing thin film transistor comprises:
Form one first nitrogenous copper alloy layer and one first bronze medal layer in regular turn on a substrate;
Remove this first nitrogenous copper alloy layer of part and this first bronze medal layer, to form a grid on this substrate;
Form a gate insulation layer, to cover this grid;
Form a channel layer on this gate insulation layer of part of this grid top;
Form one source pole and and drain on this channel layer, wherein the formation method of this source electrode and this drain electrode comprises:
Form one second nitrogenous copper alloy layer and one second bronze medal layer in regular turn in this substrate top; And
Remove this second nitrogenous copper alloy layer of part and this second bronze medal layer.
2. method of manufacturing thin film transistor as claimed in claim 1, it is characterized in that, the formation method of this second nitrogenous copper alloy layer is a physical vapor deposition processing procedure, the sputter target of this physical vapor deposition processing procedure or vapor deposition source comprise copper and be selected from group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form one of them.
3. method of manufacturing thin film transistor as claimed in claim 2 is characterized in that, the gas that this physical vapor deposition processing procedure feeds comprises a nitrogenous gas, and the flow rate ratio of this nitrogenous gas and all gas is 5% to 50%.
4. method of manufacturing thin film transistor as claimed in claim 3 is characterized in that this nitrogenous gas comprises ammonia or nitrogen.
5. method of manufacturing thin film transistor as claimed in claim 1, it is characterized in that, the formation method of this first nitrogenous copper alloy layer is a physical vapor deposition processing procedure, the sputter target of this physical vapor deposition processing procedure or vapor deposition source comprise copper and be selected from group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form one of them.
6. method of manufacturing thin film transistor as claimed in claim 5 is characterized in that, the gas that this physical vapor deposition processing procedure feeds comprises a nitrogenous gas, and the flow rate ratio of this nitrogenous gas and all gas is 5% to 50%.
7. method of manufacturing thin film transistor as claimed in claim 6 is characterized in that this nitrogenous gas comprises ammonia or nitrogen.
8. thin-film transistor comprises:
One grid is disposed on the substrate, and this grid comprises:
One first nitrogenous copper alloy layer;
One first bronze medal layer is disposed on this first nitrogenous copper alloy layer;
One gate insulation layer covers this grid;
One channel layer is disposed on this gate insulation layer of part of this grid top;
An one source pole and a drain electrode are disposed on this channel layer, and wherein this source electrode and this drain electrode comprise:
One second nitrogenous copper alloy layer is disposed on this channel layer; And
One second bronze medal layer is disposed on this second nitrogenous copper alloy layer.
9. thin-film transistor as claimed in claim 8 is characterized in that, this second nitrogenous copper alloy layer comprises copper and is selected from one of them nitro-alloy of group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form.
10. thin-film transistor as claimed in claim 8 is characterized in that, this first nitrogenous copper alloy layer comprises copper and is selected from one of them nitro-alloy of group that molybdenum, tungsten, titanium, chromium, tantalum, indium, tin, aluminium, manganese form.
11. thin-film transistor as claimed in claim 8 is characterized in that, the thickness of this first nitrogenous copper alloy layer is between 200 to 500 dusts.
12. thin-film transistor as claimed in claim 8 is characterized in that, the thickness of this second nitrogenous copper alloy layer is between 200 to 500 dusts.
13. thin-film transistor as claimed in claim 8 is characterized in that, the thickness of this first bronze medal layer is between 1500 to 4000 dusts.
14. thin-film transistor as claimed in claim 8 is characterized in that, the thickness of this second bronze medal layer is between 1500 to 4000 dusts.
15. thin-film transistor as claimed in claim 8 is characterized in that, the thickness ratio of this first bronze medal layer and this first nitrogenous copper alloy layer is between 5 to 15.
16. thin-film transistor as claimed in claim 8 is characterized in that, the thickness ratio of this second bronze medal layer and this second nitrogenous copper alloy layer is between 5 to 15.
17. thin-film transistor as claimed in claim 8 is characterized in that, the gross thickness of this first bronze medal layer and this first nitrogenous copper alloy layer is between 2000 to 4000 dusts.
18. thin-film transistor as claimed in claim 8 is characterized in that, the gross thickness of this second bronze medal layer and this second nitrogenous copper alloy layer is between 2000 to 4000 dusts.
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| CNA2006101484407A CN101179029A (en) | 2006-11-09 | 2006-11-09 | Film transistor and its making method |
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| CNA2006101484407A CN101179029A (en) | 2006-11-09 | 2006-11-09 | Film transistor and its making method |
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| CN102254950A (en) * | 2011-07-12 | 2011-11-23 | 北京大学深圳研究生院 | Cuprous oxide thin film transistor and preparing method thereof |
| CN102832253A (en) * | 2011-06-14 | 2012-12-19 | 三星电子株式会社 | Thin film transistor, |
| CN103227208A (en) * | 2013-04-10 | 2013-07-31 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| CN103700704A (en) * | 2008-11-07 | 2014-04-02 | 株式会社半导体能源研究所 | Semiconductor device |
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| CN103700704B (en) * | 2008-11-07 | 2017-07-11 | 株式会社半导体能源研究所 | Semiconductor devices |
| CN103700704A (en) * | 2008-11-07 | 2014-04-02 | 株式会社半导体能源研究所 | Semiconductor device |
| US10158005B2 (en) | 2008-11-07 | 2018-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN102832253A (en) * | 2011-06-14 | 2012-12-19 | 三星电子株式会社 | Thin film transistor, |
| CN102254950B (en) * | 2011-07-12 | 2013-05-08 | 北京大学深圳研究生院 | Cuprous oxide thin film transistor and preparing method thereof |
| CN102254950A (en) * | 2011-07-12 | 2011-11-23 | 北京大学深圳研究生院 | Cuprous oxide thin film transistor and preparing method thereof |
| CN103943682A (en) * | 2013-01-21 | 2014-07-23 | 三星显示有限公司 | Thin-film transistor and display device having the same |
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| CN104716202A (en) * | 2015-04-03 | 2015-06-17 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method thereof, array substrate and display device |
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| CN104952932A (en) * | 2015-05-29 | 2015-09-30 | 合肥鑫晟光电科技有限公司 | Thin-film transistor, array substrate, manufacturing method of thin-film transistor, manufacturing method of array substrate, and display device |
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