CN101171545A - Computer readable mask shrink control processor - Google Patents
Computer readable mask shrink control processor Download PDFInfo
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- CN101171545A CN101171545A CNA2006800158432A CN200680015843A CN101171545A CN 101171545 A CN101171545 A CN 101171545A CN A2006800158432 A CNA2006800158432 A CN A2006800158432A CN 200680015843 A CN200680015843 A CN 200680015843A CN 101171545 A CN101171545 A CN 101171545A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
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Abstract
An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and length, shape modifications, etc. for forming features in a patterned layer.
Description
Technical field
The present invention relates to the formation of semiconductor devices.
Background technology
In semiconductor wafer treatment process, utilize patterning (patterning) and the etch processes known, in wafer, limit the feature (feature) of semiconductor devices.In these were handled, photoresist (PR) material was deposited on the wafer, was exposed to the light that is filtered by reticle mask (reticle) then.Reticle mask is generally glass plate, and it is formed with typical feature geometry pattern, and this geometric configuration can stop light to pass reticle mask.
After passing reticle mask, the surface of light contact lithograph glue material.Light changes the chemical composition of photoresist material, thereby makes developer part that can be removed photoresist material.Under the situation of eurymeric photoresist material, the exposure area is removed, and under the situation of negative photoresist material, unexposed area is removed.Then, etched wafer with the material below remove in the zone that no longer is subjected to the photoresist material protection, and limits the feature of expecting thus in wafer.
Known have many for the photoresist material.Deep ultraviolet (DUV) photoresist is exposed by 248nm light.For ease of understanding, Figure 1A is the cross sectional representation of the layer 108 on substrate 104, and has the photoresist layer 112 of patterning on ARL (anti-reflection layer) 110, and ARL 110 is positioned on the layer, and layer 108 is with etched formation heap 100.Photoresist pattern (pattern) has critical dimension (CD), and it can be the width 116 of this minimal characteristic.Owing to depend on the optical properties of wavelength, the photoresist that is exposed by longer wavelength light has bigger theoretical minimal critical dimensions.
By this photoresist pattern, feature 120 can be etched, shown in Figure 1B.Ideally, the CD of this feature (width of this feature) equals the CD 116 of feature in the photoresist 112.In practice, because the erosion or the undercutting (undercutting) of abrasion (faceting), photoresist, the CD 116 of feature may be bigger than the CD of photoresist 112.Feature also may be reduced gradually, and the CD of this feature CD with photoresist at least is the same big, but the feature that reduces gradually has width smaller near feature bottom.This reducing gradually may provide insecure feature.
For the feature that has less CD is provided, seeking a kind of feature of utilizing shorter wavelength to form.The photoresist of 193nm is by the light exposure of 193nm.Utilize phase shift reticles and other technology, use the photoresist of 193nm, can form the photoresist pattern of 90-100nm CD.This also can provide the feature with 90-100nm CD.The photoresist of 157nm is by the light exposure of 157nm.Utilize phase shift reticles and other technology, can form the CD photoresist pattern of inferior 90nm.This also can provide the feature with inferior 90nm CD.
Compare and use long wavelength, use the photoresist of shorter wavelength can bring other problem.For obtaining to approach the CD of theoretical limit, lithographic equipment should be more accurate, and this needs expensive more lithographic equipment.At present the photoresist of 193nm and the photoresist of 157nm do not have high selectivity as longer wavelength photoetching glue, and in plasma etch conditions easy deformation more.
In the conductive layer etching, for example in memory device formed, being desirably under the situation that does not reduce performance increased device density.
Fig. 2 A is the cross sectional representation of photoresist layer that is used to produce the patterning of lead according to prior art a kind of, and the interval between this moment line is too near.On substrate 204 (for example wafer), restraining barrier 206 can be set.On restraining barrier 206, form dielectric layer 208, for example metal level or polysilicon layer.On dielectric layer 208, form anti-reflection layer (ARL) 210, for example darc layer.The photoresist layer 212a of patterning forms on ARL 210.In this example, the photoresist line 214a of patterning has the width that is limited by line width " L " as shown in the figure.Interval 222 width " S " that have as shown in the figure.That pitch (pitch) length " P " is defined as line width and interval width and P=L+S, as shown in the figure.Expectation reduces pitch length.
A kind of method that reduces pitch width is by reducing interval width.Fig. 2 B is the cross sectional representation of photoresist layer that is used to produce the patterning of conduction or dielectric trench line according to prior art when the interval between line is too near.On substrate 204 (for example wafer), restraining barrier 206 can be set.On restraining barrier 206, form conduction or dielectric layer 208, for example metal level, polysilicon layer or dielectric layer.On dielectric layer 208, form anti-reflection layer (ARL) 210, for example darc layer.The photoresist layer 212 of patterning forms on ARL 210.In this example, the photoresist layer 212b of patterning forms the line 214b of patterning, and forms photoresist residual 218 in the interval between the line 214b of patterning.The existence of photoresist residual 218 is to be caused by the interval too small between the line 214b of patterning, because removal residual 218 is difficult more from little interval.This may limit the density of the lead that can be provided.
Summary of the invention
For reaching aforementioned and, providing a kind of device that comprises computer-readable medium according to purpose of the present invention.Computer-readable medium comprises the computer-readable code that is used to receive the computer-readable code of feature layout (featurelayout) and is used for feature layout is used shrink correct.
In the another kind of form of expression of the present invention, provide a kind of method that is used to form feature.Feature layout is received.Feature layout is carried out shrink correct, to form the mask layout of shrink correct.
Above-mentioned and others of the present invention will be described by following detailed description of the invention in conjunction with the accompanying drawings in more detail.
Description of drawings
Non-limitingly in the accompanying drawing show the present invention by example, in the accompanying drawings, the identical similar element of mark representative, wherein:
Figure 1A-B is the cross sectional representation through etched heap according to prior art;
Fig. 2 A-B is the cross sectional representation according to the photoresist layer of the patterning of prior art formation;
Fig. 3 is the high level flow chart of the processing that can use in one embodiment of the invention;
Fig. 4 A-H is the cross sectional representation of the heap (stack) handled according to an embodiment of the invention;
Fig. 5 is the process flow diagram that forms side wall layer on the photoresist layer of patterning;
Fig. 6 A-B has shown a kind of computer system, and it is suitable for the controller implementing to use in an embodiment of the present invention;
Fig. 7 is the top view of the photoresist layer of patterning;
Fig. 8 be when side wall layer after forming on the sidewall of the photoresist layer of patterning, the top view of the photoresist layer of the patterning of Fig. 7;
Fig. 9 is the process flow diagram that is used to provide the processing of reticle mask;
Figure 10 is the top view that the photoresist layer of the patterning of Fig. 7 has shrink correct;
Figure 11 is another process flow diagram that is used to provide the processing of reticle mask;
Figure 12 is the synoptic diagram that is used to provide the system of reticle mask;
Figure 13 is the top view of feature layout;
Figure 14 A-B is the top view of the patterned layer that limited by the reticle layout of utilizing reticle layout process to generate;
Figure 15 A-B is after shrink correct is provided, the top view of the patterned layer that is limited by reticle layout;
Figure 16 A is the top view from the photoresist layer of the patterning of first reticle layout generation;
Figure 16 B is after side wall layer forms, the top view of the photoresist layer of the patterning of Figure 16 A;
Figure 17 A is the top view from the photoresist layer of the patterning of second reticle layout generation;
Figure 17 B is after side wall layer forms, the top view of the photoresist layer of the patterning of Figure 17 A;
Figure 18 is after second stack features is etched, the top view of substrate.
Embodiment
Below in conjunction with some preferred embodiments that show in the accompanying drawings, describe the present invention in detail.In the following description, will illustrate many special details to provide to thorough understanding of the present invention.But, significantly, for a person skilled in the art, the present invention can not use in these specific detail some or all and be implemented.Under other situations, treatment step and/or the structure known do not specifically describe, to avoid unnecessarily obscuring the present invention.
The invention provides feature with little critical dimension (CD).More specifically, the invention provides feature, the CD of this feature is less than the CD of the photoresist pattern that is used for etch features.
For ease of understanding, Fig. 3 is the high level flow chart of the processing that can use in one embodiment of the invention.Reticle mask (step 304) is provided.This step will be described in more detail following.Form the photoresist layer (step 308) of patterning then.This step also will be described in more detail following.Fig. 4 A is the cross sectional representation of the photoresist layer of the patterning in the one embodiment of the invention.On substrate 404 (for example wafer), restraining barrier 406 can be set.On restraining barrier 406, form etch layer 408 (for example conductive metal layer or polysilicon layer or dielectric layer).On etch layer 408, form anti-reflection layer (ARL) 410 (for example darc layer).The photoresist layer 412 of first patterning forms on ARL 410.In this example, the line 414 of patterning has with line width " L
p" width that limits, as shown in the figure.Interval 422 in photoresist layer has width " S
p", as shown in the figure.Pitch length " the P of patterning photoresist layer
p" be defined as this line width and interval width and P
p=L
p+ S
p, as shown in the figure.These width are determined by the resolution of the photoetching technique of the photoresist layer that is used to form patterning.Expectation reduces pitch length.
On the photoresist layer of patterning, form side wall layer to reduce CD (step 312).Fig. 5 forms side wall layer to reduce the more detailed process flow diagram of CD (step 312), its using gases modulation on the photoresist layer of patterning.In this embodiment, on the photoresist layer of patterning, form side wall layer and comprise that to reduce CD (step 312) depositional phase 504 and profile are shaped (profile shaping) stage 508.Depositional phase uses the first aerochemistry composition to form plasma, and this plasma is the deposited sidewalls layer on the sidewall of the photoresist layer of patterning.Profile shaping stage 508 uses the second aerochemistry composition forming plasma, and the plasma sedimental profile that is shaped is to form the sidewall of perpendicular.
Fig. 4 B is the cross sectional representation of photoresist layer 412 of first patterning of patterning, and it has the side wall layer 420 on the photoresist layer sidewall that is deposited on first patterning.Side wall layer 420 forms sidewall layer feature 424 in the photoresist layer interval of patterning, wherein sidewall layer feature 424 has the interval CD that reduces less than the photoresist layer interval CD of first patterning.Preferably, the interval CD that reduces of the photoresist layer of first patterning of deposition is littler by 50% than the interval CD of the photoresist layer feature of first patterning.Expect that also side wall layer has the sidewall 428 of perpendicular, sidewall is similar to height as shown in the figure.An example of the sidewall of perpendicular is that sidewall from bottom to top becomes from 88 ° to 90 ° angle with the bottom of feature.Similar sidewall has sedimentary deposit, and sedimentary deposit has substantially the same thickness from the top of feature to the bottom.Non-similar sidewall can form the structure of abrasion (faceting) or bread bulk (bread-loafing), and these structures provide non-vertical substantially sidewall.(tapered) sidewall of taper (come from abrasion structure) or the sidewall of bread bulk can increase sedimentary deposit CD, and the photoresist layer of relatively poor etched patternization is provided.Preferably, the deposition on the photoresist layer feature bottom of the deposition rate on the sidewall at first patterning is thicker.More preferably, do not have on layer bottom of the photoresist layer feature that is deposited over first patterning.
Then, the first feature group is etched in the etch layer 408 (step 316) by sidewall layer spaces.Fig. 4 C has shown the first feature group 432 that etches in the etch layer 408.In this example, the etched first feature group 432 has the CD width in etch layer 408, and the CD width equates with the interval CD of deposition layer features.In actual applications, the CD of feature can be slightly larger than the CD of sedimentary deposit 420 features in the first feature group 432.But, because the CD of deposition layer features is significantly less than the CD of photoresist 412, so the CD of the feature in etch layer 408 is still less than the CD of photoresist 412.If the CD of sedimentary deposit only is the CD that is slightly less than photoresist, if perhaps sedimentary deposit is denuded or bread blocking (breadloafed), so with the CD of etched layer may not can less than the CD of photoresist.In addition, the abrasion or the sedimentary deposit of bread blocking can cause feature abrasion or irregular shaping in will etched layer.Also expectation minimization is in the deposition of photoresist feature bottom.In this example, will be etched in the layer 408 CD of etched feature littler by about 50% than the CD of photoresist feature.
Then, the photoresist layer of patterning and sedimentary deposit are divested (step 320).This can be used as a step and finishes, and also can be used as two separation steps and finishes, and comprises the deposited layer removal step and the photoresist strip step of separation.Ashing (ashing) can be used for strip process.Fig. 4 D has shown the substrate 400 after sedimentary deposit and photoresist layer are removed.
To whether additional feature will etchedly be determined (step 324).In this example, second set of etch features is etched.Therefore, provide second reticle mask (step 304).Provide the processing of this reticle mask will be in following more detailed description.Go up the photoresist layer (step 308) that forms second patterning in this etched feature (being first set of etch features under this situation).Fig. 4 E has shown substrate 404, wherein the photoresist layer 442 of second patterning forms on etch layer 408, wherein the photoresist layer 442 of second patterning covers the first feature group 432, and the interval in the photoresist layer of second patterning 444 is formed between first set of etch features 432.
Then, deposited sidewalls layer on the sidewall of the photoresist layer feature of second patterning is to reduce CD (step 312).Fig. 4 F is the cross sectional representation of the photoresist layer 442 of second patterning, and wherein side wall layer 450 is deposited on the sidewall of photoresist layer 442 of second patterning.Side wall layer 450 forms sidewall layer feature 454 in the photoresist layer interval of patterning, wherein sidewall layer feature 454 has the interval CD that reduces less than the photoresist layer interval CD of second patterning.Preferably, the interval that reduces of sidewall layer feature is littler by 50% than the interval CD of the photoresist layer feature of second patterning.The sidewall of the photoresist layer feature 422 of desired patternization with perpendicular also, sidewall is similar to height as shown in the figure.An example of the sidewall of perpendicular is that sidewall from bottom to top becomes from 88 ° to 90 ° angle with the bottom of feature.Preferably, thicker in the deposition of the deposition rate on the sidewall on the photoresist feature bottom.More preferably, there is not layer to be deposited on the bottom of photoresist feature.
Shown in Fig. 4 G, feature is etched into etch layer (step 316), forms second set of etch features 452 between first set of etch features 432.The photoresist layer of patterning and sedimentary deposit are divested (step 320) then, shown in Fig. 4 H.The line width of etch layer is L as shown
fSignificant interval width in the etch layer is S as shown
fThe pitch length of this feature as shown is P
f, P wherein
f=L
f+ S
fIn order to contrast, with the photoresist layer pitch P of the patterning among Fig. 4 A
p, photoresist line width L
p, and photoresist S at interval
pBe presented among Fig. 4 G, with feature pitch P
f, characteristic curve width L
f, and significant interval width S
fCompare.In this embodiment, the length P of feature pitch
fPhotoresist layer pitch length P for patterning
pHalf because the line width L between the feature
fPhotoresist layer line width L for patterning
pHalf, and significant interval width S
fBe interval S in the photoresist layer of patterning
pHalf.Therefore, by the pitch length that reduces by half, line width and characteristic width, but utilize identical photoresist photoetching treatment, this processing can use two masks to make the etch features double resolution.In this example, first set of etch features that comes from the photoresist layer of first patterning is etched to and the identical or about identical degree of depth of second set of etch features of the photoresist layer that comes from second patterning, as shown in the figure.
Because this embodiment only uses the photoresist layer of two patternings, locate at repeating step (step 336), determine not repeat this processing (step 324).
Shrink correction processor
Fig. 7 is the top view of the photoresist layer 704 of patterning.The opening features 720 that the photoresist layer of this patterning provides three thin rectangular apertures 708, had the big rectangular aperture 712 of oval part 716 and have circular portion 724.Fig. 8 be when side wall layer after forming on the sidewall of the photoresist layer 804 of this patterning, the top view of the photoresist layer 804 of patterning.Should be noted that these sidewalls do not reduce CD obtaining to have the same characteristic features of uniform reduced size in the mode of homogeneous, but as shown in Figure 8,, have different CD contraction deviations for the different sizes and the feature of shape according to the width and the Butut of feature.As can be seen from Figure 8, the line of different interval can differently shrink.In addition, it is circular that circular portion 824 can keep, and oval part 816 is amplified more along its major axis than minor axis.In addition, the turning of line 808 all is exaggerated at x axle and y direction of principal axis, so these turnings are bigger than the sidewall growth of line, thereby forms circular projection 832.For similar reason, other turning forms other circular projection 836.
Expectation provides a kind of reticle mask, and this reticle mask provides the photoresist layer of patterning, and when being covered by side wall layer, the photoresist layer of this patterning produces has the feature of the CD that reduces, revises with how much dependences to this shrink process.
Fig. 9 provides the process flow diagram of reticle mask (step 304).Feature layout is provided (step 904).Produce reticle layout (step 908) by feature layout.Middle mask layout is carried out shrink correct (step 912).Figure 10 is the top view of photoresist layer 1004 with patterning of shrink correct.A shrink correct rule provides the interval 1036 of amplification at each turning of Butut.In addition, the relative scale of feature is changed.For example, the thickness of oval part 1016 increases, but does not increase the length of oval part 1016.
Usually have a kind of phenomenon that line shortens that is referred to as in current photoetching and etch processes, photoetching treatment shortens the photoresist line of patterning in this phenomenon.Litho rounds the edge of photoresist line of patterning, therefore need optics to close on correction (OPC) to revise.And in etching, the end of patterned lines is easier to be exposed in the sputter, therefore becomes shorter.In G-pattern (G-mode), cambium layer on the line of patterning, this makes the line of patterning bigger, and the feature between the line is littler.So under the situation of not using OPC, can use shrink correct to shorten with compensation photoetching line.Therefore, can use shrink correct eliminating or to minimize OPC, and eliminate the necessity that is used for solving the feature that shortens at (account for) line edge.
Produce reticle mask (step 916) by this reticle layout that has shrink correct then.
A plurality of reticle masks generate
In the example shown in above-mentioned Fig. 4 A-F, when using two etch processes, need the photoresist layer of the patterning of at least two separation at least, reticle mask and alignment issues should be emphasized.In this example, if be used for being shifted at the reticle mask that first etching forms the photoresist layer of patterning half of (moving) about pitch, then reticle mask can be used for second etching.When using conventional case raising middle flask (box-in-box) alignment scheme, the aligning of the photoresist layer of two patternings (when using identical reticle mask to be used for first and second exposures) can become problem.For example, at first mask with after shrinking, the size of alignment box reduces about 200nm, the size that it equals line and shrinks at interval.Now, if the photoresist layer of second patterning with respect to original line and spacer knobs apart from displacement 200nm to realize the half-section distance, the aligning of the photoresist layer of second patterning 400nm that in fact has to be adjusted so.Usually, lithography tool is designed to aim at these alignment marks (alignment key), is variation in the conventional method and implement non-aligned, and it may become the root of chaotic and potential a large amount of yield rate losses.All need carry out because aim to be adjusted on X and the Y direction, so this problem increases.
In addition, the aligning of succeeding layer (being generally hole (contact or through hole)) has further difficulty.Because alignment mark has two edges, promptly shrink relevant inward flange and owing to second edge of second contraction with first.This can influence alignment algorithm, even can be aligned algorithm and misread, and alignment algorithm must be with hole and line and spaced-apart alignment.In addition, because these edges is close to each other, double edge can reduce the sensitivity of aligning.For the minimum CD that needs shrink (being a few tenths of of nm) in a small amount, it is bad more that this sensitivity problem (being fuzzy edge) can become, and this situation lower limb almost is mixed with each other, and therefore sharp keen edge becomes and do not exist.
In addition, the application that produces pattern is more more complicated than producing the equal parallel lines of a plurality of homogeneous spacing dimensions, and therefore comparing the simple shift reticle mask need carry out more multioperation.
Figure 11 is when using an above etching, and the process flow diagram of reticle mask (step 304) is provided.Feature layout (step 1104) is provided, produces at least two reticle layout (step 1108) by feature layout.On each of this at least two reticle layout, carry out shrink correct (step 1112).Produce at least two reticle masks (step 1116) by at least two reticle layout that have shrink correct.
Example
Utilize the example of the system of one embodiment of the present of invention, system 1200 as shown in figure 12 is used to be provided for the reticle mask that many mask etchings are handled, and is used to be provided for shrinking the verification that control law is revised.Produce and/or submit to the feature layout (step 1104) of feature placement at Butut 1204 places.Reticle layout 1208 among this embodiment produces at least two reticle layout (step 1108) to use by this feature layout in many etch processes.This reticle layout needs and can produce a plurality of reticle masks and can be according to the computer code that the shrink process that is used is amplified this feature by feature layout.
For helping to produce the additional shrink correction rales that is used for this shrink correction processor, the test chip Butut can be produced, and perhaps reticle data 1216 can be used for producing test chip Butut 1234.The test chip Butut is printed on the wafer 1236, to form the photoresist layer of patterning on test chip.Cambium layer 1237 on the photoresist layer of patterning, to form side wall layer on the photoresist layer of patterning.Carry out line width then and measure 1238.In one embodiment, to measure can be measurement to the photoresist layer of the patterning that has side wall layer to line width.In another embodiment, carry out etching, on etched feature, measuring then.Provide these to measure as input to empirical model engine 1260 and parameter extraction engine 1240.The output of empirical model engine is used to produce empirical model 1264, and empirical model 1264 is used to provide improved rules to shrink correction processor 1212.
In addition, utilize parameter extraction engine 1240 to form physical model, produce physical model 1244 to extract processing parameter from the identical data centralization that is used for empirical model.Mask layout verification (MLV) 1220 compares reticle data 1216 with physical model 1244.If should be more insufficient, then data be offered empirical model engine 1260 near 1224.The output of this empirical model engine is used to produce empirical model 1264, and it is used to provide improved rules to shrink correction processor 1212.Shrink correction processor 1212 provides new reticle data 1216 then.If should be more fully near 1224, then reticle data can be used for forming reticle mask 1280 (step 304).This reticle mask is used to form the photoresist layer 1281 (step 308) of patterning.On the photoresist layer 1282 of patterning, form side wall layer (step 312).Feature is etched into etch layer (step 316) to make chip 1284 by the photoresist layer of this patterning.
Can use multiple other processing, produce a plurality of reticle masks and use this with the application characteristic Butut and shrink correction to reticle layout.For example, can carry out shrink correct, and the tabulation of shrink correction features and characteristic thereof is provided to the user.The user can import the criterion (guideline) that is used to revise then.In another embodiment, can at first make data reticle mask band.Then shrink correct is applied to the data on the data reticle mask band, this will provide the tabulation of feature and characteristic thereof to the user.The user can import the criterion that is used to revise then.Can provide this correction hereof then.These processing can be by more automated method replacement.In another modification, this criterion that is used to revise is by pre-sequencing, and this SCPP can be applied to them Butut and reticle files automatically.
Fig. 6 A and 6B have shown computer system 600, its this feature layout of reception that is suitable for using in an embodiment of the present invention, produce reticle mask and carry out shrink correct.Fig. 6 A has shown a kind of possible physical form of computer system.Certainly, computer system can have multiple physical form, from integrated circuit, printed circuit board (PCB) and little handheld device, to huge super computer.Computer system 600 comprises display 602, display 604, frame 606, disk drive 608, keyboard 610 and mouse 612.Disk 614 is a computer-readable medium, and it is used for Data transmission to computer system 600 and from computer system 600 Data transmission.
Fig. 6 B is the example that is used for the block scheme of computer system 600.What be connected to system bus 620 is various subsystems.Processor 622 (be also referred to as CPU (central processing unit), or CPU) be connected with memory device (comprising storer 624).Storer 624 comprises random-access memory (ram) and ROM (read-only memory) (ROM).Know in this area, ROM is used for the uniaxially Data transmission and instructs CPU, and RAM typically is used for two-way mode Data transmission and instruction.The storer of these and other type can comprise any type of computer-readable medium described below.Fixed disk 626 is connected with CPU 622 also two-wayly; It provides additional data storage capacities, and also can comprise any computer-readable medium described below.Fixed disk 626 can be used for stored programme, data etc., and is generally secondary storage media (for example, hard disk), and its speed is slower than primary memory.Should be appreciated that under the suitable situation, the information that keeps can be used as virtual memory and is integrated into storer 624 with the form of standard in fixed disk 626.Packaged type disk 614 can adopt the form of following any computer-readable medium.
In addition, embodiments of the invention further relate to the Computer Storage product with computer-readable medium, have the computer code that is used to carry out the operation that multiple computing machine carries out on the computer-readable medium.This medium and computer code can design especially and make up for purpose of the present invention, and perhaps they can be to know for the technician of computer software fields and available type.The example of computer-readable medium includes, but are not limited to: magnetic medium, for example hard disk, floppy disk and tape; Optical medium, for example CD-ROM and hologram device; Magnet-optical medium, but the disk read of light for example; And be configured to store hardware device with the executive routine code, for example specialized application integrated circuit (ASIC), programmable logic device (PLD) (PLD) and ROM and RAM device especially.The example of computer code comprises machine code, for example produces by compiler, and the file that comprises higher level code, the higher level code file is carried out by the computing machine that uses interpretive routine.Computer-readable medium can also be a computer code, and computer code is by the computer data signal transmission that is embodied as the instruction sequence that carrier wave and representative can be carried out by processor.
The example Butut
In the instantiation of the processing of use Figure 11 in system, as shown in figure 12, at first provide feature layout (step 1104) 1204.Figure 13 is the top view of feature layout, and this feature layout has shown and had and will be etched into the characteristic pattern 1304 of the feature 1308 of wafer.Feature layout pitch P
FBe the minimum pitch between the feature of this feature layout, as shown in the figure.Feature layout is provided to reticle layout processor 1208, and it produces at least two (a plurality of) reticle layout (step 1108) from feature layout.
For the course of work of one embodiment of the invention is shown, schematically illustrate following content.Figure 14 A and 14B are the top view of the layer of the patterning that limited by first reticle layout 1404 and second reticle layout 1408, and first reticle layout 1404 and second reticle layout 1408 produce (step 1108) by using reticle layout process.The layer that should be noted that the patterning that is limited by first reticle layout 1404 has the feature of lacking than feature pattern 1304 features 1424, and has the feature 1424 bigger than the feature of feature pattern, and has the less pattern lines between feature 1424.Similarly, the layer of the patterning that is limited by second reticle layout 1408 has the feature of lacking than feature pattern 1304 features 1428, and has the feature 1428 bigger than the feature of feature pattern.In addition, the layer of the patterning that is limited by first reticle layout 1404 has an aligned pattern 1434, and the patterning that is limited by second reticle layout 1408 layer has two aligned pattern 1438.The aligned pattern 1434 of an aligned pattern coupling on the layer of the patterning that limits by first reticle layout 1404 of the layer of the patterning that the layer of the patterning that is limited by second reticle layout 1408 limits, and the patterning that limits by second reticle layout 1404 layer another aligned pattern do not match the patterning that limits by first reticle layout 1404 layer on any aligned pattern.The layer of the patterning that is limited by first reticle layout has the first reticle layout pitch P
M1, it is the minimum pitch between the feature of the layer of the patterning that is limited by first reticle layout, shown in Figure 14 A.The layer of the patterning that is limited by second reticle layout has the second reticle layout pitch P
M2, it is the minimum pitch between the feature of the layer of the patterning that is limited by second reticle layout, shown in Figure 14 A.Shown in Figure 14 A and 14B, the first reticle layout pitch P
M1With the second reticle layout pitch P
M2Each is at least feature layout pitch P
FTwice.This allows some leeway for the photoetching that has restriction minimum pitch (limitingminimum pitch), is not more than half the feature layout of pitch of this restriction minimum pitch to provide to have, thereby the resolution of photoetching is improved twice at least.
First reticle layout and second reticle layout are submitted to shrink correction processor 1212, so that these at least two reticle layout are carried out shrink correct (step 1112).Figure 15 A is after carrying out shrink correct, the top view of the layer of the patterning that is limited by first reticle layout 1504.Provide corner cutouts 1544 at the turning of reticle mask, to solve (account for) relatively large contraction at the turning.Figure 15 B is after carrying out shrink correct, the top view of the layer of the patterning that is limited by second reticle layout 1508.Provide corner cutouts 1548 at the turning of reticle mask, to solve relatively large contraction at the turning.The shrink correct rule that is used for providing corner cutouts can be of a plurality of rules of being provided by shrink correction processor 1212.
At least two reticle masks produce (step 1116) by these at least two reticle layout that have shrink correct.The part of this step can be undertaken by producing reticle data 1216.Can on reticle data, carry out mask layout verification 1220.If the mask checking data indicates this reticle data correct, then form reticle mask by reticle data.
Use first reticle mask to form the photoresist layer (step 308) of first patterning.Figure 16 A is the top view of photoresist layer 1604 that comes from first patterning that reticle mask produced of first reticle layout 1504 after the shrink correct 1504.The pitch P of the photoresist layer 1604 of first patterning
P1It is the minimum pitch between photoresist layer 1604 features of first patterning.Side wall layer forms (step 316) on the photoresist layer of patterning.Figure 16 B is after side wall layer has formed with the shrinkage characteristic size, the top view of the photoresist layer 1608 of patterning.Characteristic dimension is reduced.Otch allows shrink process to form the turning, but not forms circular projection.Substrate is etched then, feature is etched into (step 316) in the substrate.The photoresist layer of patterning is divested (step 320) then.
Utilize second reticle mask to repeat this processing (step 324) then, wherein second reticle layout 1508 of second reticle mask after by shrink correct provides (step 304).Second reticle mask is used for forming on the formerly etched feature photoresist layer (step 308) of second patterning.Figure 17 A is the top view that the formerly etched first feature group 1712 (being shown as dotted line) goes up the photoresist layer 1704 of the patterning that forms.The pitch P of the photoresist layer 1704 of second patterning
P2It is the minimum pitch between the feature of photoresist layer 1704 of second patterning.Side wall layer forms (step 316) on the photoresist layer of patterning.Figure 17 B has formed with after shrinking this characteristic dimension the top view of the photoresist layer 1708 of patterning when side wall layer.This characteristic dimension is reduced.Otch allows this shrink process to form the turning, but not forms circular projection.Substrate is etched then, feature is etched into (step 316) in the substrate.The photoresist layer of this patterning is divested (step 320) then.
Figure 18 is the top view of the etched meron of the second feature group.In substrate, be to utilize the photoresist layer etched first feature group 1712 of institute of first patterning come from first reticle mask and the etched second feature group 1812 of photoresist layer that utilization comes from second patterning of second reticle set.The part of the first feature group 1712 is adjacent to the part of the second feature group 1812, with pitch and the resolution that increase is provided.The pitch P of feature
FIt is the minimum pitch between the feature.As shown in the figure, the pitch P of the substrate of the second feature group after etched
FBe not more than the pitch P of the photoresist layer of the photoresist layer of first patterning and second patterning
PHalf.
Relation between the photoresist layer of first and second patternings be different from dual damascene (dualdamascene) handle in relation between the photoresist layer of groove and through-hole patternization, in dual damascene process, trench features is not adjacent to the through hole feature with the increase pitch, but is positioned on the through hole feature to form dual-damascene structure.In addition, the first feature group is etched to the approximately identical degree of depth with the second feature group, and wherein groove is not etched to the approximately degree of depth identical with through hole.But the photoresist layer that the treatment process of this innovation can use first and second patternings has the through hole of the pitch of increase with generation, perhaps uses the photoresist layer of first and second patternings to have the groove of the pitch of increase with formation.Feature in this example has about twice pitch of the pitch resolution of lithographic process.Second alignment characteristics 1808 allows improved aligning to be used for next and handles rank.
In test and/or development process, the substrate after first etching or second etching may experience line width and measure 1238, and data can flow to empirical model 1260 and/or parameter extraction engine 1240.Empirical model 1260 provides a kind of empirical model, and this empirical model can provide ancillary rules to handle to improve this shrink correct to shrink correction processor 1212.Parameter extraction 1240 provides a kind of physical model, and it is used for mask layout verification 1220.These methods have been improved the shrink correct processing.
In an optional embodiment, the generation of reticle layout can form the feature identical with the characteristic dimension of characteristic pattern, can use the size of shrink correct rule with the increase feature then, and reduces the size of the line of patterning.In another embodiment, reticle layout 1208 and shrink correct 1212 can be carried out in single step, to produce a plurality of reticle layout and carry out shrink correct in one step, but still can be shown as two steps in order knowing.
Some difference of shrink correct and OPC are as follows: middle mask is carried out OPC, so that the photoresist layer of resulting patterning is formed the feature of similar expectation.Middle mask is carried out shrink correct, so that the photoresist layer of resulting patterning is different with the feature of expectation, but instead, shrink correct makes the photoresist layer of resulting patterning more different with final feature.The formation of follow-up side wall layer makes the photoresist layer of patterning form the feature of similar expectation.Carry out OPC so that the photoresist layer of more high-resolution patterning to be provided.And carry out shrink correct is that photoresist layer for the patterning that makes low resolution produces high-resolution result on wafer.OPC provides rule to add the photoresist material, with the loss of compensation additional materials in the photoresist layer process that forms patterning.Shrink correct provides rule, and it removes additional materials, with the increase of compensation material in forming the side wall layer process.
In various embodiments, can be measured through etched feature, so that the contraction control information to be provided, perhaps after forming side wall layer, the feature of the photoresist layer of patterning can be measured, so that the contraction control information to be provided.These measurements can be compared with feature layout or reticle layout.
Some treatment process once used first reticle mask so that dense feature to be provided, and used second reticle mask so that the feature of more isolating to be provided.To the requirement of these reticle masks be because dense feature need be different with isolation characteristic exposure or photoresist.Instead, under the situation of utilization and identical lithography tool and photoresist, use shrink correct and form a plurality of reticle masks to be used in some dense feature of formation on the reticle mask, and on another reticle mask, form dense feature and isolation characteristic simultaneously.
Other embodiments of the invention can be used the reticle mask more than two.For example, can use three reticle masks so that the pitch of feature layout be each reticle mask pitch 1/3rd.In another example, can use four reticle masks, so that the pitch of feature layout is 1/4th of each reticle mask pitch.The application people that this many mask process technology was submitted on February 3rd, 2005 is called the Application No. 11/050 of " Reduction of Feature Critical Dimensions Using Multiple Masks (utilizing many masks to reduce feature critical dimensions) " for Jeffrey Marks and Reza Sadjadi, name, describe in 985, be all purposes, it is incorporated into the application by reference.
Although described the present invention according to several preferred embodiments, have the equivalent way of change, displacement and plurality of replaceable, this all falls within the scope of the present invention.Should be noted that the alternate ways that has multiple enforcement the inventive method and device.Therefore, appended claim is intended to be interpreted as comprising that all fall into the equivalent way of these changes, displacement and plurality of replaceable in purport of the present invention and the scope.
Claims (14)
1. device that comprises computer-readable medium comprises:
Be used to receive the computer-readable code of feature layout; And
Be used for described feature layout is used the computer-readable code of shrink correct.
2. device according to claim 1 further comprises being used for resulting testing wafer and described feature layout are compared, and based on the described computer-readable code that relatively generates the shrink correct rule.
3. device according to claim 2 comprises that further the described shrink correct rule application that is used for generating is in the computer-readable code of described feature layout.
4. according to the described device of claim 1 to 3, wherein, the described computer-readable code that is used for described feature layout is used described shrink correct comprises:
Be used for generating a plurality of reticle layout from described feature layout, and to institute
State a plurality of reticle layout and use the computer-readable code of shrink correct.
5. according to the described device of claim 1 to 4, wherein, be used for the computer-readable code that described feature layout is used shrink correct comprised being used to provide corner cutouts to form the computer-readable code of feature at patterned layer.
6. according to the described device of claim 1 to 5, wherein, the described computer-readable code that is used to use shrink correct further comprises the size calculation machine readable code of the patterning layer line that is used to reduce described patterned layer.
7. method comprises:
Receive feature layout; And
Described feature layout is carried out shrink correct, to form the reticle layout of shrink correct.
8. method according to claim 7, wherein, the described shrink correct of described execution comprises the corner cutouts that is provided for forming feature in reticle mask.
9. according to the described method of claim 7 to 8, further comprise:
Based on the reticle layout of described shrink correct, on wafer, form pattern
Change layer, wherein, described patterned layer has corner cutouts; And
On described patterned layer, form side wall layer.
10. method according to claim 9 comprises that further the reticle layout based on described shrink correct forms reticle mask, and wherein, described formation patterned layer uses the described reticle mask based on the reticle layout of described shrink correct.
11., further comprise feature is etched in the substrate that is arranged on described patterned layer below according to the described method of claim 9 to 10.
12. method according to claim 11 further comprises etched feature and described feature layout are compared, and based on the comparison of described etched feature and described feature layout, generates and shrink control law.
13. according to the described method of claim 7 to 11, wherein, describedly on described feature layout, carry out shrink correct, comprising:
Generate a plurality of reticle layout from described feature layout; And
Each execution shrink correct to described a plurality of reticle layout.
14. according to the described method of claim 7 to 13, wherein, carry out the use that OPC was eliminated or minimized to described shrink correct, and wherein, carry out described shrink correct and eliminated the necessity that is used to solve the feature that shortens at the line edge.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/126,708 | 2005-05-10 | ||
| US11/126,708 US7539969B2 (en) | 2005-05-10 | 2005-05-10 | Computer readable mask shrink control processor |
| PCT/US2006/017067 WO2006121741A2 (en) | 2005-05-10 | 2006-05-02 | Computer readable mask shrink control processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101171545A true CN101171545A (en) | 2008-04-30 |
| CN101171545B CN101171545B (en) | 2014-09-03 |
Family
ID=37003360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200680015843.2A Expired - Fee Related CN101171545B (en) | 2005-05-10 | 2006-05-02 | Computer readable mask shrink control processor |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US7539969B2 (en) |
| JP (2) | JP2008541171A (en) |
| KR (1) | KR101290617B1 (en) |
| CN (1) | CN101171545B (en) |
| MY (1) | MY139989A (en) |
| TW (1) | TWI502281B (en) |
| WO (1) | WO2006121741A2 (en) |
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| CN112255883A (en) * | 2020-11-12 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | Method for improving perpendicularity of photoetching pattern |
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-
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- 2006-05-02 WO PCT/US2006/017067 patent/WO2006121741A2/en active Application Filing
- 2006-05-02 CN CN200680015843.2A patent/CN101171545B/en not_active Expired - Fee Related
- 2006-05-02 JP JP2008511179A patent/JP2008541171A/en active Pending
- 2006-05-08 TW TW095116252A patent/TWI502281B/en not_active IP Right Cessation
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112255883A (en) * | 2020-11-12 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | Method for improving perpendicularity of photoetching pattern |
| CN112255883B (en) * | 2020-11-12 | 2023-11-24 | 上海华虹宏力半导体制造有限公司 | Method for improving perpendicularity of photoetching pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2012238890A (en) | 2012-12-06 |
| JP2008541171A (en) | 2008-11-20 |
| TW200710558A (en) | 2007-03-16 |
| CN101171545B (en) | 2014-09-03 |
| TWI502281B (en) | 2015-10-01 |
| WO2006121741A2 (en) | 2006-11-16 |
| MY139989A (en) | 2009-11-30 |
| KR20080005548A (en) | 2008-01-14 |
| KR101290617B1 (en) | 2013-08-08 |
| US7539969B2 (en) | 2009-05-26 |
| WO2006121741A3 (en) | 2007-02-15 |
| JP5680595B2 (en) | 2015-03-04 |
| US20060259886A1 (en) | 2006-11-16 |
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