CN101163978B - Testable electronic circuit, test method and tester - Google Patents
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- CN101163978B CN101163978B CN2006800038093A CN200680003809A CN101163978B CN 101163978 B CN101163978 B CN 101163978B CN 2006800038093 A CN2006800038093 A CN 2006800038093A CN 200680003809 A CN200680003809 A CN 200680003809A CN 101163978 B CN101163978 B CN 101163978B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
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Abstract
An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). The test control circuit (16) is coupled to control the clock multiplexing circuit (15a-c, 18) dependent on the mode assumed by the test control circuit (16). The clock multiplexing circuit (15a-c, 18) is arranged to substitute clock signals from respective ones of the data terminals (l la-c) temporarily at the clock inputs of respective ones of the groups (12a-c) in the test normal mode.
Description
Technical field
The present invention relates to a kind of electronic circuit, be specifically related to a kind of measurable integrate circuit that comprises a plurality of clock zones.The invention still further relates to a kind of tester apparatus that is used for the method that this electronic circuit is tested and is used for this electronic circuit is tested.
Background technology
U.S. Patent number 6,131,173 disclose a kind of measurable integrate circuit that comprises a plurality of clock zones.Along with the increase of current integrated circuit size, the functional circuit of integrated circuit is divided into different clock zones has become necessary.During normal running, this integrated circuit uses on a plurality of parts or whole clock signals independently, with the circuit operation in the control different clock-domains.Typically, integrated circuit comprises a plurality of internal clock circuits, so that produce most different clocks signal in inside.For example, typical clock circuit can comprise pierce circuit or PLL circuit, so that produce the clock signal that for example locks onto reference signal.
The use of different clock-domains makes to the test of integrated circuit difficult more.Operation can cause unpredictable relative timing in the time of different clocks signal (the especially inner clock signal that produces), and this can cause unpredictable test result.
At this problem, designed multiple solution.For example, US6,131,173 disclose and how to use the clock zone buffer circuit that the functional circuit of different clock-domains is isolated mutually, to avoid unpredictable test result.Other solutions comprise: the special test clock signals in entire circuit under the use test pattern, perhaps use the particular interface between the different clock-domains, to realize predictable sequential etc.
This solution has realized predictable test result, but often is to be cost with the sizable circuit overhead of circuit in the test.These solutions make and are difficult to carry out distinguishing " (at speed) at full speed " test this test is used for determining whether different circuit parts can make data available in each different delay interval.
Summary of the invention
Wherein, the objective of the invention is to reduce the electronic circuit that comprises a plurality of clock zones is tested required circuit overhead amount.
Wherein, the objective of the invention is to increase degree of control to the clock signal in the electronic circuit in the test.
In claim 1, ask for protection according to integrated circuit of the present invention.According to the present invention, when integrated circuit when test period is caught test result, the outside terminal that temporarily will be used to move into the integrated circuit of test data is reused for to catch to the time of test result provides clock signal.Typically, at test period, each outside terminal is used for providing clock signal to the part of circuit, and the part of this circuit provides clock by each internal clock circuit usually.When moving into test data, preferably use single test clock to provide clock signal, to move into test data to all these circuit.In this manner, during sequential key (timing critical) part of test, be available to the external control completely of different clocks signal, do not need a large amount of additional outside terminals that clock signal is provided.
Description of drawings
By with reference to the following drawings, and use non-limiting example, these and other purposes of the present invention and favourable aspect are described.
But Fig. 1 shows test circuit.
Fig. 2 shows clock switch circuit.
Fig. 3 shows test macro.
Fig. 4 shows test signal.
Embodiment
But Fig. 1 shows test circuit, but should comprise functional circuit 10, trigger group 12a-c, boundary scan cell 13a-f, clock circuit 14a-c, the first clock switch circuit 15a-c, test control circuit 16 and second clock commutation circuit 18 by test circuit.Preferably, but the element of test circuit be integrated in the integrated circuit.In typical embodiment, in normal (non-test) operating period, trigger 12a-c and functional circuit 10 1 biconditional operations, functional circuit 10 includes only combinational logic circuit (not having trigger).
Can think that but test circuit comprises data stream part, clock stream part and test control section.Data stream partly has input end 11a-c and output terminal 19a-c (the outside input that typically all is integrated circuit is connected).Each input end 11a-c is connected to boundary scan input block 13a-c separately, and boundary scan input block 13a-c is connected to the input end of trigger group 12a-c separately.The output terminal of each trigger group 12a-c is connected to output boundary scan cell 13d-f separately, and output boundary scan cell 13d-f is connected to output terminal 19a-c separately.
In the clock stream part, trigger group 12a-c receives separately clock signal from separately the first clock switch circuit 15a-c.The first input end of each among the first clock switch circuit 15a-c all is connected with separately clock circuit 14a-c, and second input end is connected with second clock commutation circuit 18.First input end of clock of second clock commutation circuit 18 is connected to the test clock input end 17a of test interface 17, and the second clock input end is connected to input end 11a-c separately.
The test interface 17 of test control section (the outside input that typically is integrated circuit connects) is connected to test control circuit 16.For example, this test interface can be traditional scan control interface, comprise that the TCK that is used for test clock connects, the TDS that the TDO that the TDI that is used to test the input data connects, be used to test output data connects, be used to test control connects and the RST that is used to reset connects.The output terminal of test control circuit 16 be connected to the first clock switch circuit 15a-c the control input end, be connected to trigger group 12a-c the control input end, be connected to second clock commutation circuit 18 and boundary scan cell 13a-f.
In normal feature operation, test control circuit 18 is switched to functional status, wherein test control circuit 18 makes each trigger (not shown) among the trigger group 12a-c provide numerical data to functional circuit 10, simultaneously from functional circuit 10 catches digital data.But such feature operation of test circuit itself is known, therefore is not described in detail.
During this normal feature operation, control the sequential that the trigger of each trigger group 12a-c is caught and/or provided by each clock circuit 14a-c.At first, each clock switch circuit 14a-c is set to, and selectively transmits from the clock signal of each clock circuit 14a-c or from the clock signal of second clock commutation circuit 18.
In normal function operating period, test control circuit 16 provides control signal to the first clock switch circuit 15a-c, with the trigger that is delivered to trigger group 12a-c from the clock signal of clock circuit 14a-c.For this reason, for example each first clock switch circuit 15a-c comprises multiplex electronics, and the multiplexed input end of this circuit is connected to clock circuit 15a-c and second clock commutation circuit 18, and the control input end of this circuit is connected to test control circuit 16.
As example, external input terminals 11a-c and output terminal 19a-c have been shown only have been connected to trigger group 12a-c, therefore in normal function operating period, providing and/or catching of numerical data is provided for specific single trigger (not shown) and outside output terminal 19a-c and/or output terminal 19a-c.Yet in normal function operating period, functional circuit 10 can also be directly connected to external input terminals 11a-c and/or output terminal 19a-c, to receive and/or to provide numerical data.For the sake of clarity, omitted such connection in the accompanying drawing, but should be understood that such connection can exist.
Under the control of test interface, but test circuit can be switched to test pattern.Under test pattern, test control circuit 18 is supported test displaced condition and test normal condition.The state of these types, and be known to the control of the switching between these states itself, therefore be not described in detail.For example, in one embodiment, test control circuit 18 comprises the state machine that can take (assume) different conditions and appropriate control signals is provided in each state, whether and when switch to another state from a state from the control signal control state machine of interface 17.
In the test displaced condition, the trigger among the test control circuit 18 (see figure 2)s control trigger group 12a-c, so each group among the trigger group 12a-c all is used as serial shift register separately.Circuit among the trigger group 12a-c is provided with supports that this operation itself is known, therefore is not described in detail.Under displaced condition, test control circuit 18 control second clock commutation circuit 18 provides identical test clock signals to all first clock switch circuit 15a-c, and the test control circuit 18 controls first clock switch circuit 15a-c offers the trigger of organizing among the 12a-c with this test clock signals, with the sequential of control serial-shift.
The test displaced condition is used for: before can being applied to functional circuit 10 to test data, test data is moved into from input end 11a-c by trigger group 12a-c; And test result shifted out to output terminal 19a-c by trigger group 12a-c.In an embodiment, can between trigger group 12a-c and output terminal 19a-c, add signature calculation circuit (not shown), therefore only need the output signed data.
Under the test normal condition, the trigger among the test control circuit 18 control trigger group 12a-c, so trigger is caught data-signal concurrently from functional circuit 10.Control capture time by clock signal.Under the test normal condition, 18 signals from input end 11a-c of test control circuit control second clock commutation circuit offer the first clock switch circuit 15a-c, and the test control circuit 18 control first clock switch circuit 15a-c offers trigger among each group 12a-c with each signal in these signals, with the control capture time.
Fig. 2 shows the embodiment of second clock commutation circuit 18.In this embodiment, second clock commutation circuit 18 comprises a plurality of multiplex electronics 20a-c, the first multiplexed input end of multiplex electronics 20a-c is connected to and connects 17a with the acceptance test clock signal, and the second multiplexed input end is connected to input end 11a-c.The output terminal 28a-d of multiplex electronics 20a-c is connected to the input end of each first clock switch circuit (not shown).The public control input end 22 of multiplex electronics 20a-c is connected to the test control circuit (not shown).Under the test displaced condition, test control circuit control multiplex electronics 20a-c is delivered to first multiplex electronics to the test clock signals from input end of clock 17a.Under the test normal condition, test control circuit control multiplex electronics 20a-c is delivered to first multiplex electronics to the signal from input end 11a-c.
Fig. 3 shows typical test macro.This system comprises that circuit 30, the test signal in the test provides equipment 32 and test signal to select equipment 34.But the circuit in the test is the test circuit shown in Fig. 1 for example.In operation, the input end of the circuit in the test 30, output terminal and test interface all are connected to test signal equipment 32 are provided.Test signal provides the circuit 30 of equipment 32 in test that test data and control signal are provided, and (for example regain test result, data of from functional circuit 10, catching or the signature that from these data, calculates), this test result is estimated, to determine whether this circuit comprises fault.Before test, the description that test signal selects equipment 34 to receive the circuit in the test, and the set that produces test data pattern (pattern), thereby in the specific classification of relevant error shown in the test result.Test signal selects equipment 34 to provide equipment that the information about selected pattern and the test result of the expectation that produces under the situation of error-free circuit are provided to test signal.
Test signal provides equipment 32 that test pattern is offered input end 11a-c, and connects 17 to test control signal is provided, so that trigger group 12a-c is shifted test pattern by trigger.Next, test signal provides equipment 32 that control signal is provided, so that test control circuit is switched to the test normal condition.At this moment, make second clock commutation circuit 18 that signal is delivered to trigger group 12a-c with the control clock from input end 11a-c.In this manner, between trapping period, provide equipment 32 to carry out sequential control completely to test signal.Whether test signal provides equipment 32 to provide the time clock with sequential of selecting according to required test at input end 11a-c place, react with needed speed with the specific part of determining functional circuit.
Fig. 4 shows the employed signal of test period.Show three time interval 40a, 42,40b.During the first and the 3rd time interval 40a, b, test control circuit is in the test displaced condition, and the catching at interval during 42 of centre, test control circuit is in the test normal condition.Show each clock signal 44a-c in the group.These clock signals produce at IC interior, and part is from internal signal, and part is from external signal.During the first and the 3rd time interval 40a, b, when test control circuit is in displaced condition, define the time clock of clock signal 44a-c by a test clock signals, so clock signal 44a-c comes down to identical.Normal function operating period beyond test, these clock signals are certainly different, because in normal function operating period, these clock signals are provided by different clock circuit 15a-c.
Catching during the interval 42 in test, when test control circuit was in the test normal condition, from the signal acquisition clock signal 44a-c of input end 11a-c, so each clock signal 44a-c can provide equipment to define separately by test signal.Input signal 46a-c shows the example of the signal at input end 11a-c place.During the first and the 3rd time interval 40a, b, input signal 46a-c comprises the test data (being represented by hacures) that does not pass to clock signal 44a-c.
In catching interval 42, input signal 46a-c comprises the time clock 47,48 that passes to clock signal 44a, c.Unlike signal among the input signal 46a-c is can be mutually different or can provide equipment 32 controls time clock down to carry out different timings by test signal, and therefore different clock signal 44a-c can also catch at interval in 42 difference mutually.
In the example of Fig. 4, apply two time clock 47,48 to each trigger group 12a-c.Pulse 48 makes the trigger in the respective sets catch data.First pulse 47 can be used for producing signal transition at the input end of functional circuit 10.In typical circuit, can be with trigger to being used for this purpose, wherein the input end of first trigger of this trigger centering has with the function of the output terminal of second trigger of this trigger centering and is connected.During the test displacement, mutually opposite test data values is loaded in the right trigger of this trigger.(before first pulse 47) at first, first trigger provides first test data values to functional circuit 10.Respond first time clock 47, comprise the trigger loading data of first trigger of this trigger centering.Thus, first trigger of this trigger centering is from the second trigger loading data, and this makes the output signal from first trigger to functional circuit change numerical value.After certain time delay, second pulse 48 makes trigger catch data again, so another trigger will catch consequential signal from functional circuit 10, and this consequential signal is subjected to the influence from the signal of first trigger of this trigger centering.Typically, the consequential signal of being caught will shift out to check by output terminal 19a-c.Check the consequential signal of being caught, whether in the time interval, correctly react by the time clock definition to determine this functional circuit.
Be understandable that, if this is just about using an example of external clock pulse.In other examples, can carry out the more complicated test that comprises more timing acquisition operations.In this case, during test normal, can apply time clock from outside terminal more than two time clock 47,48.Can use other technologies to replace setting up transformation by loading mutually opposite test data, such as under test normal, using the trigger be in toggle (toggle) configuration, the negative circuit of perhaps using first time clock 47 by the trigger output to be activated.
In this manner, can use the sequential relationship of any desired in each trigger group, to catch data.For example, in the example of Fig. 4, trigger group 12a-c that can be different is set to operate on different mutually clock frequencies, such as 10MHz, 16.6MHz and 50MHz, and can test signal provide equipment to be set to time clock be offered input end 11a-c with the corresponding time gap of these frequencies or with maximum or the minimum time gap accepted.
Though invention has been described according to specific embodiment, should be understood that the present invention is not limited to this embodiment.For example, though invention has been described in conjunction with boundary scan test circuit, it should be understood that the present invention can separate application with boundary scan.As another example, use input end 11a-c that clock signal is provided temporarily though described, it should be understood that in normal function operating period and can be used for providing clock signal at test period temporarily as one or more terminal of input end and output terminal.Use some additional three state circuits, even can be used to provide clock signal a terminal 29a-c during feature operation as output terminal.Key is, is used for the terminal of this purpose, and no matter what its normal function is, between trapping period, when circuit temporarily was not in the scan shift state, these terminals did not need to receive or provide other signals.In addition, though shown three trigger group 12a-c, three input end 11a-c and three output terminal 19a-c, it should be understood that trigger 12a-c, input end 11a-c and the output terminal 19a-c that can use any amount.Clock signal from any input end or other terminals can be provided, replace clock signal, be used for providing the input end 11a-c of data to provide clock signal to identical group to certain triggers group 12a-c from any clock circuit 14a-c.
Though 14a-c illustrates as separate unit clock circuit, it should be understood that between clock circuit to have contact, for example, because wherein some or all are set to lock onto the common clock source.In addition,, it should be understood that alternatively, can one or more clock circuit be connected to integrated circuit by outside terminal though all clock circuits preferably are integrated in the identical integrated circuit.In addition, though show embodiment, wherein each input end 11a-c is connected to the input end of clock of each predetermined trigger group 12a-c, be understood that, alternatively, can provide commutation circuit, thereby input end 11a-c is connected to optional trigger group 12a-c, trigger group 12a-c is selected by test control circuit 16, for example selects according to test control circuit 16 received control commands.
In addition, though illustrate from the clock signal of second clock commutation circuit 18 as at the replacement from the clock signal of each clock circuit 14a-c, it should be understood that does not need such one-one relationship.In one embodiment, can be replaced the clock signal from specific clock circuit 15a-c by two or more the different clock signals from input end 11a-c, these clock signals are applied to different trigger groups.In another embodiment, from the clock signal of a plurality of clock circuit 14a-c, for example, can all replace by identical clock signal from one of input end 11a-c from the clock signal of two clock circuits among this clock circuit 14a-c.Under the test normal condition, use different input end 11a-c to provide different clock signals to have following advantage: can test a plurality of circuit parts concurrently to the different piece of circuit, wherein each circuit part all has its own sequential, but can use common clock signal that the part of the identical sequential of needs is tested.Even different trigger group 12a-c is in the identical clock signal of normal function operating period reception, it also is favourable using and testing these groups from the clock signal of different input end 11a-c, because this can be used to illustrate additional mistake.
In addition,, wherein a test clock signals is used for controlling the displacement of all trigger group 12a-c, it should be understood that alternatively, can use a plurality of different test clock signals to control the different son groups of group 12a-c though shown circuit.Between trapping period, these test clock signals are replaced by the signal from input end 11a-c, thereby can use how different clock signals, or use has the clock signal of optional more freely sequential attribute.
In the prior art, the circuit structure standard of the circuit in the given test has been developed strong method and has been selected test pattern, and this test pattern can illustrate the fault of circuit effectively.Test signal selects equipment 34 can be set to provide the method for this prior art.Yet, may have problems in this case, because these methods do not have to consider can temporarily become at the test period terminal fact of clock end.A method handling this problem is: provide the test signal with virtual circuit specification for structure to select equipment 34, this test signal selection equipment 34 has the independent input end at clock signal and data.Subsequently, by " merging " data and clock end, promptly by selecting only to comprise the test pattern of data terminal signal, and in virtual circuit is in the almost whole time interval of test normal, the signal of copies data end from the test pattern of virtual circuit, thus the test pattern of this virtual circuit is compiled as the test pattern of side circuit.During the test normal of virtual circuit, the clock signal from test pattern is copied to the test pattern of the data terminal of side circuit.
In an embodiment, the external data end 11a-c of clock signal is provided and between the internal circuit of these data terminal received signals, provides holding circuit being used to.Holding circuit is connected to test control circuit, to receive control signal.When this circuit enters test during normal condition, test control circuit control these holding circuits to internal circuit be provided at enter the test normal condition before received last input signal.When this circuit left the test normal condition, test control circuit control holding circuit was recovered the transmission to its input signal.In this manner, the clock signal that is applied to terminal under the test normal condition can not be passed through normal circuit path (path) arrival internal circuit.
Use at the shortcoming of the data terminal of test clock pulse is: when data terminal was not useable for applying test signal under test normal, test coverage may reduce.Preferably, the provide support circuit of clock test pattern and data test pattern.In an embodiment, test control circuit is set to the response test order to switch to clock test pattern or data test pattern.Under the clock test pattern, as previously mentioned, test control circuit makes the clock switching signal the input end of clock that offers from the clock signal of terminal 11a-c under the test normal.Preferably, as previously mentioned, control circuit control holding circuit is to remain on data under this pattern.Under the data test pattern, test control circuit makes the clock switching signal offer input end of clock under the test normal to test clock signals.If the use holding circuit, then when being in data test pattern following time, control circuit is controlled these holding circuits with Data transmission under test normal.In this manner, the test that can under the control of test control circuit, carry out proper testing and use external signal.
Claims (10)
1. a testable electronic circuit comprises
-a plurality of data terminals (11a-c);
-functional circuit (10);
-a plurality of trigger groups (12a-c), be connected to data terminal (11a-c) and functional circuit (10), each trigger group has the input end of clock that is used for providing to the trigger of this trigger group (12a-c) clock, each group can be switched between shift configuration and functional configuration, moving into test data serially, and be used for respectively signal being offered functional circuit (10) concurrently and/or respectively from functional circuit (10) received signal from data terminal (11a-c);
-test control circuit (16), can between functional mode, test shift mode and test normal, switch, described test control circuit (16) is connected to trigger group (12a-c), under functional mode, switching to functional configuration, and under the test shift mode, switch to shift configuration with described group with described group;
-clock multiplex electronics (15a-c, 18), has the input end that is connected to data terminal (11a-c), and the output terminal that is connected to the input end of clock of trigger group (12a-c), the pattern of being taked according to test control circuit (16), connect described test control circuit (16) with control clock multiplex electronics (15a-c, 18), clock multiplex electronics (15a-c, 18) is set to: under test normal, at the input end of clock place of each trigger group (12a-c), temporary transient substitution is from the clock signal of each data terminal (11a-c).
2. testable electronic circuit as claimed in claim 1, comprise the test clock end (17a) that is connected to clock multiplex electronics (15a-c, 18), clock multiplex electronics (15a-c, 18) is set to: under the test shift mode, the test clock signals from test clock end (17a) is offered the input end of clock of trigger group (12a-c).
3. testable electronic circuit as claimed in claim 2, comprise a plurality of clock circuits (14a-c) that are connected to clock multiplex electronics (15a-c, 18), clock multiplex electronics (15a-c, 18) is set to: under functional mode, the clock signal from each clock circuit (14a-c) is offered the input end of clock of each trigger group (12a-c).
4. the method for a test electronic circuits, described method comprises:
-electronic circuit is switched to test pattern;
-move into test data by a plurality of data terminals (11a-c) of electronic circuit;
-by a plurality of trigger groups (12a-c), serially test data is shifted;
-test clock signals from test clock is routed to the sequential control input end of trigger group (12a-c), to control the sequential of described displacement;
-testing interim normal time, change the clock route, each data terminal (11a-c) is connected to the sequential control input end of each trigger group (12a-c);
-when the clock route had changed, (11a-c) provided time clock to data terminal;
-use from the sequential under the time sequence control of the time clock of data terminal, the test result in the capture trigger group (12a-c).
5. method of testing as claimed in claim 4, wherein, when the clock route had changed, the time clock in the data terminal (11a-c) at least two terminals had mutually different sequential pattern.
6. method of testing as claimed in claim 4, wherein,
-the first test data values slave flipflop group (12a-c) is displaced to first trigger, second test data to the slave flipflop group (12a-c) that will be different from first test data values is displaced to second trigger;
-when the clock route has changed, at least the first and second time clock are applied in the data terminal (11a-c) at least one, the first time clock sequential copies second test data values to first trigger from second trigger, and the second clock pulse sequence is loaded into the response of functional circuit to the output signal of first trigger in another trigger.
7. method of testing as claimed in claim 4, wherein, described electronic circuit is set to, in normal function operating period, clock signal is routed to each trigger group (12a-c) from each clock circuit (14a-c), described method comprises and changes the clock route, with before entering the test shift mode with described group of test clock signals feed-in.
8. method of testing as claimed in claim 7, wherein, under the test shift mode, each in the trigger group (12a-c) receives identical test clock signals.
9. one kind comprises that electronic circuit as claimed in claim 1 and the test signal that links to each other with the data terminal (11a-c) of this electronic circuit (30) provide the test macro of equipment (32), wherein, test signal provides equipment (32) to be programmed to: when test control circuit (16) when entering acquisition mode, provide the pulse with the sequential pattern of having programmed to data terminal (11a-c).
10. tester, comprise the output terminal that is used for providing test data to the electronic circuit (30) of test, described tester is set to provide the test data that defines to data terminal (11a-c) able to programmely, and the electronic circuit in making test (30) enter be used to catch the test normal condition of test result pattern after, each time clock with the sequential pattern that defines is provided to data terminal (11a-c) able to programmely.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05300077.4 | 2005-02-01 | ||
| EP05300077 | 2005-02-01 | ||
| PCT/IB2006/050326 WO2006082555A1 (en) | 2005-02-01 | 2006-01-31 | Testable electronic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101163978A CN101163978A (en) | 2008-04-16 |
| CN101163978B true CN101163978B (en) | 2010-08-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800038093A Expired - Fee Related CN101163978B (en) | 2005-02-01 | 2006-01-31 | Testable electronic circuit, test method and tester |
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| Country | Link |
|---|---|
| US (1) | US7899641B2 (en) |
| EP (1) | EP1875256B1 (en) |
| JP (1) | JP2008528999A (en) |
| CN (1) | CN101163978B (en) |
| AT (1) | ATE436028T1 (en) |
| DE (1) | DE602006007695D1 (en) |
| WO (1) | WO2006082555A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8432181B2 (en) * | 2008-07-25 | 2013-04-30 | Thomson Licensing | Method and apparatus for reconfigurable at-speed test clock generator |
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| US6260165B1 (en) * | 1996-10-18 | 2001-07-10 | Texas Instruments Incorporated | Accelerating scan test by re-using response data as stimulus data |
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| CA2225879C (en) | 1997-12-29 | 2001-05-01 | Jean-Francois Cote | Clock skew management method and apparatus |
| US6484280B1 (en) * | 1999-09-30 | 2002-11-19 | Agilent Technologies Inc. | Scan path test support |
| US6763489B2 (en) * | 2001-02-02 | 2004-07-13 | Logicvision, Inc. | Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description |
| US20030084390A1 (en) | 2001-10-26 | 2003-05-01 | Mentor Graphics Corporation | At-speed test using on-chip controller |
| US7000164B2 (en) * | 2002-01-30 | 2006-02-14 | Sun Microsystems, Inc. | Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops |
| US6861867B2 (en) * | 2002-03-07 | 2005-03-01 | Lightspeed Semiconductor Corporation | Method and apparatus for built-in self-test of logic circuits with multiple clock domains |
| JP2006518040A (en) * | 2003-02-18 | 2006-08-03 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Electronic circuit test |
| TWI235841B (en) * | 2003-07-02 | 2005-07-11 | Realtek Semiconductor Corp | Multi-clock domain logic device for performing scan test with single scan clock and method thereof |
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2006
- 2006-01-31 US US11/815,313 patent/US7899641B2/en not_active Expired - Fee Related
- 2006-01-31 DE DE602006007695T patent/DE602006007695D1/en active Active
- 2006-01-31 EP EP06710792A patent/EP1875256B1/en not_active Not-in-force
- 2006-01-31 WO PCT/IB2006/050326 patent/WO2006082555A1/en active Application Filing
- 2006-01-31 JP JP2007552801A patent/JP2008528999A/en not_active Withdrawn
- 2006-01-31 AT AT06710792T patent/ATE436028T1/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6393592B1 (en) * | 1999-05-21 | 2002-05-21 | Adaptec, Inc. | Scan flop circuitry and methods for making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1875256B1 (en) | 2009-07-08 |
| EP1875256A1 (en) | 2008-01-09 |
| DE602006007695D1 (en) | 2009-08-20 |
| CN101163978A (en) | 2008-04-16 |
| WO2006082555A1 (en) | 2006-08-10 |
| US20080133167A1 (en) | 2008-06-05 |
| US7899641B2 (en) | 2011-03-01 |
| ATE436028T1 (en) | 2009-07-15 |
| JP2008528999A (en) | 2008-07-31 |
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