CN101149968A - Delay counter possessing frequency detector and its delayed counting method - Google Patents

Delay counter possessing frequency detector and its delayed counting method Download PDF

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CN101149968A
CN101149968A CNA200610154302XA CN200610154302A CN101149968A CN 101149968 A CN101149968 A CN 101149968A CN A200610154302X A CNA200610154302X A CN A200610154302XA CN 200610154302 A CN200610154302 A CN 200610154302A CN 101149968 A CN101149968 A CN 101149968A
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control signal
delay
input clock
frequency
clock
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CN100543871C (en
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郑文昌
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

The delay counter for delaying the access control signals of a memory comprises a clock delay module for delaying an input clock to produce a delayed input clock according to at least a certain delay, a frequency detector for detecting the frequency of a specific signal in the memory to set the delay, and a delay control signal producing module for outputting a first delayed control signal and a second delayed control signal which are correspondent to the access control signals of the memory respectively according to the delayed input clock and delayed output clock. In which the time sequence of the first delayed control signal is earlier than that of the second delayed control signal.

Description

Delay counter and delay counter method thereof with frequency detector
Technical field
The invention relates to a kind of delay counter that is applied to storer, refer to a kind of delay counter and its delay counter method especially with frequency detector.
Background technology
Along with development of information industry, the correlation technique of semiconductor element also progresses greatly day by day.(random access memory RAM) in writing/speed of reading of data, double-speed data transmission (double data rate, DDR) The Application of Technology have occurred then in order to promote random access memory.The random access memory of using this technology is so-called double-speed random access memory (DDR RAM).When the general microprocessor of being taken in was desired access memory, this microprocessor can be sent out and read the control circuit of signal to this storer, and wherein this reads signal and external clock is synchronous.Yet, known technology can use delay counter (LatencyCounter) to be coupled between this processor and this control circuit, it provides and reads signal in this time delay (delay period number), makes this storer have time enough and comes this particular address of access.Because the frequency range of the operating clock of storer is extremely wide, makes delay counter need have different delay period numbers under the operation of high and low frequency, promptly the delay period number under high frequency is more, and the delay period number under low frequency is less.But because circuit itself promptly has the delay of its inside, therefore under the operating environment of high frequency, the cycle of this high frequency clock signal of retardation ratio of circuit inside is when being greater, the known delay counter just easily reads the delay period number that signal and this external clock have output error when asynchronous slightly at this, makes this control circuit read wrong signal.Just can't be satisfied with demand at higher storage device clock frequency and the big designed delay counter of delay period number than low memory clock frequency and less delayed periodicity.
Summary of the invention
Therefore fundamental purpose of the present invention is to provide a kind of delay counter and its delay counter method that frequency detector is adjusted the delay period number that have, to solve above-mentioned known problem.
A kind of delay counter that is applied to storer is provided in one embodiment of the invention, is used for the delay memory access control signal.This delay counter includes: the clock delay module, be coupled to input clock, and be used for postponing this input clock and postpone the back input clock to produce according at least one retardation; Frequency detector is coupled to this clock delay unit, is used for detecting the frequency of signal specific in this storer to set this retardation; And delayed control signal generation module, be coupled to this delay back input clock, this input signal and this memory access control signal, be used for respectively according to this delay back input clock and output clock export to should memory access control signal first postpone back control signal and second and postpone the back control signal, wherein this first sequential that postpones the back control signal be early than this second postpone after the sequential of control signal.
A kind of delay counter method that is applied to storer is provided in one embodiment of the invention, is used for the delay memory access control signal.This method includes: postpone this input clock according at least one retardation and postpone the back input clock to produce; The frequency that detects signal specific in this storer is to set this retardation; And respectively according to this delay back input clock and output clock export to should memory access control signal first postpone back control signal and second and postpone the back control signal, wherein this first sequential that postpones the back control signal be early than this second postpone after the sequential of control signal.
Description of drawings
Fig. 1 is applied to the synoptic diagram of an embodiment of the delay counter of storer for the present invention.
Fig. 2 is that delay counter shown in Figure 1 is applied in the sequential chart under the high frequency accessing operation.
Fig. 3 is that delay counter shown in Figure 1 is applied in the sequential chart under the low frequency accessing operation.
Fig. 4 is the process flow diagram of an embodiment of delay counter method of the present invention.
[main element label declaration]
100 Delay counter
102 The clock delay module
102a～102g May command clock delay unit
104 Frequency detector
106 The delayed control signal generation module
106a～106g Temporary element
Embodiment
Please refer to Fig. 1, Fig. 1 is applied to the synoptic diagram of an embodiment of the delay counter 100 of storer for the present invention.Delay counter 100 is used for delay memory access control signal PAR, and as shown in the figure, delay counter 100 includes: clock delay module 102, frequency detector 104 and delayed control signal generation module 106.Clock delay module 102 is coupled to input clock V Clk, be used for according to a plurality of retardation D 1, D 2, D 3Postpone input clock V ClkTo produce a plurality of delays back input clock VD respectively Clk1, VD Clk2, VD Clk3Frequency detector 104 is coupled to clock delay module 102, is used for detecting (the input clock V of signal specific in this storer Clk) frequency f ClkTo set retardation D 1, D 2, D 3, in the present embodiment, input clock V for example ClkOperating clock for this storer.Delayed control signal generation module 106 is coupled to and postpones back input clock VD Clk1, VD Clk2, VD Clk3, input signal V ClkWith memory access control signal PAR, be used for respectively according to postponing back input clock VD Clk1, VD Clk2, VD Clk3Export a plurality of delays back control signal LT1～LT7 of corresponding stored device access control signal PAR with memory access control signal PAR, the sequential that wherein postpones back control signal LT1 is early than the sequential that postpones back control signal LT2, the sequential that postpones back control signal LT2 is early than the sequential that postpones back control signal LT3, by that analogy.In delay counter 100 of the present invention, clock delay module 102 includes may command clock delay unit 102a, is used to provide retardation D 1Give input clock V ClkPostpone back input clock VD to produce Clk1May command clock delay unit 102b is used to provide retardation D 2Give input clock V ClkPostpone back input clock VD to produce Clk2May command clock delay unit 102c is used to provide retardation D 3Give input clock V ClkPostpone back input clock VD to produce Clk3Delayed control signal generation module 106 includes temporary element (present embodiment is to do in fact by trigger) 106a, is according to postponing back input clock VD Clk1Triggering (clock end C 1) read memory access control signal PAR (data terminal D 1) postpone back control signal LT1 (output terminal N to produce 1); Temporary element 106b is according to postponing back input clock VD Clk2Triggering (clock end C 2) read and postpone back control signal LT1 (data terminal D 2) postpone back control signal LT2 (output terminal N to produce 2); Temporary element 106c is according to postponing back input clock VD Clk3Triggering (clock end C 3) read and postpone back control signal LT2 (data terminal D 3) postpone back control signal LT3 (output terminal N to produce 3).Note that in order to be illustrated more clearly in spiritual place of the present invention, the delayed control signal generation module 106 of delay counter 100 also comprised temporary element 106d ..., 106g, its clock end C 4, C 5, C 6, C 7All be coupled to input clock V Clk, its data terminal D 4, D 5, D 6, D 7Be coupled to output terminal N respectively 3, N 4, N 5, N 6, be used for producing respectively postpone back control signal LT4 ..., LT7 (as shown in Figure 1).Note that delay counter 100 of the present invention only utilizes three may command clock delay unit, yet in other embodiment, circuit designers also can all belong to category of the present invention according to the number of its increase in demand or minimizing may command clock delay unit.
Because this storer may be set to two kinds of high frequency accessing operation (using higher memory clock) and low frequency accessing operations (using lower memory clock) in the operation of reality, under the high frequency accessing operation, the user tends to choose control signal after the big more delay of retardation so that access memory correctly for example postpones back control signal LT5, postpones back control signal LT6 or postpones back control signal LT7.This moment, frequency detector 104 detected input clock V ClkFrequency f hDuring for high frequency, frequency detector 104 will be set three above-mentioned retardation D 1, D 2, D 3Non-vanishing, D wherein 1, D 2, D 3Value can be determined according to the operational requirements of this storer.Please refer to Fig. 2, Fig. 2 is that delay counter 100 shown in Figure 1 is applied to the sequential chart under the high frequency accessing operation.In the present embodiment, if delay counter 100 at time t 1Receive input clock V ClkFirst pulse of (clock period is T), and memory access control signal PAR can be in the t after this first pulse 2Reach the clock end C of temporary element 106a 1, the clock end C of then temporary element 106a 1Can be at t 1+ D 1Receive and postpone back input clock VD Clk1, therefore, the output terminal N of temporary element 106a 1Can be at t 1+ D 1+ D 106aJust control signal LT1 (as shown in Figure 2), wherein D after the output delay afterwards 106aIt is the time delay of temporary element 106a.Then, because may command clock delay unit 102b can be to input clock V ClkSecond pulse daley D 2, and the clock end C of feasible temporary element 106b 2Can be at t 1+ T+D 2Just receive and postpone back input clock VD Clk2, the output terminal N of therefore temporary element 106b 2Can be at t 1+ T+D 2+ D 106bControl signal LT2 after the output delay just afterwards,, D wherein 106bIt is temporary element 1 06bTime delay.In like manner, because may command clock delay unit 102c can be to input clock V ClkThe 3rd pulse daley D 3, and the clock end C of feasible temporary element 106c 3Can be at t 1+ 2T+D 3Receive and postpone back input clock VD Clk3, the output terminal N of therefore temporary element 106c 3Can be at t 1+ 2T+D 3+ D 106cJust control signal LT3, wherein D after the output delay afterwards 106cIt is the time delay of temporary element 106c.Then, postpone the data terminal D that back control signal LT3 can reach the temporary element 106d of next stage 3, keep in the clock end C of element 106d this moment 3Can wait for input clock V ClkNext positive edge removes to trigger temporary element 106d, i.e. input clock V ClkThe 4th pulse, and then in time t 1+ 3T+D 106dControl signal LT4 (as shown in Figure 2) D wherein after the output delay 106dIt is the time delay of temporary element 106d.In like manner, postponing back control signal LT5, LT6 and LT7 all can be respectively at time t 1+ 4T+D 106e, t 1+ 5T+D 106f, t 1+ 6T+D 106gOutput, wherein D 106e, D 106f, D 106gBe respectively the time delay of temporary element 106e, temporary element 106f and temporary element 106g.These three retardation D 1, D 2, D 3Be that each is different, and under the operation of high frequency, D 1＞D 2＞D 3, as shown in Figure 2.
On the other hand, under the low frequency accessing operation, the user tends to choose control signal after the less delay of delay period number, for example postpones back control signal LT2 or postpones back control signal LT3.This moment, frequency detector 104 detected input clock V ClkFrequency f 1During for low frequency, frequency detector 104 will be with two retardation D 2, D 3Be made as zero, and the retardation D that only utilizes may command clock delay unit 102a to be provided 1Remove to postpone input clock V ClkPlease refer to Fig. 3, Fig. 3 is that delay counter 100 shown in Figure 1 is applied in the sequential chart under the low frequency accessing operation.In the present embodiment, if delay counter 100 at time t 1Receive input clock V ClkWith memory access control signal PAR, then keep in the clock end C of element 106a 1Can be at t 1+ D 1Receive and postpone back input clock VD Clk1, therefore, the output terminal N of temporary element 106a 1Can be at t 1+ D 1Control signal LT1 (as shown in Figure 3) after the output delay just afterwards.Owing to retardation D this moment 2, D 3Be zero, the clock end C of therefore temporary element 106b 2Can wait for input clock V ClkNext positive edge removes to trigger temporary element 106b, i.e. Δ t 2, and then in time t 1+ D 1+ Δ t 2Control signal LT2 (as shown in Figure 3) after the output delay.In like manner, postponing back control signal LT3 can be at time t 1+ D 1+ Δ t 2+ T output.
Please refer to Fig. 4, Fig. 4 is the process flow diagram of an embodiment of delay counter method of the present invention.Delay counter method of the present invention is to be applied to delay counter shown in Figure 1 100, is used for delay memory access control signal PAR, and its running is summarized as follows simply:
Step 402: detect (the input clock V of signal specific in this storer Clk) frequency f Clk
Step 404: judge input clock V ClkBe high frequency or low frequency; If high frequency then skips to step 406; If low frequency then skips to step 412;
Step 406: according to retardation D 1, D 2, D 3Postpone input clock V ClkPostpone back input clock VD to produce respectively Clk1, VD Clk2, VD Clk3
Step 408: according to postponing back input clock VD Clk1, VD Clk2, VD C1k3Export control signal LT1, LT2 and LT3 after the delay of corresponding stored device access control signal PAR with memory access control signal PAR, the sequential that wherein postpones back control signal LT1 is early than the sequential that postpones back control signal LT2, and the sequential of delay back control signal LT2 is early than the sequential that postpones back control signal LT3;
Step 410: respectively at time t 1+ 3T+D 106d, t 1+ 4T+D 106e, t 1+ 5T+D 106f, t 1+ 6T+D 106gExport control signal LT4 after the required delay, postpone back control signal LT5, postpone back control signal LT6 and postpone back control signal LT7;
Step 412: with retardation D 2, D 3Be made as zero;
Step 414: utilize retardation D 1Remove to postpone input clock V C1kAnd
Step 416: in time t 1+ D 1+ Δ t 2Control signal LT2 after the output delay, and at time t 1+ D 1+ Δ t 2Control signal LT3 after the+T output delay.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (9)

1. delay counter that is applied to storer is used for the delay memory access control signal, and this delay counter includes:
The clock delay module is coupled to input clock, is used for postponing this input clock according at least one retardation and postpones the back input clock to produce;
Frequency detector is coupled to this clock delay unit, is used for detecting the frequency of signal specific in this storer to set this retardation; And
The delayed control signal generation module, be coupled to this delay back input clock, this input signal and this memory access control signal, be used for respectively according to this delay back input clock and this output clock export to should memory access control signal first postpone back control signal and second and postpone the back control signal, wherein this first postpone after sequential of control signal be sequential early than control signal after this second delay.
2. delay counter according to claim 1, wherein this clock delay module includes:
The first may command clock delay unit is used to provide first retardation and gives this input clock to produce the first delay back input clock; And
The second may command clock delay unit is used to provide second and postpones this input clock of quantum to produce the second delay back input clock;
This delayed control signal generation module includes:
The first temporary element reads this memory access control signal to produce this first delay back control signal according to this first triggering that postpones the back input clock; And
The second temporary element reads this first delay back control signal according to this second triggering that postpones the back input clock and postpones the back control signal to produce the 3rd;
Wherein when detecting this frequency correspondence first frequency of this signal specific, it is zero that this frequency detector can be set this second retardation, and when this frequency correspondence that detects this signal specific was higher than the second frequency of this first frequency, it was zero that this frequency detector can not set this second retardation.
3. delay counter according to claim 2, wherein this frequency detector also control this first retardation in the numerical value under this second frequency greater than the numerical value under this first frequency.
4. delay counter according to claim 1, wherein this signal specific is the operating clock of this storer.
5. delay counter according to claim 1, wherein this frequency detector detects this input clock, and at random sets this retardation to be applicable to any frequency of this input clock according to testing result.
6. delay counter method that is applied to storer is used for the delay memory access control signal, and this method includes:
Postpone this input clock according at least one retardation and postpone the back input clock to produce;
The frequency that detects signal specific in this storer is to set this retardation; And
Respectively according to this delay back input clock and output clock export to should memory access control signal first postpone back control signal and second and postpone the back control signal, wherein this first sequential that postpones the back control signal be early than this second postpone after the sequential of control signal.
7. method according to claim 6 wherein postpones this input clock and includes:
Provide first retardation to give this input clock and postpone the back input clock to produce first; And
Provide second retardation to give this input clock and postpone the back input clock to produce second;
Respectively according to this delay back input clock and this output clock export to should memory access control signal this first postpone back control signal and this second delay after control signal include:
Read this memory access control signal to produce this first delay back control signal according to this first triggering that postpones the back input clock; And
Read this first delay back control signal according to this second triggering that postpones the back input clock and postpone the back control signal to produce the 3rd;
Wherein when detecting this frequency correspondence first frequency of this signal specific, setting this second retardation is zero, and when this frequency correspondence that detects this signal specific was higher than the second frequency of this first frequency, not setting this second retardation was zero.
8. method according to claim 7, wherein detect in this storer this frequency of this signal specific also comprise this first retardation of control in the numerical value under this second frequency greater than the numerical value under this first frequency.
9. method according to claim 6, wherein this signal specific is the operating clock of this storer.
CNB200610154302XA 2006-09-20 2006-09-20 Delay counter and delay counter method thereof with frequency detector Active CN100543871C (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102467956A (en) * 2010-11-17 2012-05-23 海力士半导体有限公司 Clock control circuit and semiconductor memory apparatus using the same
CN103383587A (en) * 2012-05-04 2013-11-06 爱思开海力士有限公司 Semiconductor apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102467956A (en) * 2010-11-17 2012-05-23 海力士半导体有限公司 Clock control circuit and semiconductor memory apparatus using the same
CN102467956B (en) * 2010-11-17 2015-05-13 海力士半导体有限公司 Clock control circuit and semiconductor memory apparatus using the same
CN103383587A (en) * 2012-05-04 2013-11-06 爱思开海力士有限公司 Semiconductor apparatus
CN103383587B (en) * 2012-05-04 2017-09-22 爱思开海力士有限公司 Semiconductor device

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