CN101149763A - Burst mode asynchronous control circuit design method - Google Patents
Burst mode asynchronous control circuit design method Download PDFInfo
- Publication number
- CN101149763A CN101149763A CNA2007100360524A CN200710036052A CN101149763A CN 101149763 A CN101149763 A CN 101149763A CN A2007100360524 A CNA2007100360524 A CN A2007100360524A CN 200710036052 A CN200710036052 A CN 200710036052A CN 101149763 A CN101149763 A CN 101149763A
- Authority
- CN
- China
- Prior art keywords
- burst
- state machine
- state
- sub
- req
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Information Transfer Systems (AREA)
Abstract
This invention discloses an asynchronous control circuit design method of burst mode, the problem to be solved is to improve the design scale, bring the large-scale burst mode asynchronous control circuit into practical use. The technical programme is to use directed loop set corresponding to burst mode state machine M to decompose M; add additional request and response signal, adjust the burst mode sub state machine from the first level to the K level, design burst mode interface state machine to judge if trigger arbitration or not to the state machine; adjust all the second level to K-1 level burst mode sub state machine once again; achieve sub control circuit module and interface control circuit module; synthesis burst mode asynchronous control circuit. Using this invention can decompose levels of sub state machine with high efficiency and large scale; can solve the arbitration problem between the state machines, with simple design method; can effectively remove requirements of timing constraints between the sub state machine the and reduce the difficulties of logic synthesis.
Description
The technical field is as follows:
the invention relates to a design method of a large-scale asynchronous control circuit, in particular to a design method of a large-scale burst-mode (burst-mode) asynchronous control circuit.
The background art comprises the following steps:
due to the scale-up of integrated circuits, the reduction of feature sizes, the increase of design dominant frequencies, and the limitation of manufacturing processes, the line delay, clock tree load, etc., which are negligible in the synchronous circuits, are becoming more and more prominent, and the design method also faces many problems (especially clock skew problems) that are difficult to solve. Relatively speaking, an asynchronous circuit does not need a global clock, so that the problems of complex clock tree design and clock deviation are effectively avoided, and meanwhile, the asynchronous circuit gradually becomes a hot point of circuit design research according to various characteristics such as good portability, high modularization degree, strong anti-electromagnetic interference capability, low power consumption and the like.
The development of asynchronous circuits can be said to depend to a large extent on the sophistication and maturity of asynchronous circuit design methods and EDA tools. Since the main difference between the asynchronous circuit and the synchronous circuit lies in the control logic of the circuit, and the data paths of the circuit are basically consistent, the existing asynchronous circuit design method generally utilizes the design flow of the existing synchronous circuit and the commercial EDA tool to design the asynchronous data paths, and focuses on the design of the asynchronous control circuit.
According to different types and description mechanisms of asynchronous control circuits, asynchronous control circuit design methods can be roughly divided into three types, namely, CSP-based methods, petri net-based methods and finite-state machine-based methods:
A. the CSP (Communicating Sequential processing) based method mainly adopts CSP asynchronous description languages such as Balsa, tangram, DI-Algebra, DISP (DI Sequential processing) and CHP (Communicating Hardware processing) to describe the behavior of the control circuit, and obtains the delay-independent or quasi-delay-independent asynchronous control circuit through syntax-driven conversion (syntax-directed conversion). The method can describe the circuit behavior at a higher level, can more fully mine the parallelism of the asynchronous control circuit, and has the defect that
a) The global optimization technology cannot be applied, and the designed circuit has low working efficiency;
b) CSP asynchronous description language syntax is obscure, related EDA tools are imperfect, and wide acceptance and use are difficult;
B. the Petri Net-based method mainly adopts LPN (Labeled Petri Net), STG (Signal Transition Graph) or CD (Change Diagram) and the like to describe the behavior of the control circuit, and the speed-independent asynchronous control circuit is obtained through reachability analysis, state coding, boolean expression generation, logic decomposition and process mapping. The method can describe the circuit behavior at a lower level, can use time sequence information during optimization, and generates a more efficient circuit structure. Meanwhile, for deep submicron processes, line delay dominates, and the delay assumption of the circuit may no longer apply.
C. The Finite-State-Machine-based method mainly adopts an Asynchronous Finite-State Machine (Asynchronous State Machine) or a Burst Mode State Machine (Burst Mode Machine) to describe the behavior of the control circuit, and a basic Mode Huffman circuit and a Burst Mode Asynchronous control circuit are respectively obtained through State reduction, state assignment, logic synthesis and process mapping. The method is similar to a synchronous circuit design method based on a finite-state machine, can fully utilize or use the existing design method and EDA tools for processing, and has the defects that the concurrent change of input and output is not allowed, and when and only when the circuit is completely stable, namely the state of the circuit does not change any more, the external input signal of the circuit is allowed to change, thereby causing the operation cycle of the circuit to be lengthened and the working efficiency to be reduced.
By comparing the advantages and the disadvantages of the method, the asynchronous control circuit design method based on the finite-state machine is more feasible and practical.
The burst mode state machine is a commonly used description mechanism for asynchronous control circuit design methods based on finite state machines, and uses a state transition diagram similar to a synchronous Mealy machine to describe circuit behavior. Burst mode state machines are derived from asynchronous finite state machines, but the description capability of the asynchronous finite state machines is expanded: reducing the basic assumption requirement of an asynchronous finite state machine (which requires no change in the current input signal before the response to the previous input signal is stable) allows the signals in the burst input (the non-empty set of input signals) to change in any order. Of course, the burst mode state machine still requires that the fundamental assumptions must be satisfied between the various burst inputs.
Burst mode state machine M typically employs a 7-tuple pair<V，E，I，O，v 0 ，trans i ，trans o >Performing formal description, wherein V is a state node set, a node V belongs to V and corresponds to the state V of M, E \583974, V multiplied by V is a directed edge set, and a directed edge E =<u，v>E connects nodes u and v for describing the transition between states u and v in M, I = { x = 1 ，…，x m Is the set of input signals, O = { z } 1 ，…，z n Is the set of output signals, node v 0 E.g. V is defined as the starting state node, and the starting state V of M 0 And correspondingly. Directed edge marking function trans i ：E→{-，+} I And trans o ：E→{-，+} O For specifying burst input transitions and burst output transitions at state transitions, respectively, i.e., the changing behavior of burst input and burst output during state transitions. For any directed edge E epsilon E, distinguishing corresponding burst input and burst output by using '|', whereinBefore "|" is the burst input, followed by the burst output, which is allowed to be empty.
The burst mode asynchronous control circuit is obtained through a burst mode state machine and consists of a burst input, a burst output, a combinational logic circuit and a feedback loop, wherein the combinational logic circuit adopts a finite delay model, and the feedback loop adopts an infinite feedback delay model. The current state of the circuit is maintained in a feedback loop, and the burst output and the next state of the circuit are determined by the burst input, the current state, and the feedback of a portion of the output signal.
For the asynchronous control circuit design method based on the finite-state machine, because complete state space search is required in the logic synthesis stage and the problem of state space explosion is faced, the method is only suitable for the design of medium and small scale control circuits. In order to effectively improve the design scale of the Burst Mode Asynchronous control circuit, a Decomposition design Method of a large-scale Burst Mode Asynchronous control circuit is provided in an article A Cycle-Based composition Method for Burst-Mode Asynchronous controls by an Asynchronous circuit and system research group of Columbia university, the Method firstly carries out hierarchical Decomposition on a complex Burst Mode state machine to obtain mutually independent Burst Mode sub-state machines, the input of each sub-state machine is an input signal of an external environment, and the sub-state machines do not have constraint relation on input and output; then, respectively synthesizing each sub-state machine by using the existing asynchronous control circuit synthesis tools (3D of the university of California and MINIMALIST of the university of Columbia) to obtain corresponding burst mode sub-control circuit modules; then, each sub-control circuit module is adjusted, and an input signal latch module is added to solve the arbitration problem among the sub-control circuit modules (since the sub-control circuit modules are independent from each other, the change of input signals may cause a plurality of sub-control circuit modules to be driven simultaneously, so that the sub-control circuit modules allowed to operate need to be reasonably selected); and finally, connecting the sub-control circuit modules to obtain a final burst mode asynchronous control circuit. The method has two disadvantages: firstly, hierarchical decomposition of a burst mode state machine is carried out by adopting a depth-first search algorithm, so that the decomposition efficiency is low; secondly, the arbitration mechanism of the sub-control circuit modules requires that strict time sequence constraints exist among the sub-control circuit modules, and the strict time sequence constraints are difficult to meet in the circuit design process, so that the method is difficult to effectively put into practical application.
The invention content is as follows:
the invention aims to solve the technical problem of improving the design method of the existing burst mode asynchronous control circuit, improving the design scale and enabling the large-scale burst mode asynchronous control circuit to be practical. Decomposing the state machine by utilizing a directed loop set of a corresponding diagram of the burst mode state machine to obtain mutually independent burst mode sub-state machines; adjusting each sub-state machine, and realizing four-segment handshake communication between corresponding sub-state machines by adopting a request/response signal; the burst mode interface state machine is designed to address the arbitration problem between the corresponding sub-state machines.
The technical scheme of the invention is as follows:
the invention comprises six steps of decomposing a burst mode state machine, adjusting a burst mode sub-state machine, designing a burst mode interface state machine, readjusting the burst mode sub-state machine, realizing a sub-control circuit module, an interface control circuit module and a synthetic burst mode asynchronous control circuit. The method comprises the following specific steps:
1. and performing hierarchical decomposition on the M by using a directed loop set of a corresponding graph of the burst mode state machine M to obtain a K-level burst mode sub-state machine, wherein K is the total level of the burst mode sub-state machine obtained by M decomposition.
The decomposition process comprises the following steps:
(1) Determining an initial sub-state machine set S according to a directed loop set C of the corresponding directed graph G = < V, E > of M: the corresponding structure of any directed loop C (C e C) in M, including state nodes, directed edges and corresponding burst inputs and burst outputs, constitutes an initial sub-state machine S (S e S).
(2) Determining a decision node set D: and all the vertexes with out degrees larger than 2 in G are corresponding state nodes in M, namely the judgment nodes.
(3) M start state node v 0 To the nearest decision node d 1 The directed path between E D and the corresponding burst input and burst output form a first-stage burst mode sub-state machine, and the initial state node of the first-stage sub-state machine is v 0 (ii) a All containing decision node d 1 The initial sub-state machines are all second-stage burst mode sub-state machines, and the initial state node of the second-stage sub-state machine is d 1 。
(4) The number of sub-state machine stages N =2 is set.
(5) All nth level burst mode sub-state machines are deleted from S.
(6) Judging S, and if S is not empty, skipping to the step (7); and if S is null, M decomposition is completed.
(7) Judging the N-th-level burst mode sub-state machines one by one, and if other judgment nodes (which may not be unique and are denoted as d without losing generality) exist except the initial state node N i I =1, \8230;, l is the number of decision nodes except the start state node in the nth-level burst-mode sub-state machine), all S include d N i The initial sub-state machines are all N + 1-level burst mode sub-state machines, and the initial state node is d N i 。
(8) And (5) adjusting the number of stages of the sub-state machine N = N +1, and jumping to the step (6).
2. And adding extra request/response signals to adjust all burst mode sub-state machines from the 1 st stage to the K th stage, realizing four-segment handshake communication between two adjacent stages of sub-state machines, and removing the time sequence requirement between the two adjacent stages of sub-state machines. The method for adjusting all burst mode sub-state machines from the 1 st stage to the Kth stage is as follows:
(1) Burst mode sub-state machine M at level N N (1. Ltoreq. N. Ltoreq.K-1)Adding auxiliary state node v N And a decision node d other than the initial state node N Connecting; set directed edges<d N ，v N >The corresponding burst input transition and burst output transition are ack respectively N + and req N -; set a directed edge<v N ，d N >The corresponding burst input transition and burst output transition are ack respectively N -and req N +; with d N Directed edge as an end point: (<v N ，d N >Except) burst output transitions increase req N +. (+ represents a transition of the signal from 0 to 1, -represents a transition from 1 to 0)
(2) Memory M N The corresponding (N + 1) th-level burst mode sub-state machines are respectively M N+1 1 ，…，M N+1 L L is the number of the (N + 1) th-level burst mode sub-state machines and is in M N+1 i (i =1, \8230;, L) node d is in the initial state N The burst input transition and the burst output transition of the directed edge as the starting point respectively increase the req N+1 i + and ack N+1 i +, with node d N Increasing req for burst input and burst output transitions, respectively, of directed edges of an endpoint N+1 i -and ack N+1 i -。
M N With any N +1 th-level burst mode sub-state machine M N+1 i The communication process of (2) is as follows:
(1)M N enter state d N While simultaneously applying the signals req N Setting to be high, starting handshake operation and requesting to trigger the (N + 1) th-level sub-state machine;
(2)M N+1 i receiving from M N Is requested to be req N+1 i Then the signal ack N+1 i Set high for confirmation;
(3)M N receiving from M N+1 i Ack of N + go to state v N While simultaneously applying the signals req N Set to low, proceed to handshake operationResetting the rows;
(4)M N+1 i receiving from M N Is requested to reset req N+1 i -, then the signal ack N+1 i Setting to be low, and adding confirmation;
(5)M N receiving from M N+1 i In response to the response signal ack N +, back to state d N While the signal req is repeated N Set high, and new communication is performed.
For M N With any N +1 th-level burst mode sub-state machine M N+1 i In other words, M communicates using a delay-independent four-segment handshake protocol N+1 i Receive M N The trigger request sent is only executed after, M N+1 i When executing M N Is interrupted, M N+1 i M completed execution N Can be executed, and thus the timing requirements between adjacent two levels of sub-state machines can be effectively removed.
Due to M N+1 1 ，…，M N+1 L The sub-state machines are independent from each other, that is, there is no constraint relation between the input and output of the sub-state machines, so that a change of a certain input signal may cause a plurality of sub-state machines to be triggered simultaneously, thereby causing an arbitration problem of the sub-state machines.
3. And designing a burst mode interface state machine between two adjacent stages of sub-state machines to arbitrate whether the sub-state machines trigger or not.
Sub-state machine M for any Nth order burst mode N And its corresponding N + 1-th-level burst mode sub-state machine M N+1 1 ，…，M N+1 L In other words, N is more than or equal to 1 and less than K, and L is the total number of the (N + 1) th-level burst mode sub-state machines; sub-state machine M N The decision node other than the initial state node is d N Auxiliary state node is v N ， By node d N Directed edge e as starting point N ≠<d N ，v N >The corresponding burst input is BI N With a corresponding burst input transition of trans i (e N ) (ii) a Sub-state machine M N+1 i (i =1, \8230;, L) node d in the initial state N Directed edge e as starting point N+1 i The corresponding burst input is BI N+1 i With corresponding burst input transition to trans i (e N+1 i )。
The design method of the interface state machine comprises the following steps:
(1) And determining input and output signals of the interface state machine. Interface state machine and M N ，M N+1 1 ，…，M N+1 L Connected, the input signal including burst input BI N ，BI N+1 1 ，…，BI N+1 L Son state machine M N Request signal req of N And a sub-state machine M N+1 1 ，…，M N+1 L Corresponding answer signal ack N+1 1 ，…，ack N+1 L (ii) a The output signal comprising a sub-state machine M N In response to the response signal ack N Son state machine M N+1 1 ，…，M N+1 L Corresponding request signal req N+1 1 ，…，req N+1 L And an auxiliary signal pseu.
(2) The number of interface state machine state nodes is determined. When N =1, the interface state machine only needs to solve M N+1 1 ，…，M N+1 L The arbitration problem is triggered, at this time, 3L +1 state nodes are needed, and are marked as d N ，v 1 1 ，…，v L 1 ，v 1 2 ，…，v L 2 ，v 1 3 ，…，v L 3 . When 1 < N < K, the interface state machine not only needs to solve M N+1 1 ，…，M N+1 L And needs to solve M N And M N+11 ，…，M N+1 L The problem of triggering an arbitration between the two,at this time, it is necessary to3L+3A state node, noteIs composed ofd N ，v 0 1 ，v 1 1 ，…，v L 1 ，v 0 2 ，v 1 2 ，…，v L 2 ，v 1 3 ，…，v L 3 。
(3) Directed edges between state nodes and their corresponding burst input/burst output transitions are determined.
a) Directed edge<d N ，v 0 1 >The corresponding burst input transitions to req N +，trans i (e N ) Burst output transitions to pseu +; directed edge<v 0 1 ，v 0 2 >Corresponding burst input transition to req N Burst output transition to pseu-; directed edge<v 0 2 ，d N >Corresponding burst input transition toFor any signal x ∈ BI N If x + ∈ trans i (e N ) Then, then
If x-is equal to trans i (e N ) Then, then
b) For any i =1, \8230;, L, directed edge<d N ，v i 1 >Corresponding burst input transition toreq N +，trans i (e N+1 i >Burst output transition to req N+1 i +; directed edge<v i 1 ，v i 2 >The corresponding burst input transition is ack N+1 i +, burst output transition to ack N +; directed edge<v i 2 ，v i 3 >Corresponding burst input transitions to
Burst output transition to req N+1 i -; directed edge<v i 3 ，d N >，
Corresponding burst input transition to ack N+1 i Burst output transition to ack N -。
For the first level of sub-state machines, divide by<d 1 ，v 1 >There is no other node d 1 For the starting point, the interface state machine connecting the first level sub state machine and the second level sub state machine does not need to output the auxiliary signal pseu, so the interface state machine is the simplest.
Burst mode sub-state machine M at level N N And the corresponding N +1 st-level burst mode sub-state machine M N+1 1 ，…，M N+1 L After designing the interface state machine, when M N Enter State d N When, M N The starting handshake operation requests the interface state machine to arbitrate, the interface state machine judges according to the change condition of the external environment input signal, and the interface state machine arbitrates whether the sub-state machine is triggered, the method is as follows:
(1) Transition req if burst input N +，trans i (e N+1 i ) First active, then the interface state machine enters state v i 1 Selectively triggering the N +1 th level sub-state machine M N+1 i The specific process is as follows:
a) Interface state machine receives information from M N Of the arbitration request req N + when burst input transitions trans i (e N ) Enter state v when active i 1 While simultaneously applying the signals req N+1 i Set high, request trigger M N+1 i ；
b)M N+1 i Receiving a trigger request req from a state machine N+1 i Ack, signal N+1 i Setting to be high, and confirming the triggering request;
c) Interface state machine receives information from M N+1 i In response to the response signal ack N+1 i Enter state v i 2 While the signal ack is transmitted N Set high, acknowledge the arbitration request;
d)M N receiving a reply signal ack from the interface state machine N Entering state v N While req will be simultaneously N Resetting the arbitration request when the value is set to be low;
e) Interface state machine receives information from M N Arbitrated reset request req of N Entering state v i 3 All are the same asTime will req N+1 i Resetting the triggering request when the trigger is set to be low;
f)M N+1 i receiving a triggered reset request req from an interface state machine N+1 i Waiting for the corresponding burst input transition to be active and then entering state d N While simultaneously applying the signal ack N+1 i Set to low, confirm the trigger reset;
g) Interface state machine receives information from M N+1 i In response to the response signal ack N+1 i -, go back to the state d N While the signal ack is transmitted N Set to low, affirm the arbitration reset;
h)M N receiving a reply signal ack from the interface state machine N +, back to state d N While re-applying the signal req again N Set high, a new arbitration is performed.
(2) Transition req if burst input N +，trans i (e N ) First active, then the interface state machine enters state v 0 1 Choose to continue operation M N The specific process is as follows:
a) Interface state machine receives information from M N Of (2) an arbitration request req N + when burst input transitions trans i (e N+1 i ) Enter state v when active 0 1 Setting the signal pseu to be high;
b)M N receiving status from an interfaceThe auxiliary signal of the machine transits pseu +, then req N Resetting is carried out when the voltage is set to be low;
c) The interface state machine receives a reset request req N Entering state v 0 2 While the signal pseu is set low;
d)M N receiving an auxiliary signal transition pseu from an interface state machine, waiting that the corresponding burst input transition is effective, and further continuing to operate;
e) The interface state machine waits for the corresponding burst input transition to be active and then returns to state d N Wait for a new arbitration request.
4. Readjusting all burst mode sub-state machines M from level 2 to level K-1 N And N is more than or equal to 2 and less than K, so that the arbitration between the N-level burst mode sub-state machine and the corresponding N + 1-level sub-state machine is realized.
Sub-state machine M for Nth order burst mode N And the corresponding N +1 stage sub-state machine M N+1 1 ，…，M N+1 L In other words, when arbitration is performed using the interface state machine, M N Whether the operation is continued or a certain N + 1-level sub-state machine is triggered and the operation is finished is determined according to whether the auxiliary output signal pseu of the interface state machine is transited or not. To this end, M N A new input signal pseu needs to be introduced for readjustment.
M N The decision nodes other than the initial state node are d N Removing auxiliary status node v N Outer and d N The nodes connected by directed edges are v c (ii) a Directed edge<d N ，v N >Corresponding burst output transition req N -, has a directional edge e N ＝<d N ，v c >The corresponding burst input transition and burst output transition are trans respectively i (e N ) And trans o (e N )。
The adjusting method comprises the following steps:
(1) Deleting directed edges<d N ，v c >And its corresponding burst inputTransition trans i (e N ) And burst output transition o (e N )；
(2) Adding extra state nodes v and setting directed edges<d N ，v>The corresponding burst input transition and burst output transition are pseu + and req, respectively N -; set directed edges<v，v c >The corresponding burst input transition and burst output transition are pseu-, trans-, respectively i (e N ) And trans o (e N )。
5. And performing state reduction, state assignment, logic synthesis and process mapping on all burst mode sub-state machines and burst mode interface state machines by adopting the existing asynchronous control circuit design method and tool based on the finite state machine to obtain corresponding sub-control circuit modules and interface control circuit modules.
6. And connecting all the sub-control circuit modules and the interface control circuit module according to corresponding signals to obtain the final burst mode asynchronous control circuit.
The invention can achieve the following technical effects:
1. the invention fully utilizes the directed loop set of the corresponding graph of the burst mode state machine to carry out hierarchical decomposition on the state machine, and has higher decomposition efficiency and larger processing scale than a decomposition algorithm based on depth-first search;
2. the arbitration problem among the sub state machines is effectively solved through the additionally designed burst mode interface state machine, the design method is simple, and no time sequence constraint is required to be added;
3. the four-segment handshake protocol between the corresponding sub-state machines is communicated by using the request/response signals, so that the time sequence constraint requirement between the sub-state machines is effectively eliminated, and the difficulty of logic synthesis is reduced.
Description of the drawings:
FIG. 1 is a timing diagram of a four-segment handshake communication;
FIG. 2 is a flow chart of a method for designing an asynchronous control circuit based on a finite state machine;
FIG. 3 is a block diagram of a burst mode asynchronous control circuit;
FIG. 4 is a flow chart of a burst mode asynchronous control circuit design method based on hierarchical decomposition proposed by university of Columbia;
FIG. 5 is a flow chart of a burst mode asynchronous control circuit design method based on hierarchical decomposition according to the present invention;
FIG. 6 is a typical burst mode state machine M;
FIG. 7 is a directed graph and set of directed loops corresponding to the burst mode state machine M shown in FIG. 6;
FIG. 8 is a burst mode sub-state machine after decomposition of M using the present invention;
FIG. 9 is a diagram of a burst mode sub-state machine modified from that shown in FIG. 8;
FIG. 10 is a burst mode sub-state machine after a re-adjustment of the burst mode sub-state machine of FIG. 9;
FIG. 11 is a burst mode interface state machine designed for M using the present invention;
fig. 12 is a schematic diagram illustrating a connection manner between the interface state machine and the sub-state machine shown in fig. 11.
The specific implementation mode is as follows:
fig. 1 is a timing diagram of request/acknowledge signals when performing four-segment handshake communication between two asynchronous circuit modules. When data is synchronously transmitted between two asynchronous circuit modules a, B, four steps are typically involved:
(1) The module A sends data and sets a request signal req high to start handshake; (2) The module B receives the data, then sets the ack of the response signal to be high to confirm, indicates that the data is received, and starts corresponding operation; (3) the module A sets the request signal req to be low for resetting; and (4) the module B sets the acknowledgement signal ack to be low to complete the handshake.
FIG. 2 is a flow chart of a design method of an asynchronous control circuit based on a finite state machine. The asynchronous circuit design method based on the finite state machine model is basically the same as the design flow of a synchronous circuit, firstly, finite state machine description is converted into an asynchronous flow table, secondly, state reduction and assignment are carried out to obtain a binary asynchronous flow table, then, logic synthesis is carried out to determine a logic expression of an output variable, and finally, a gate-level netlist of the circuit is obtained through process mapping.
Fig. 3 is a block diagram of a burst mode asynchronous control circuit. The burst mode asynchronous control circuit is composed of burst input, burst output, a combinational logic circuit and a feedback loop, wherein the combinational logic circuit adopts a finite delay model, and the feedback loop adopts an infinite feedback delay model. The current state of the circuit is maintained in a feedback loop, and the burst output and the next state of the circuit are determined by the burst input, the current state and the feedback of part of the output signal.
FIG. 4 is a flow chart of a burst mode asynchronous control circuit design method based on hierarchical decomposition promulgated by university of Columbia. For the description of a given complex burst mode state machine, firstly, a depth-first search algorithm is adopted to carry out hierarchical decomposition to obtain mutually independent burst mode sub-state machines; secondly, performing logic synthesis on each sub-state machine by using the existing burst mode state machine synthesis tools (such as 3D of the university of California and MINIMALIST of the university of Columbia) to obtain corresponding burst mode sub-control circuit modules; and finally, connecting the sub-control modules according to the corresponding input and output signal relationship to obtain the final burst mode asynchronous control circuit.
Fig. 5 is a flow chart of a design method of a burst mode asynchronous control circuit based on hierarchical decomposition, which comprises 6 steps in total: (1) Carrying out hierarchical decomposition on the state machine by utilizing a directed loop set of a directed graph corresponding to the burst mode state machine; (2) Adjusting the burst mode sub-state machines by adding extra request/response signals to realize four-segment handshake communication between the corresponding sub-state machines; (3) Designing a burst mode interface state machine to solve the arbitration problem of the sub-state machines; (4) Adjusting the burst mode sub-state machine again to realize arbitration between the nth level burst mode sub-state machine and the corresponding N +1 level sub-state machine; (5) Performing logic synthesis on each sub-state machine and the interface state machine to obtain a sub-control circuit module and an interface circuit module; (6) And connecting the sub-control modules to obtain the final burst mode asynchronous control circuit.
Fig. 6 is a typical burst mode state machine M with state nodes v0, v1, v2, v3, v4, v5; the directed edge is<v0，v1>，<v1，v2>，<v2，v3>，<v3，v2>，<v2，v4>，<v4，v5>，<v5，v4>，<v4，v1>(ii) a The input signal is a in ，b in ，c in And d in The output signal is y out And z out The start state node is v0.
Fig. 7.1 is directed graph G for M. Fig. 7.2, 7.3 and 7.4 are directed loops of the directed graph G, constituting a directed loop set C.
Fig. 8 is a burst mode sub-state machine obtained by decomposing M shown in fig. 6 by using the present invention. FIG. 8.1 shows a first level burst mode sub-state machine M 1 FIG. 8.2 shows a second level burst mode sub-state machine M 2 1 FIG. 8.3 shows the second level burst mode sub-state machine M 2 2 FIG. 8.4 shows a third level burst mode sub-state machine M 3 1 。
The specific decomposition process is as follows:
(1) An initial set S of sub-state machines of M is generated. The corresponding structure of the directed loop in M in the directed loop set C comprises a state node, a directed edge and a corresponding burst input and a burst output, and forms an initial sub-state machine of M. The directed loops shown in fig. 7.2, 7.3 and 7.4 correspond to the initial sub-states shown in fig. 8.2, 8.3 and 8.4, respectively.
(2) Determining a set of decision nodes D, D = { v2, v4} in M.
(3) The directed path between the start state node v0 to the decision node v2 in M and the corresponding burst input and burst output constitute a first-level burst mode sub-state machine M 1 The start state node is v0.
(4) The initial sub-state machine containing node v2 is the second level burst mode sub-state machine M 2 1 And M 2 2 The start state nodes are all set to v2.
(5) For M 2 2 In other words, there is a decision node v4 in addition to the start state node v2, so the initial sub-state machine containing v4 is the third-level burst-mode sub-state machine M 3 1 The start state node is set to v4.
Fig. 9 is a diagram of an adaptation of the burst mode sub-state machine shown in fig. 8, i.e., the burst mode sub-state machine after the addition of an additional request/acknowledge signal. The adjusted burst mode sub-state machines shown in fig. 9.1, 9.2, 9.3 and 9.4 correspond to the burst mode sub-state machines shown in fig. 8.1, 8.2, 8.3 and 8.4, respectively.
The specific adjusting steps are as follows:
(1) At M as shown in FIG. 8.1 1 In, add auxiliary state node v 1 Is connected with the node v 2; set up directed edges<v2，v 1 >The corresponding burst input transition and burst output transition are ack respectively 1 + and req 1 -; set up directed edges<v 1 ，v2>The corresponding burst input transition and burst output transition are ack respectively 1 -and req 1 +; with a directional edge<v1，v2>Burst output transition of (1) increasing req 1 +。
(2) At M as shown in FIG. 8.2 2 1 In, the directed edge<v2，v3>The burst input transition and the burst output transition of (1) respectively increase the req 2 1 + and ack 2 1 +, directed edge<v3，v2>Burst input transition and burst output transition ofIncrease req respectively 2 1 -and ack 2 1 -。
(3) At M as shown in FIG. 8.3 2 2 In, there is an edge<v2，v4>The burst input transition and the burst output transition of (1) respectively increase the req 2 2 + and ack 2 2 +, directed edge<v1，v2>Respectively increasing req for burst input transitions and burst output transitions 2 2 -and ack 2 2 -。
(4) At M as shown in FIG. 8.3 2 2 In, add auxiliary state node v 2 Is connected with the node v 4; set up directed edges<v4，v 2 >The corresponding burst input transition and burst output transition are ack respectively 2 + and req 2 -; set directed edges<v 2 ，v4>The corresponding burst input transition and burst output transition are ack respectively 2 -and req 2 +; directed edge<v2，v4>Burst output transition of (1) increasing req 2 +。
(5) At M as shown in FIG. 8.4 3 1 In, there is an edge<v4，v5>The burst input transition and the burst output transition of (1) respectively increase the req 3 1 + and ack 3 1 +, directed edge<v5，v4>Respectively increasing req for burst input transitions and burst output transitions 3 1 -and ack 3 1 -。
Fig. 10 shows the burst mode sub-state machine after the output auxiliary signal pseu of the incoming interface state machine has been re-conditioned. Second level burst mode sub-state machine M for M 2 1 And M 2 2 In other words, M is due to 2 1 There is no corresponding third-level burst-mode sub-state machine, so only M needs to be adjusted 2 2 。
The specific adjusting steps are as follows:
(1) Deleting directed edges<v4，v1>And its corresponding burst input transition a in +，b in +；
(2) Adding extra state nodes v and setting directed edges<v4，v>The corresponding burst input transition and burst output transition are pseu + and req, respectively 2 -；
(3) Set directed edges<v，v1>The corresponding burst input transition is pseu-, a in +，b in +。
FIG. 11 is a burst mode interface state machine designed according to the present invention, the interface state machine A of FIG. 11.1 being used to solve the first level burst mode sub-state machine M of FIG. 9.1 1 And the second-stage burst-mode sub-state machine M shown in FIGS. 9.2 and 10 2 1 、M 2 2 To arbitration issues in between. Interface State machine B shown in FIG. 11.2So as to solve the second-level burst mode sub-state machine M shown in FIG. 10 2 2 And the third-stage burst mode sub-state machine M shown in FIG. 9.4 3 1 To arbitration issues in between.
The arbitration process of the interface state machine A is as follows: m 1 Enter state v2 while simultaneously signaling req 1 Setting to be high, starting handshake operation and requesting an interface state machine A to arbitrate; the interface state machine A judges according to the change condition of the external environment input signal, if the input signal changes into the transition req in burst 1 +，b in +，c in + Prior Effect, interface state machine A enters state v 1 1 Selection trigger M 2 1 (ii) a If input transition req 1 +，a in Before valid, then interface state machine A enters state v 2 1 Selection trigger M 2 2 。
1. When the interface state machine A enters the state v 1 1 Selection trigger M 2 1 The specific execution process is as follows:
a) Interface state machine A receives data from M 1 Of the arbitration request req 1 When burst input transition b in +，c in Enter State v when active 1 1 While simultaneously applying the signal req 2 1 Set high, request trigger M 2 1 ；
b)M 2 1 Receiving a trigger request req from the interface state machine A 2 1 +, go to state v3 while asserting signal ack 2 1 Setting to be high, and confirming the triggering request;
c) Interface state machine A receives data from M 2 1 Ack of 2 1 Entering state v 1 2 While the signal ack is transmitted 1 Set high, acknowledge the arbitration request;
d)M 1 receives the acknowledge signal ack from the interface state machine A 1 + go to state v 1 While req will be simultaneously transmitted 1 Resetting the arbitration request when the value is set to be low;
e) Interface state machine A receives data from M 1 Arbitrated reset request req of 1 Entering state v 1 3 At the same time, req 2 1 Resetting the trigger request when the trigger request is set to be low;
f)M 2 1 receiving a trigger reset request req from the interface state machine a 2 1 Wait for burst input transition b in -，c in Active and then return to state v2 while simultaneously asserting signal ack 2 1 Set to low, confirm the trigger reset;
g) Interface state machine A receives data from M 2 1 In response to the response signal ack 2 1 -, back to the state v2 whileWill signal ack 1 Set to low, acknowledge arbitration reset;
h)M 1 receives the acknowledge signal ack from the interface state machine A 1 Return to state v2 while the signal req is again asserted 1 Set high for new arbitration.
2. Interface state machine a enters state v 2 1 Selecting trigger M 2 2 Specific execution process of time and entering state v thereof 1 1 Selecting trigger M 2 1 Is at firstSo that the effect is achieved.
The arbitration process of the interface state machine B is as follows: m 2 2 Enter state v4 while simultaneously signaling req 2 Setting to be high, starting handshake operation and requesting an interface state machine B to arbitrate; the interface state machine B judges according to the change condition of the external environment input signal, if the burst input changes into the transition req 2 +，a in +，b in + active first, then interface state machine B enters state v 0 1 Choose to continue operation M 2 2 (ii) a Transition req if burst input 2 +，d in + Prior Effect, then interface state machine B enters state v 1 1 Selection trigger M 3 1 。
1. Interface state machine B enters state v 1 1 Selecting trigger M 3 1 Specific execution process of time and interface state machine A enter state v 1 1 Selecting trigger M 2 1 The time is substantially the same.
2. Interface state machine B enters state v 0 1 Choose to continue operation M 2 2 The specific execution process is as follows:
a) Interface state machine B receives the message from M 2 2 Of the arbitration request req 2 +, when burst input transitions d in Enter State v when active 0 1 Setting the signal pseu to be high;
b)M 2 2 receiving an auxiliary signal transition pseu + from the interface state machine B, entering state v and converting req 2 Resetting is carried out when the voltage is set to be low;
c) Interface state machine B receives a reset request req N Entering state v 0 2 While setting the signal pseu low;
d)M 2 2 receiving an auxiliary signal transition pseu-from the interface state machine B, waiting for a burst input transition a in -，b in Valid, then enter state v1 to continue operation;
e) Interface state machine wait burstInput transition a in -，b in Valid, then back to state v4, etcWaiting for a new arbitration request.
FIG. 12.1 is the interface state machine A of FIG. 11.1 and the first-level burst-mode sub-state machine M of FIG. 9.1 1 FIG. 9.2 shows a second level burst mode sub-state machine M 2 1 And a second-stage burst-mode sub-state machine M shown in FIG. 10 2 2 Schematic diagram of the connection mode. Interface state machine a passes through handshake signal req 1 And ack 1 And M 1 Connected via a handshake signal req 2 1 And ack 2 1 And M 2 1 Connected via a handshake signal req 2 2 And ack 2 2 And M 2 2 Are connected. FIG. 12.2 shows the interface state machine B of FIG. 11.2 and the second level burst mode sub-state machine M of FIG. 10 2 2 And a third level burst mode sub-state machine M shown in FIG. 9.4 3 1 The connection mode between the two is shown schematically. Interface state machine B passes handshake signal req 2 And ack 2 And auxiliary signals pseu and M 2 2 Are connected by a signal req 3 1 And ack 3 1 And M 3 1 Are connected.
Claims (8)
1. A burst mode asynchronous control circuit design method comprises the steps of decomposing a burst mode state machine, realizing a sub-control circuit module and synthesizing a burst mode asynchronous control circuit, and is characterized by further comprising three steps of adjusting the burst mode sub-state machine, designing a burst mode interface state machine and readjusting the burst mode sub-state machine between the step of decomposing the burst mode state machine and the step of realizing the sub-control circuit module, wherein the specific steps are as follows:
the method comprises the steps that firstly, hierarchical decomposition is carried out on M by utilizing a directed loop set of a corresponding graph of the burst mode state machine M to obtain a K-level burst mode sub-state machine, wherein K is the total level of the burst mode sub-state machine obtained by M decomposition;
adding additional request/response signals, adjusting all burst mode sub-state machines from the 1 st stage to the K th stage, realizing four-segment handshake communication between two adjacent stages of sub-state machines, and removing the time sequence requirement between the two adjacent stages of sub-state machines;
thirdly, designing a burst mode interface state machine between two adjacent stages of sub state machines, and arbitrating whether the sub state machines are triggered or not;
fourth, all burst mode sub-state machines M of stages 2 to K-1 are adjusted again N And N is more than or equal to 2 and less than K, and arbitration between the N-level burst mode sub-state machine and the corresponding N + 1-level sub-state machine is realized;
fifthly, performing state reduction, state assignment, logic synthesis and process mapping on all the burst mode sub-state machines and the burst mode interface state machines to obtain corresponding sub-control circuit modules and interface control circuit modules;
and sixthly, connecting all the sub control circuit modules and the interface control circuit module according to corresponding signals to obtain a final burst mode asynchronous control circuit.
2. The design method of burst mode asynchronous control circuit as claimed in claim 1, wherein said hierarchical decomposition procedure is:
(1) Determining an initial sub-state machine set S according to a directed loop set C of the corresponding directed graph G = < V, E > of M: the corresponding structure of any directed loop C (C belongs to C) in M comprises a state node, a directed edge and corresponding burst input and burst output, and an initial sub-state machine S (S belongs to S) is formed;
(2) Determining a decision node set D: all the corresponding state nodes of the vertexes with out degrees larger than 2 in the G in the M are judgment nodes;
(3) Starting state node v in M 0 To the nearest decision node d 1 The directed path between E D and the corresponding burst input and burst output form a first-stage burst mode sub-state machine, and the initial state node of the first-stage sub-state machine is v 0 (ii) a All containing decision nodes d 1 The initial sub-state machines of (1) are all second-stage burst mode sub-state machines, and the initial state node of the second-stage sub-state machines is d 1 ；
(4) Setting the number of the sub state machine stages N =2;
(5) Deleting all Nth-level burst mode sub-state machines from the S;
(6) Judging S, and if S is not empty, skipping to the step (7); if S is empty, M decomposition is completed;
(7) Judging the N-th-level burst mode sub-state machines one by one, if other judging nodes d except the initial state node exist N i I =1, \ 8230;, l is the number of decision nodes except the start state node in the Nth-level burst mode sub-state machine, and all S include d N i The initial sub-state machines are all N +1 level burst mode sub-state machines, and the initial state node is d N i ；
(8) And (5) adjusting the number of stages of the sub-state machine N = N +1, and jumping to the step (6).
3. A burst mode asynchronous control circuit design method as claimed in claim 1, wherein the method of adjusting all burst mode sub-state machines of stages 1 to K is:
(1) Burst mode sub-state machine M at Nth level N (N is more than or equal to 1 and less than or equal to K-1), adding auxiliary state nodes v N And decision nodes d other than the initial state nodes N Connecting; set directed edges<d N ，v N >The corresponding burst input transition and burst output transition are ack respectively N + and req N -; set directed edges<v N ，d N >The corresponding burst input transition and burst output transition are ack respectively N -and req N +; with d N Directed edge as an end point: (<v N ，d N >Except) burst output transitions increase req N +; + represents a transition of the signal from 0 to 1, -represents a transition from 1 to 0;
(2) Memory M N The corresponding (N + 1) th-level burst mode sub-state machines are respectively M N+1 1 ，…，M N+1 L L is the number of the (N + 1) th-level burst mode sub-state machines, and is in M N+1 i (i =1, \8230;, L) node d is in the initial state N The burst input transition and the burst output transition of the directed edge as the starting point respectively increase the req N+1 i + and ack N+1 i + to node d N Increasing req for burst input and burst output transitions, respectively, of directed edges of an endpoint N+1 i -and ack N+1 i -。
4. A burst mode asynchronous control circuit design method as defined in claim 3 wherein said M N With arbitrary N +1 level burst mode sub-state machine M N+1 i The communication process of (2) is as follows:
(1)M N enter state d N While simultaneously applying the signals req N Setting to be high, starting handshake operation and requesting to trigger the (N + 1) th-level sub-state machine;
(2)M N+1 i receiving from M N Trigger request req of N+1 i Then feeds the signal ack N+1 i Set high for confirmation;
(3)M N receiving from M N+1 i In response to the response signal ack N Entering state v N While simultaneously applying the signal req N Resetting the handshake operation when the voltage is set to be low;
(4)M N+1 i receiving from M N Is requested to reset req N+1 i -, then the signal ack N+1 i Setting to be low, and confirming;
(5)M N receiving from M N+1 i In response to the response signal ack N +, back to state d N While sending the letter againNumber req N Set high, new communication is performed.
5. A method of designing a burst mode asynchronous control circuit as claimed in claim 1, wherein said interface state machine is designed by:
(1) Determining input and output signals of an interface state machine: interface state machine and M N ，M N+1 1 ，…M N+1 L Connected, the input signal comprising burst input BI N ，BI N+1 1 ，…，BI N+1 L Son state machine M N Request signal req of N And a sub-state machine M N+1 1 ，…，M N+1 L Corresponding answer signal axk N+1 1 ，…，ack N+1 L (ii) a The output signal comprising a sub-state machine M N In response to the response signal ack N Son state machine M N+1 1 ，…，M N+1 L Corresponding request signal req N+1 1 ，…，req N+1 L And an auxiliary signal pseu;
(2) Determining the number of interface state machine state nodes: when N =1, the interface state machine only needs to solve M N+1 1 ，…，M N+1 L The arbitration problem is triggered, and at this time, 3L +1 state nodes are needed and are marked as d N ，v 1 1 ，…，v L 1 ，v 1 2 ，…，v L 2 ，v 1 3 ，…，v L 3 (ii) a When 1 < N < K, the interface state machine not only needs to solve M N+1 1 ，…，M N+1 L And needs to solve M N And M N+1 1 ，…，M N+1 L Trigger arbitration problem in between, at which time, 3L +3 states are requiredNode, denoted as d N ，v 0 1 ，v 1 1 ，…，v L 1 ，v 0 2 ，v 1 2 ，…，v L 2 ，v 1 3 ，…，v L 3 。
(3) Determining directed edges and their corresponding burst input/burst output transitions between state nodes:
a) Directed edge<d N ，v 0 1 >Corresponding burst input transition to req N +，trans i (e N ) Burst output transitions to pseu +; directed edge<v 0 1 ，v 0 2 >Corresponding burst input transition to req N -, burst output transition to pseu-; directed edge<v 0 2 ，d N >Corresponding burst input transition to
(ii) a For arbitrary signals x ∈ BI N If x +. Epsilon.trans i (e N ) Then, then
If x-e trans i (e N ) Then, then
b) For any i =1, \8230;, L, directed edge<d N ，v i 1 >Corresponding burst input transition to req N +，trans i (e N+1 i ) Burst output transition to req N+1 i +; directed edge<v i 1 ，v i 2 >Corresponding burstInput transition is ack N+1 i (ii) burst output transition to ack N +; directed edge<v i 2 ，v i 3 >Corresponding burst input transition to req N -，
Burst output transition to req N+1 i -; directed edge<v i 3 ，d N >，
Corresponding burst input transition to ack N+1 i Burst output transition to ack N -。
6. A burst mode asynchronous control circuit design method as claimed in claim 1 or 5, characterized in that said interface state machine arbitrates whether a sub-state machine triggers or not by:
(1) Transition req if burst input N +，trans i (e N+1 i ) First active, then the interface state machine enters state v i 1 Selectively triggering the N +1 th level sub-state machine M N+1 i The specific process is as follows:
a) Interface state machine receives information from M N Of (2) an arbitration request req N + when burst input transitions trans i (e N ) Enter state v when active i 1 While simultaneously applying the signals req N+1 i Set high, request trigger M N+1 i ；
b)M N+1 i Receiving a trigger request req from a state machine N+1 i Ack, signal N+1 i Setting to be high, and confirming the triggering request;
c) Interface state machine receives information from M N+1 i Ack of N+1 i + go to state v i 2 While the signal ack is transmitted N Set high, acknowledge the arbitration request;
d)M N receiving an acknowledge signal ack from the interface state machine N + go to state v N While req will be simultaneously N Resetting the arbitration request when the signal is set to be low;
e) Interface state machine receives information from M N Arbitrated reset request req of N -, entering the Statev i 3 At the same time, req N+1 i Resetting the triggering request when the trigger is set to be low;
f)M N+1 i receiving a triggered reset request req from an interface state machine N+1 i Waiting for the corresponding burst input transition to be active and then entering state d N While the signal ack is transmitted N+1 i Set to low, confirm the trigger reset;
g) Interface state machine receives information from M N+1 i In response to the response signal ack N+1 i -, go back to the state d N While the signal ack is transmitted N Set to low, acknowledge arbitration reset;
h)M N receiving a reply signal ack from the interface state machine N +, back to state d N While re-applying the signal req again N Setting to be high, and carrying out new arbitration;
(2) Transition req if burst input N +，trans i (e N ) First active, then the interface state machine enters state v 0 1 Choose to continue operation M N The specific process is as follows:
a) Interface state machine receives information from M N Of (2) an arbitration request req N + when burst input transitions trans i (e N+1 i ) Enter state v when active 0 1 Setting the signal pseu to be high;
b)M N receiving an auxiliary signal transition pseu + from an interface state machine and then comparing req N Resetting is carried out when the voltage is low;
c) The interface state machine receives a reset request req N Entering state v 0 2 While the signal pseu is set low;
d)M N receiving an auxiliary signal transition pseu from an interface state machine, waiting that the corresponding burst input transition is effective, and further continuing to operate;
e) The interface state machine waits for a corresponding burst input changeGo active and then return to state d N Wait for a new arbitration request.
7. The burst-mode asynchronous control circuit design method as claimed in claim 1, wherein said pair of all burst-mode sub-state machines M of stages 2 through K-1 N The readjustment method comprises the following steps:
(1) Deleting directed edges<d N ，v c >And its corresponding burst input transition trans i (e N ) And burst output transition o (e N )；d N Is M N In decision nodes other than the start state node, v c For removing auxiliary state node v N Sum of outer and d N Nodes connected by directed edges; directed edge<d N ，v N >Corresponding burst output transition req N -, directed edge e N ＝<d N ，v c >The corresponding burst input transition and burst output transition are trans respectively i (e N ) And trans o (e N )；
(2) Adding extra state nodes v and setting directed edges<d N ，v>The corresponding burst input transition and burst output transition are pseu + and req, respectively N -; set directed edges<v，v c >The corresponding burst input transition and burst output transition are pseu-, trans (e), respectively N ) And trans o (e N )。
8. A burst-mode asynchronous control circuit design method as claimed in claim 5, characterized in that the interface state machine connecting the first stage sub-state machine and the second stage sub-state machine does not output the auxiliary signal pseu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100360524A CN101149763B (en) | 2007-11-06 | 2007-11-06 | Burst mode asynchronous control circuit design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100360524A CN101149763B (en) | 2007-11-06 | 2007-11-06 | Burst mode asynchronous control circuit design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101149763A true CN101149763A (en) | 2008-03-26 |
| CN101149763B CN101149763B (en) | 2011-02-02 |
Family
ID=39250289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100360524A Expired - Fee Related CN101149763B (en) | 2007-11-06 | 2007-11-06 | Burst mode asynchronous control circuit design method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101149763B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346769A (en) * | 2013-04-12 | 2013-10-09 | 威盛电子股份有限公司 | State machine circuit and state adjusting method |
| CN107301143A (en) * | 2017-05-08 | 2017-10-27 | 浙江大学 | A kind of asynchronous arbiter based on the phase Handshake Protocol of coding and double track four |
| CN113609801A (en) * | 2021-07-12 | 2021-11-05 | 海南师范大学 | Asynchronous sequential control circuit design method and device |
-
2007
- 2007-11-06 CN CN2007100360524A patent/CN101149763B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346769A (en) * | 2013-04-12 | 2013-10-09 | 威盛电子股份有限公司 | State machine circuit and state adjusting method |
| CN103346769B (en) * | 2013-04-12 | 2016-03-16 | 威盛电子股份有限公司 | State machine circuit and state adjusting method |
| CN107301143A (en) * | 2017-05-08 | 2017-10-27 | 浙江大学 | A kind of asynchronous arbiter based on the phase Handshake Protocol of coding and double track four |
| CN107301143B (en) * | 2017-05-08 | 2020-09-04 | 浙江大学 | Asynchronous arbiter based on double-track coding four-phase handshake protocol |
| CN113609801A (en) * | 2021-07-12 | 2021-11-05 | 海南师范大学 | Asynchronous sequential control circuit design method and device |
| CN113609801B (en) * | 2021-07-12 | 2023-11-10 | 海南师范大学 | Asynchronous time sequence control circuit design method and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101149763B (en) | 2011-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3258000B2 (en) | Electronic circuit | |
| Jalabert et al. | xpipesCompiler: A tool for instantiating application-specific Networks on Chip | |
| Huang et al. | High-performance and power-efficient CMOS comparators | |
| Mokhov et al. | Conditional partial order graphs: Model, synthesis, and application | |
| Sarkar et al. | Network-on-chip hardware accelerators for biological sequence alignment | |
| Chen et al. | Computer generation of high throughput and memory efficient sorting designs on FPGA | |
| CN101149763A (en) | Burst mode asynchronous control circuit design method | |
| Branover et al. | Asynchronous design by conversion: Converting synchronous circuits into asynchronous ones | |
| CN101770362B (en) | Distributed dynamic process generating unit meeting System C processor | |
| CN110110863A (en) | A kind of distributed machines study tune ginseng system based on celery | |
| Huang et al. | ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping | |
| Gilabert et al. | Exploring high-dimensional topologies for NoC design through an integrated analysis and synthesis framework | |
| CN112906328A (en) | FPGA prototype verification system generation method and system and FPGA prototype verification method and system | |
| Xu et al. | Automatic synthesis of computation interference constraints for relative timing verification | |
| Case et al. | Inductively finding a reachable state space over-approximation | |
| Xia et al. | Data communication in systems with heterogeneous timing | |
| CN102201817A (en) | Low-power-consumption LDPC decoder based on optimization of memory folding architecture | |
| Yakovlev et al. | Design and analysis of a self-timed duplex communication system | |
| Xu et al. | Towards energy-efficient asynchronous circuit design with flip-flop-to-latch replacement | |
| Perumalla et al. | Using reverse circuit execution for efficient parallel simulation of logic circuits | |
| Ding et al. | Configuring algorithm for reconfigurable Network-on-Chip architecture | |
| Liu et al. | A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs | |
| Schmidt et al. | Reconfigurable computing cluster project: Phase I brief | |
| Calazans et al. | Asynchronous Circuit Principles and a Survey of Associated Design Tools | |
| Oliveira et al. | Synthesis by direct mapping of asynchronous extended burst-mode controllers using RS latch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110202 Termination date: 20111106 |