CN101141114A

CN101141114A - CMOS self-adaptive biasing circuit

Info

Publication number: CN101141114A
Application number: CNA2007101759137A
Authority: CN
Inventors: 杜春山; 刘章发
Original assignee: Beijing Jiaotong University
Current assignee: Beijing Jiaotong University
Priority date: 2007-10-16
Filing date: 2007-10-16
Publication date: 2008-03-12
Anticipated expiration: 2027-10-16
Also published as: CN100488034C

Abstract

The invention discloses a CMOS self-adapted biasing circuit in the multi level radio frequency integrated power amplifier. The first capacitance in the circuit couples in the detected front level output DC power signals, the second resistance and the second capacitance form a low pass filter 1. The first half detects the power; with the increasing of the detected signals, the positive proportion of the signals coupled in increases gradually at the knot N, after rectification and filtering, the MP grid electrical potential of the PMOS pipe increases and the source electrode electric potential increases correspondingly. The third resistance and capacitance and the NMOS pipe MN form a low pass filter 2 to further reduce the AC proportion of the low MP source electrode so as to make stable the DC proportion. The NMOS pipe MN distributes voltage to dereference the resistance and the capacitance of the low pass filter 2 within rational range so as to reduce size. The PMOS pipe MP source electrode and the biasing point are separated by the fourth resistance to reduce the influence of the biasing circuit to the following grade.

Description

The CMOS adaptive bias circuit

Technical field

The present invention relates to the biasing circuit in a kind of CMOS of being applied in radio frequency integrated power amplifier design.

Background technology

Current, a lot of wireless communication systems have all adopted the modulation technique of amplitude/phase combination, and power amplifier will prevent distortion when output is high-power, and this linearity to power amplifier has proposed very high requirement.Adopt the research of adaptive-biased raising power amplifier linearity output power range to be of long duration.The design of a lot of adaptive bias circuits all is based on Bipolar (ambipolar) technology, and adaptive bias circuit is actually rare under the CMOS technology.In the related adaptive bias circuit, the grid of field effect transistor provides biasing by resistance pressure-dividing network in the document [1], and this paths can be introduced extra power consumption undoubtedly.In addition, link to each other by a resistance between the drain electrode of field effect transistor and the power supply, the fluctuation of grid voltage is easy to cause the fluctuation of drain voltage like this, and then causes the fluctuation of bias voltage; Document [2] has related to another adaptive bias circuit, wherein, the grid that plays the NMOS field effect transistor of rectified action also is to provide biasing by resistance pressure-dividing network, also can produce extra power consumption, compare with [1], the source electrode of PMOS field effect transistor links to each other with power supply by a low pass filter, but, in practical design, the value of resistance and electric capacity can be very big, can occupy bigger chip area like this.

[1]Yi-Jan?Emery?Chen，Chih-Yun，et?al.“A?high-efficient?CMOS?RF?poweramplifier?with?automatic?adaptive?bias?control”，IEEE?microwave?and?wirelesscomponents?letters，VOL.16，NO.11，November?2006.

[2]YunSeong?Eo，KwangDu?lee.“High?efficiency?5GHz?power?amplifier?withadaptive?bias?control”，IEEE?radio?frequency?integrated?circuits?symposium，2004

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of convenient and practical adaptive bias circuit for multistage CMOS radio frequency integrated power amplifier: overcome unnecessary power loss in the prior art, effectively reduce device size, further dwindle circuit area.

Technical scheme of the present invention:

A kind of CMOS adaptive bias circuit constitutes the connected mode between the device of this circuit:

One end of first electric capacity links to each other with power detection point, and its other end links to each other with an end of first resistance and the negative electrode of diode through node;

The other end of first resistance links to each other with an end of second resistance, an end of second electric capacity and the grid of PMOS pipe MP;

The other end of the other end of the anode of diode, second resistance, second electric capacity, PMOS pipe MP grounded drain;

The source electrode of PMOS pipe MP links to each other with an end of the 3rd resistance and an end of the 4th resistance with substrate;

The other end of the 4th resistance links to each other with bias point;

NMOS pipe MN source electrode links to each other with the 3rd the other end, substrate ground connection, and grid and drain electrode are connected to power supply Vdd;

One end of the 3rd electric capacity links to each other with power supply Vdd, and the other end links to each other with the source electrode of PMOS pipe MP.

Beneficial effect of the present invention: the present invention improves on documents [1] and [2] basis, has simple in structure, saving chip area, can reach circuit function, can reduce chip cost again, be a kind of CMOS adaptive bias circuit of realizing under the CMOS technology.

Description of drawings

The typical application circuit that Fig. 1 is adaptive-biased

Fig. 2 CMOS adaptive bias circuit

Embodiment

In conjunction with the accompanying drawings the present invention is done step explanation:

Circuit of the present invention can be applicable in the circuit such as multi-stage power amplifier, the typical application circuit adaptive-biased as Fig. 1.Thereby the biasing of one-level after the power output dynamic adjustments of this adaptive bias circuit detection previous stage.

Fig. 2 is CMOS adaptive bias circuit figure of the present invention.

In the circuit of Fig. 2, first capacitor C 1 is coupled into detected previous stage output AC power signal, and diode D1 plays rectified action, and second resistance R 2 and second capacitor C 2 have constituted low pass filter 1 (LPF1).This first half plays a part power detection: along with the increase of detection signal Vdetect intensity, the signal that coupling is come in increases gradually at the positive composition in node N place, and after rectification and filtering, PMOS pipe MP grid potential increases thereupon, like this, its source potential also can increase accordingly.The 3rd resistance R 3, the 3rd capacitor C 3 and NMOS pipe MN have constituted a low pass filter 2 (LPF2), can further reduce the alternating component of PMOS pipe MP source electrode, make its direct current ingredient stability.NMOS pipe MN plays a part dividing potential drop, can effectively reduce the resistance of the 3rd resistance R 3, and the resistance of low pass filter LPF2 and electric capacity is value in the reasonable scope, and then reaches the effect of dwindling area.PMOS pipe MP source electrode and bias point VBias keep apart by the 4th resistance R 4, will reduce the influence of this biasing circuit to the back one-level like this.

Connected mode between the device of formation CMOS adaptive bias circuit:

One end of first capacitor C 1 links to each other with power detection point Vdetect, and its other end links to each other with the negative electrode of first resistance R, 1 one ends and diode D1 through node N;

The other end of first resistance R 1 links to each other with an end of second resistance R 2, an end of second capacitor C 2 and the grid of PMOS pipe MP;

The other end of the other end of the anode of diode D1, second resistance R 2, second capacitor C 2, PMOS pipe MP grounded drain;

The source electrode of PMOS pipe MP links to each other with an end of the 3rd resistance R 3 and an end of the 4th resistance R 4 with substrate;

The other end of the 4th resistance R 4 links to each other with bias point Vbias;

The MN source electrode of NMOS pipe links to each other with the other end of the 3rd R3, substrate ground connection, and grid and drain electrode are connected to power supply Vdd;

One end of the 3rd capacitor C 3 links to each other with power supply Vdd, and the other end links to each other with the source electrode of PMOS pipe MP.

Claims

1. CMOS adaptive bias circuit is characterized in that: constitute the connected mode between the device of this circuit:

One end of first capacitor C 1 links to each other with power detection point, and its other end links to each other with an end of first resistance R 1 and the negative electrode of diode D1 through node N;

The other end of the 4th resistance R 4 links to each other with bias point;

NMOS pipe MN source electrode links to each other with the other end of the 3rd resistance R 3, substrate ground connection, and grid and drain electrode are connected to power supply Vdd;