CN101136367A - Manufacturing method of photoelectric conversion device - Google Patents
Manufacturing method of photoelectric conversion device Download PDFInfo
- Publication number
- CN101136367A CN101136367A CNA200710148317XA CN200710148317A CN101136367A CN 101136367 A CN101136367 A CN 101136367A CN A200710148317X A CNA200710148317X A CN A200710148317XA CN 200710148317 A CN200710148317 A CN 200710148317A CN 101136367 A CN101136367 A CN 101136367A
- Authority
- CN
- China
- Prior art keywords
- electric conductor
- mos transistor
- hole
- electric
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
A noise generated by a constitution of widening an incident aperture of light of a photoelectric conversion element is reduced. In a manufacturing method of a photoelectric conversion device, first electroconductor arranged in a first hole arranged in the first interlayer insulation layer electrically connects a first semiconductor region to a gate electrode of an amplifying MOS transistor not through wirings included in a wiring layer. Moreover, a second electroconductor electrically connects a second semiconductor region different from the first semiconductor region to a wiring. In a constitution of that second electroconductor, a third electroconductor arranged in a second hole arranged in the first interlayer insulation layer and a fourth electroconductor arranged in a third hole arranged in the second interlayer insulation layer are stacked and electrically connected to each other. And the step of forming the first electroconductor, and the step of forming the third electroconductor are performed simultaneously.
Description
Technical field
The present invention relates to the manufacture method of photoelectric conversion device.
Background technology
Recent years, provide the cheap digital camera of high image quality and video camera to popularize.The photoelectric conversion device that uses in digital camera and video camera comprises CCD type and MOS type photoelectric conversion device.MOS type photoelectric conversion device comprises photoelectric conversion region and peripheral circuit region, described photoelectric conversion region comprises MOS transistor and photodiode, and described peripheral circuit region comprises the signal of exporting described photoelectric conversion region and the MOS transistor of the MOS transistor of drive arrangement in photoelectric conversion region.Those photoelectric conversion regions and peripheral circuit region can be made by the general procedure of CMOS manufacturing process.
TOHKEMY has been described for H09-055440 number and has been made the contact structures of using under the occasion of SRAM by the CMOS manufacturing process.Specifically, in structure, semiconductor region is electrically connected with gate electrode by the electric conductor that is embedded in the hole that is arranged in the interlayer insulating film, and a plurality of conductor layers in the hole of stacked arrangement in interlayer insulating film.In addition, TOHKEMY discloses for 2002-368203 number in the source follower circuit that exists in the peripheral circuit region of CCD type photoelectric conversion device, is electrically connected the structure of semiconductor region and gate electrode by being embedded in electric conductor in the hole that is arranged in the interlayer insulating film.
Because a pixel comprises photo-electric conversion element and a plurality of MOS transistor, the wiring layer that the MOS photoelectric conversion device need be more more than CCD photoelectric conversion device.Limit the incident light hole footpath of photo-electric conversion element herein, by wiring layer.Therefore, in order to increase light incident efficient, needs are used to be widened to the incident light hole distributing directly of photo-electric conversion element to improve sensitivity.
In order to widen the aperture, in the photoelectric conversion region of the photo-electric conversion element of arranging the MOS photoelectric conversion device, the inventor has been found that employing is electrically connected the structure of semiconductor region and gate electrode by being embedded in electric conductor in the hole that is arranged in the interlayer insulating film.And, have in manufacturing under some occasions of photoelectric conversion device of this structure, find that noise increases sometimes.
Therefore, an object of the present invention is, suppressing the above-mentioned noise of finding recently increases problem, and a kind of manufacture method of MOS photoelectric conversion device is provided, and described MOS photoelectric conversion device has improved to the efficient of the light incident of photo-electric conversion element.
Summary of the invention
The manufacture method of photoelectric conversion device of the present invention is the manufacture method that comprises as the photoelectric conversion device of lower part: be arranged in a plurality of photo-electric conversion elements on the Semiconductor substrate; Be used for the electric charge of photo-electric conversion element is transferred to the transfer MOS transistor of first semiconductor region; And being used for coming the amplifying mos transistor of read output signal based on the electric charge that shifts, described method comprises the steps: to form photo-electric conversion element, first semiconductor region, shifts MOS transistor and amplifying mos transistor on Semiconductor substrate; First interlayer insulating film that form and cover described photo-electric conversion element, shifts MOS transistor and amplifying mos transistor; In described first interlayer insulating film, form single hole comprises the part of the part of gate electrode of amplifying mos transistor and first semiconductor region with exposure zone; In described first interlayer insulating film, form the hole comprises the part of the part of electrode of amplifying mos transistor and first semiconductor region with exposure zone; Embedding first electric conductor in described single hole; Embedding second electric conductor in corresponding to the hole of the area arrangements of at least a portion electrode district that comprises amplifying mos transistor; And second interlayer insulating film that forms described first and second electric conductors of covering; Zone corresponding at least a portion that comprises second electric conductor in described second interlayer insulating film forms the hole; Embedding the 3rd electric conductor in corresponding to the hole of the area arrangements of at least a portion that comprises second electric conductor; And form the wiring that is electrically connected with described the 3rd electric conductor on described the 3rd electric conductor, wherein the step of the step of embedding first electric conductor and embedding second electric conductor is carried out simultaneously.
In addition, the manufacture method of photoelectric conversion device of the present invention is the manufacture method that comprises as the photoelectric conversion device of lower part: be arranged in photo-electric conversion element and a plurality of MOS transistor on the Semiconductor substrate, described MOS transistor comprises the transfer MOS transistor and the amplifying mos transistor that is used for coming based on the electric charge that shifts read output signal that is used for the electric charge of photo-electric conversion element is transferred to first semiconductor region; And be arranged in the wiring layer that comprises a plurality of wirings on the Semiconductor substrate, a plurality of interlayer insulating films, described interlayer insulating film comprises arranges first interlayer insulating film and second interlayer insulating film that is layered on described first interlayer insulating film that is used to cover described photo-electric conversion element and a plurality of MOS transistor, wherein said photoelectric conversion device also comprises first and second electric conductors, first electric conductor is embedded in first hole that is arranged in described first interlayer insulating film, being used for not being electrically connected described first semiconductor region by the wiring that is included in wiring layer is electrically connected second semiconductor region that is different from described first semiconductor region and is included in the wiring of first in the wiring layer with second electric conductor of the gate electrode of amplifying mos transistor, and comprise the 3rd electric conductor and the 4th electric conductor that pile up each other and be electrically connected, described the 3rd electric conductor is embedded in second hole that is arranged in described first interlayer insulating film, described the 4th electric conductor is embedded in the 3rd hole that is arranged in described second interlayer insulating film, and the step of the step of wherein said embedding first electric conductor and embedding second electric conductor is same step.
Other features and advantages of the present invention will be from below in conjunction with manifesting the description of the drawings, and wherein similarly Reference numeral is represented same or analogous parts in whole accompanying drawing.
Description of drawings
Fig. 1 is the generalized section of the photoelectric conversion device of first embodiment.
Fig. 2 A, 2B, 2C and 2D are the schematic diagrames of setting forth the photoelectric conversion device manufacturing step.
Fig. 3 is the generalized section of the photoelectric conversion device of second embodiment.
Fig. 4 is the generalized section that is used for the photoelectric conversion device of comparison.
Fig. 5 A is the plane figure of photoelectric conversion device, and Fig. 5 B is the plane figure that is used for the photoelectric conversion device of comparison.
Fig. 6 is the practical circuit of photoelectric conversion device.
Fig. 7 is the block diagram of an example of image picking system.
Fig. 8 A and 8B are the plane figures of MOS transistor.
Fig. 9 is the plane figure of first electric conductor.
Figure 10 is the figure of relevant contact resistance.
Figure 11 is the generalized section of the photoelectric conversion device of the 4th embodiment.
In conjunction with and the accompanying drawing that constitutes a specification part set forth embodiments of the invention with specification, be used to explain principle of the present invention.
Embodiment
Photoelectric conversion device of the present invention comprises a plurality of photo-electric conversion elements of being arranged on the Semiconductor substrate, is arranged in a plurality of MOS transistor and wiring on the described Semiconductor substrate.Those MOS transistor comprise the amplifying mos transistor of the electric charge of photo-electric conversion element being transferred to the transfer MOS transistor of first semiconductor region and coming read output signal based on the electric charge that shifts at least.Described photoelectric conversion device comprises and is arranged on the Semiconductor substrate first interlayer insulating film that covers described photo-electric conversion element and a plurality of MOS transistor, and is stacked on second interlayer insulating film on described first interlayer insulating film.In this photoelectric conversion device, use first electric conductor that is embedded in first hole that is arranged in described first interlayer insulating film to be electrically connected the gate electrode of first semiconductor region and amplifying mos transistor and not pass through and connect up.In addition, second semiconductor region that is different from first semiconductor region is electrically connected with connecting up by described second electric conductor.Constitute second electric conductor by piling up and being electrically connected the 3rd electric conductor that is embedded in second hole that is arranged in described first interlayer insulating film with the 4th electric conductor that is embedded in the 3rd hole that is arranged in described second interlayer insulating film herein.And by the step identical with the step that is used for first electric conductor at each hole embedding the 3rd electric conductor.
Therefore this structure can connect up and be electrically connected between first semiconductor region and gate electrode, and reduce the quantity of required wiring and improved the degree of freedom of designing wiring, and can improve the aperture ratio of photo-electric conversion element.In addition, form first electric conductor and the 3rd electric conductor by same steps as.Therefore, metal impurities reduce to the diffusion of semiconductor region, thereby can simplify manufacturing step.Therefore, when reducing the noise increase, can widen the aperture of photoelectric conversion device, thereby the photoelectric conversion device of the signal to noise ratio with improvement can be provided.
In addition, described first electric conductor and the 3rd electric conductor have equal height, make the complanation that is arranged in the interlayer insulating film on described first electric conductor and the 3rd electric conductor will become easy.In addition, can make the interlayer insulating film attenuation.Therefore, can shorten to the travel path of incident light of photo-electric conversion element.And can increase the light that enters photo-electric conversion element more.
Then, the noise that explanation is produced owing to above-mentioned metal impurities.Generally, in photoelectric conversion device, metal impurities spread in active region (semiconductor region), have increased dark current and produce noise, and increased the deviation of each picture element signal.Particularly under the situation that metal impurities spread in the photo-electric conversion element periphery, the attribute of photo-electric conversion element will significantly reduce.Because the noise that metal impurities cause is with appreciable impact picture quality.Therefore, particularly will in photoelectric conversion device, cause problem.
, in the step that forms above-mentioned first electric conductor, consider following situation herein: on first interlayer insulating film, form first electric conductor, in described first interlayer insulating film, be formed for the hole of the electrical connections in another zone then.In the case, in the step that forms the hole, after forming first electric conductor, Semiconductor substrate is exposed in the metal atmosphere, thereby metal spreads in substrate sometimes.In view of the typical problem of this photoelectric conversion device, obtain the present invention.
Next, the electric conductor that explanation is made each zone be electrically connected.According to the object that will be electrically connected, there are two class electric conductors to be arranged in the hole in the interlayer insulating film.One class be electrically connected the active region with such as the electric conductor of wiring or electric connection grid electrode and contact plug such as the electric conductor of wiring.Another kind of is to be electrically connected contact plug and wiring or self the through hole plug of connecting up.Herein, the structure that zones of different and parts only are not electrically connected by wiring by plug will be known as shared contact structures hereinafter.In addition, under the situation that zones of different and parts are electrically connected, will be called the contact structures (stacked via) of piling up to form to be electrically connected piling up a plurality of plugs.Therefore, the structure that comprises above-mentioned first electric conductor can be called shared contact structures.The structure that comprises second electric conductor can be called and pile up (stacked via) contact.In addition, can between hole and electric conductor, arrange barrier film.Provide barrier film to attempt to suppress alloy reaction between interlayer insulating film, substrate etc. and the electric conductor, perhaps suppress the diffusion of electric conductor to interlayer insulating film, substrate etc.In similar trial, can also provide barrier film to the upper and lower of wiring.
Next, will the aperture of photoelectric conversion device be described.The aperture refers to allow light to enter the zone of photo-electric conversion element and is limited by wiring pattern and photomask usually.The pattern of predetermined hole diameter is used to determine enter the periphery of the light of photo-electric conversion element, and the optical analog of photoelectric conversion device section etc. will bring the knowledge of being determined the aperture by pattern.
Hereinafter, will be called " substrate " and comprise material substrate treated situation as described below as the Semiconductor substrate of material substrate.For example, the parts under the state that forms one or more semiconductor regions, perhaps the parts of parts in the middle of a series of manufacturing steps or a series of manufacturing steps of process also can be known as substrate.The active region refers to the semiconductor region that distinguished by the element separation that forms by LOCOS etc., perhaps forms the zone of the part of each element or composed component.For example, comprise drain region and source region in the transistor.The following with reference to the accompanying drawings embodiments of the invention that explain.
(circuit structure of photoelectric conversion device)
At first, explanation can be used the circuit of MOS photoelectric conversion device of the present invention.Fig. 6 has enumerated the circuit of MOS photoelectric conversion device.Shift the electric charge that MOS transistor 102a and 102b shift photo-electric conversion element.In the present embodiment, the electronics in the electric charge that produces in photo-electric conversion element is counted as signal charge.In addition, shifting MOS transistor is the N type.The drain region that reset mos transistor 103 resets photo- electric conversion element 101a and 101b and shifts MOS transistor.In addition, amplifying mos transistor 104 comes amplifying signal and exports these signals to holding wire 106 based on the electric charge that produces in photo-electric conversion element.A part and its drain region that amplifying mos transistor is suitable as source follower circuit are powered voltage.Select MOS transistor 105 controls reading to holding wire.Transfering transistor, reset transistor, amplifying mos transistor and selection MOS transistor will be collectively referred to as reads MOS transistor.In Fig. 6, the reset mos transistor of reading in the MOS transistor to be comprised 103, amplifying mos transistor 104 and select MOS transistor 105 to share by two photo-electric conversion element 101a and 101b.Photo-electric conversion element is arranged in the photoelectric conversion region 124.
In addition, on each holding wire 106, provide clamp circuit 108, cascade amplifier part 120 and the signal retaining part 121 that is suitable for comprising clamping ability.Signal retaining part 121 is suitable for comprising capacitor 112a and 112b, switch etc.Comprise scanning circuit 123 and 129.Read out in the signal that produces photo-electric conversion element 101a and the 101b by the transistor of reading that drives by scanning circuit 123 from output line 106, and output to horizontal output line 116a and 116b by clamp circuit 108 and signal retaining part 121.Export the signal of horizontal output line 116a and 116b at last from differential amplifier 118.In clamp circuit 108 and differential amplifier 118, from signal, remove noise component(s) to become picture signal.In Fig. 6, the part such as scanning circuit and clamp circuit except that photoelectric conversion region 124 is made peripheral circuit region by general designation.
To structure of the present invention be described with embodiment below.But the present invention will be not limited to those embodiment, but can suitably revise in being no more than the scope of main points of the present invention.
(first embodiment)
In the present embodiment, will share contact structures and be used for first electric conductor, this first electric conductor is electrically connected the gate electrode of semiconductor region (first semiconductor region) and amplifying mos transistor, wherein shifts the electric charge that produces in photo-electric conversion element in semiconductor region.In addition, contact structures be will pile up and other MOS transistor and wiring will be used to be electrically connected.
To specify Fig. 1 below.Fig. 1 is the generalized section of pixel of the photoelectric conversion device of first embodiment.Fig. 1 is corresponding to the part that comprises photo-electric conversion element 101 and transfer MOS transistor 102 among Fig. 6.In Fig. 1, on a primary flat of substrate, provide the semiconductor region 1 of the first electric conductor type.This semiconductor region 1 can be one of substrate of the trap and the first electric conductor type.Photo-electric conversion element comprises the semiconductor region 2 of the second electric conductor type.The semiconductor region 3 of the first electric conductor type covers semiconductor region 2.The gate electrode 4 that shifts MOS transistor shifts the electric charge of photo-electric conversion element.The electric charge of photo-electric conversion element is transferred to the semiconductor region 5 (below be known as floating diffusion region, i.e. FD district) of the second electric conductor type.Element isolation zone 6 is STI (shallow trench isolation from) structure in the present embodiment.Source follower circuit comprises the gate electrode 7 of amplifying mos transistor.Active region in the pixel (semiconductor region) 8 is connected with wiring.With the active region that is connected of wiring is the electrode district that for example is selected from the group that comprises above-mentioned source region of reading MOS transistor, drain region etc.There is the trap contact that is used for to trap supply voltage in addition.In addition, gate electrode comprises and the wiring that interconnects FD district and the integrated situation of wiring of supplying voltage to gate electrode.
First electric conductor 9 is electrically connected the gate electrode 7 of FD district 5 and amplifying mos transistor.First electric conductor is arranged in the single contact hole (first hole) in first interlayer insulating film 17.First electric conductor is electrically connected gate electrode 7 and FD district 5 and does not pass through wiring.
Second electric conductor 11 and 13 is electrically connected active region 8 and wiring 15.Second electric conductor comprises the 3rd electric conductor and the 4th electric conductor that piles up and be electrically connected.The 3rd electric conductor 11 is arranged in second hole in described first interlayer insulating film 17.The 4th electric conductor 13 is arranged in the 3rd hole in described second interlayer insulating film 18.Between electric conductor and interlayer insulating film, arrange barrier film 10,12 and 14.In addition, arrange barrier film 16 in the upper and lower of wiring 15.Insulation such as interlayer insulating film 17,18 makes wiring with 19, contact.
On element isolation zone 6, arrange the gate electrode 7 that is electrically connected with first electric conductor.This element isolation zone 6 is sti structure preferably.For example, be under the situation of LOCOS structure at element isolation zone, thereby the beak of the etching damage LOCOS structure under the situation that forms the hole of arranging first electric conductor part has increased leakage current.In addition, the LOCOS structure is higher than sti structure on the height of distance substrate, and therefore the technology controlling and process when forming the hole is difficult.Therefore, element isolation zone can be a sti structure.Herein, the gate electrode 7 that is arranged on the element isolation zone 6 can be as wiring.
Herein, for relatively, Fig. 4 will describe the grid of amplifying mos transistor wherein and the FD district structure by two electric conductors and wiring electrical connection.Electric conductor 26, electric conductor 27 are provided and have connected up 28.That is, different with structure among Fig. 1, in the layer (highly) identical, will need additional wiring 28 with wiring 15.By this wiring 28, the aperture of photo-electric conversion element is narrowed down thereby wiring layer has reduced the degree of freedom of layout.But, in Fig. 1, under the situation in electric connection grid electrode 7 and FD district 5, do not need wiring.Therefore, wiring layer has increased the degree of freedom of layout.Therefore, can widen the aperture of photo-electric conversion element.In addition, can be on second interlayer insulating film arrange wiring in the desired zone in the part of the first electric conductor area just above.Thereby it is easy that the shielding in FD district 5 will become.
In addition, will the improvement of aperture ratio be described.Fig. 5 A has shown the plane figure of the photoelectric conversion device with first electric conductor (sharing contact structures) that is electrically connected with the gate electrode of amplifying mos transistor.Therefore the Reference numeral of Fig. 5 A will omit its explanation corresponding to Fig. 6.The FD district is electrically connected with the gate electrode of amplifying mos transistor 104 by first electric conductor 9.Output line 106 and power line 107 are arranged.Herein, active region 130 is electrically connected with power supply.
For relatively, Fig. 5 B has shown the plane figure of the photoelectric conversion device of first electric conductor that is electrically connected without any for example the same gate electrode that is used to make amplifying mos transistor with structure among Fig. 4.Fig. 6 equally aspect Reference numeral corresponding to Fig. 5 A.Fig. 5 B has shown the wiring 133 that is used to make output line 106, power line 107, FD district and gate electrode electrical connection, and each pixel is than the wiring that has greater number among Fig. 5 A.Therefore, by adopting the structure of present embodiment, wiring layer has increased the degree of freedom of layout, the feasible aperture that can widen photo-electric conversion element.In addition, above the FD district, arrange wiring.Thereby, can reduce the light that enters the FD district.In wiring is not under the situation of the drive wire that is electrically connected with the gate electrode of MOS transistor but one of output line 106 and power line 107, can further reduce because the noise in the FD district that the potential change that connects up causes.
Next, will illustrate except the grid of amplifying mos transistor and the electric connection structure in the part the FD district.Active region 8 in the pixel possesses second electric conductor that the wiring that is used for making top is electrically connected.
This second electric conductor also can be formed by an electric conductor.Specifically, according to this method, between with first interlayer insulating film and the second layer stacked dielectric layer together after, form the hole penetrating described first interlayer insulating film and second interlayer insulating film, thus embedding electric conductor there.But as mentioned above, when forming this hole, metal impurities may be diffused in the active region 8.Therefore, in the structure of present embodiment, form the 3rd electric conductor 11 and first electric conductor 9 of substrate side by identical step.Then, above described the 3rd electric conductor, pile up the 4th electric conductor 13.Thereby, reduced metal impurities and entered semiconductor region, and can provide and have more low noise photoelectric conversion device.
In addition, the 3rd electric conductor and first electric conductor roughly have equal height.Thereby, can simplify the complanation of second interlayer insulating film that is arranged in those electric conductor tops, thereby can make interlayer insulating film thinner.In addition, can shorten to the travel path of incident light of photo-electric conversion element.
(manufacture method of photoelectric conversion device)
Next, an example of the manufacture method of photoelectric conversion device will be described with Fig. 2 A, 2B, 2C and 2D.Fig. 2 A, 2B, 2C and 2D are corresponding with Fig. 1 aspect Reference numeral.
At first, in the semiconductor region 1 of the first electric conductor type, form element isolation zone 6, the second electric conductor type semiconductor district 3, FD district 5 etc.Next, on Semiconductor substrate, form the gate electrode of for example making 4 and 7, thereby be provided at the state that forms photo-electric conversion element and MOS transistor in the Semiconductor substrate by polysilicon.Then, form first interlayer insulating film 17 made by silicon dioxide film so that the structure of Fig. 2 A to be provided.
As shown in Fig. 2 B, the photoresist that is coated on first interlayer insulating film 17 experiences patterning to form photoresist pattern 20.Use this photoresist pattern 20 as mask, in first interlayer insulating film 17, be formed for the hole 21 and the hole 22 that is used for the 3rd electric conductor of first electric conductor by etching.Obviously as seen, hole 21 is the single holes corresponding to the zone of the part in the part of the gate electrode that comprises amplifying mos transistor and FD district from Fig. 2 B.In addition, as mentioned above, in as the zone of at least a portion of reading one of the source region of transistorized electrode district and drain region, forming hole 22.The shape in hole can be the All Ranges that is used to cover each electrode district.Shape also can be only corresponding to the one subregion.Reading transistor for example is amplifying mos transistor.
After removing photoresist pattern 20, be formed for forming the film of barrier film 10 and 11.In addition, be formed for forming the metal film (tungsten film) of first electric conductor 9 and the 3rd electric conductor 11.For example, use WF
6Gas forms tungsten film by the CVD method.At electric conductor is under the situation of tungsten, and barrier film for example comprises Ti and TiN.Barrier film can be one of individual layer and lamination.By eat-backing barrier film and metal film simultaneously, form first electric conductor 9 and the 3rd electric conductor 11 that comprise barrier film 10 and 11.For this step, except eat-backing, can adopt CMP (chemico-mechanical polishing) method.This step can make first electric conductor and the 3rd electric conductor have equal height.Then, cover first electric conductor 9, the 3rd electric conductor 11 and first interlayer insulating film, form second interlayer insulating film 18, provide the structure of Fig. 2 C.
Next, form the photoresist pattern once more on second interlayer insulating film 18, feasible pattern with photoresist is formed for the hole of the 4th electric conductor as mask.This hole forms in the zone corresponding at least a portion of second electric conductor.By with Fig. 2 C in identical step, form the 4th electric conductor 13 and barrier film 14 (Fig. 2 D).
Then, form wiring.At first, the order experience film according to barrier film, the metal film that is used to connect up and barrier film forms and patterning.Thereby form wiring 15 and barrier film 16 thereof.The 4th electric conductor 13 is electrically connected with wiring 15.Form the 3rd interlayer insulating film 19 to provide the structure of Fig. 1.Adopt aluminium to be used for the metal film of wiring layer, but also can adopt copper.
The shape of first electric conductor and second electric conductor will be described herein, with Fig. 8 A and 8B.Fig. 8 A be used to describe the electric conductor bottom surface shape schematic plan view and comprise gate electrode 30 and active region 31.The shape 29 of hole arranged bottom surface in active region 31 and gate electrode 30.In Fig. 8 A and 8B, contact approximately is a rectangle, has the line of length X 1 with vertical and have another line of length Y1 with it.The situation that has elliptical shape in addition.Length X 1 equals length Y1.Fig. 8 B is the schematic plan view of the bottom surface 32 in the hole in the structure (sharing contact structures) that has shown first electric conductor that comprises Fig. 1.Fig. 8 B aspect Reference numeral corresponding to Fig. 8 A.The bottom surface 32 in hole also roughly is a rectangle.In addition, can adopt ellipse.Line with length Y2 is crossed over gate electrode 30 and active region 31.Another line has length X 2.Length Y2 is longer than length X 2.Herein, length X 2 can be longer than length X 1.By specific length like this, can suppress the reduction of conductivity and can reduce the connection defective.
In the present embodiment, form first electric conductor 9 and the 3rd electric conductor in the aperture be arranged in first interlayer insulating film 17 simultaneously.Thereby, can reduce the diffusion of metal impurities to substrate.Thereby, can provide to have more low noise high-quality light electrical switching device.In addition, in the present embodiment, second electric conductor is electrically connected active region 8 and wiring layer.But the structure of described second electric conductor also is applicable to the gate electrode of the MOS transistor that is different from amplifying mos transistor and the electrical connection between the wiring layer.
(second embodiment)
In Fig. 3, set forth the structure of present embodiment.Fig. 3 on Reference numeral corresponding to Fig. 1.Present embodiment is characterised in that the structure that is included in the barrier film in second electric conductor.Between the 3rd electric conductor 11 and active region 8, provide barrier film 24-1 and 24-2.Between the 4th electric conductor 13 and the 3rd electric conductor, provide barrier film 25.Can be by before the step of arranging first electric conductor and the 3rd electric conductor, being provided in the hole, forming the step of double-deck barrier film, and before the step of arranging the 4th electric conductor, increase the step that is used for forming the individual layer barrier film, form described structure in the hole.For example, using under the situation of tungsten as electric conductor, the barrier film of first electric conductor 9 and the 3rd electric conductor 11 is double-deckers of Ti film and TiN film, and the barrier film of the 4th electric conductor 13 is individual layer TiN films.This structure can be improved the output capacity of the photoelectric conversion device of the structure that comprises that second electric conductor is such.
In the such structure of second electric conductor, the barrier film of the 3rd electric conductor 11 in the lower floor is double-deckers, the Ti film 24-1 and the anti-WF of Si bonding
6TiN film 24-2.This structure can be improved the reliability of barrier film and reduce the diffusion of tungsten.But the 4th electric conductor 13 in the upper strata only comprises anti-WF
6TiN.In the case, compare, can arrange thick TiN film, and therefore can improve the coating rate, thereby reduce the misgrowth of tungsten and the corrosion of barrier film with the double-deck situation of Ti film and TiN film.
The misgrowth of tungsten and the corrosion of barrier film will further be illustrated in greater detail herein.Be formed in second interlayer insulating film 18 under the situation of contact hole of the 4th electric conductor 13 in the upper strata, the center of the 3rd electric conductor 11 is left at the center in hole sometimes.In this case, in a part of barrier film, be easy to take place not enough coating.Therefore, when the stacked structure of Ti film and TiN film also is used for the barrier film on upper strata, the coating of TiN film will become not enough and to WF
6Patience will become not enough.And, WF may take place
6Corrosion Ti barrier film and the excrescent situation of tungsten.Therefore, the barrier film in the upper strata can be to WF
6The single layer structure of TiN film of patience excellence.This structure can make TiN thicker than the situation that multilayer is provided, and can reduce the corrosion and the excrescent generation of tungsten of barrier film.Therefore, can improve the output capacity of the photoelectric conversion device of the contact that comprises stacked structure.Herein, reactivity is lower than WF
6Material be selected from the group that comprises TaN, WSi, WN etc.
(the 3rd embodiment)
Present embodiment is defined in the length in the zone that the part of gate electrode area just above of the amplifying mos transistor of first electric conductor (share with contact structures) arranges and the length ratio in the zone of arranging in the part of the active region of described first electric conductor area just above.The regulation of this length will be described with Fig. 9 and Figure 10.
Fig. 9 has set forth the bottom surface that forms first electric conductor that is exaggerated in the part of first electric conductor 9 among Fig. 5 A.Fig. 9 is corresponding with Fig. 1 aspect Reference numeral.Fig. 9 has shown wiring 301 and 303.These wirings are corresponding to holding wire 106 and power line 107.First electric conductor 9 comprises the first area of the part of the gate electrode area just above that is arranged in amplifying mos transistor, and the second area that is arranged in the part of FD district 5 area just above.In Fig. 9, be parallel to and those first and second zones between the length in first and second zones of direction of boundary-intersected be respectively Z1 and Z2.Length Z1 and Z2 be in the flat shape of first electric conductor vertically on length.
Herein, from the top, first electric conductor is rectangular shape basically, and gate electrode 7 and FD district 5 between the direction of boundary-intersected on have longer line.The more short-term of first electric conductor basically with gate electrode 7 and FD district 5 between the border parallel.By this relation, in the position of the arrangement strictness in design rule center line and space, also can be that gate electrode 7 and FD district 5 guarantee enough contacts area.Herein, first electric conductor can be shapes such as ellipse from the top.
Figure 10 is the figure that has shown the relation between the length ratio in first and second zones of first electric conductor shown in contact resistance and Fig. 9.Ratio Z2/Z1 is the length ratio in first and second zones of described first electric conductor, promptly in other words, is the percentage of the area of the area of second area and first area.Ratio Z2/Z1 among Figure 10 has shown the variation of length Z2 when Z1 is steady state value.Specifically, set forth at length Z1 and be fixed on 0.28 and change the variation of contact resistance under the situation of value of length Z2.As shown in Figure 10, along with ratio Z2/Z1 is 0.6 or bigger, contact resistance linear reduction significantly along with the increase of ratio Z2/Z1.That is, when the contact area of first electric conductor and gate electrode 7 became contact area greater than first electric conductor and FD district 5, contact resistance is linear to be reduced.
On the other hand, along with ratio Z2/Z1 less than 0.6, contact resistance increases sharply along with the reduction of ratio Z2/Z1 significantly.That is, when the contact area of first electric conductor and gate electrode 7 became contact area less than first electric conductor and FD district 5, contact resistance increased sharply.
Photoelectric conversion device uses the information of the pixel of two-dimensional arrangements to form image.Therefore, need the attribute of each pixel even.But the deviation during manufacturing etc. causes the deviation of the bed-plate dimension of first electric conductor in each pixel sometimes.That is, ratio Z2/Z1 less than 0.6 situation under, very little deviation also can cause the remarkable deviation of contact resistance during manufacturing.Even the uniform light quantity of irradiation on whole pixel, under the situation of the remarkable deviation of contact resistance of first electric conductor, deviation also will take place in the voltage that applies to the gate electrode of amplifying mos transistor.Therefore, the output bias of each pixel taking place, thereby makes the image chap of acquisition sometimes.On the contrary, ratio Z2/Z1 be 0.6 or bigger situation under, even same deviation takes place during fabrication, the deviation of contact resistance also is little, and therefore can reduce the deviation of each pixel output.
In addition, passing ratio Z2/Z1 is less than 1, and the displacement during manufacturing can suppress first electric conductor and be formed on situation outside the gate electrode 7 sometimes.Because the possibility that contacts with the active region of another element increases, do not wish to take place outside the width that first electric conductor is in gate electrode 7.When design, must consider surplus, the therefore microminiaturized difficulty that becomes.Therefore, desired proportion Z2/Z1 is 0.6-1.In addition, when considering to make electric conductor in lithography step with the situation of the size surplus of aiming at surplus and patterning of gate electrode under, desired proportion Z2/Z1 is 0.7 or bigger.Therefore, stablized contact resistance and technology controlling and process and become easy.
As mentioned above, the structure of first electric conductor of setting forth in the present embodiment can be microminiaturized and do not reduce electrical properties.
(the 4th embodiment)
To use Figure 11 that the structure of the photoelectric conversion device of present embodiment is described.Further possesses antireflection film 1101 structure of Figure 11 in Fig. 1.In addition, arranging wiring 1102 above the 3rd electric conductor 11 and on one deck, arranging wiring 1103.Can use antireflection film 1101 when forming the hole as the etching block film, make and can form the hole in the mode of good control.In addition, arrange wiring 1102 and wiring 1103 in the layer above the 3rd electric conductor 11.Thereby, can reduce height.
In addition, gate electrode 7 comprises the sidewall 1104 that comprises antireflection film 1101.In the case, in the bed-plate dimension of first electric conductor, the length in the zone that is connected with described sidewall 1104 can be included among the above-mentioned length Z1.
(being applied to image picking system)
Fig. 7 is used for as the block diagram under the situation of the video camera of an example of image picking system at the photoelectric conversion device that will describe with the foregoing description.Another image picking system is a digital still camera etc.Based on Fig. 7 details is described below.
Experience predetermined process from the vision signal of sampling and holding circuit 704 outputs by treatment circuit 705, described predetermined process is selected from the group that comprises γ-correction, color separation, elimination of hidden etc., treatment circuit 705 output brightness signal Y and carrier chrominance signal C.Make from the carrier chrominance signal C experience white balance of treatment circuit 705 output and colour balance is proofreaied and correct and as color difference signal R-Y and B-Y output by chrominance signal correcting circuit 721.In addition, modulation is from the brightness signal Y of treatment circuit 705 outputs and color difference signal R-Y and the B-Y that exports from chrominance signal correcting circuit 721 in encoder circuit (ENC circuit) 724, and as standard television signal output and supply electronic viewfinder, for example one of the video tape recorder that does not show in the accompanying drawings and monitoring electronic viewfinder (EVF).Regard as signal processing circuit such as described treatment circuit 705 grades.
Subsequently, aperture control circuit 706 is based on controlling aperture drive circuit 707 from the vision signal of sample-and-hold circuit 704 supplies.Aperture control 706 control ig meter 708 automatically makes the level of vision signal become the steady state value of predetermined level with the aperture amount of control diaphragm 702.
Band pass filter (BPF) 713 and 714 extracts from the vision signal of sampling and holding circuit 704 outputs and carries out the required high fdrequency component of focus detection.In gate circuit 715, keep the signal exported from first band pass filter 713 (BPF1) that has the different band limit respectively and second band pass filter 714 (BPF2) by focusing on doorframe.And, detect and keep peak value by peak detection circuit 716, and simultaneously in the input logic control circuit 717.This signal will be known as focus voltage.Focus by this focus voltage.
In addition, focus on the shift position that encoder 718 detects condenser lens 701A.Zoom encoder 719 detects the focusing of zoom lens 701B.Aperture encoder 720 detects the aperture amount of diaphragm 702.The detected value of those encoders is supplied to the logic control circuit 717 that carries out system's control.
When the indication zoom, zoom drive circuit 711 rotation zoom motors 712.When zoom motor 712 rotations, zoom lens 701B moves to carry out zoom.
Use photoelectric conversion device of the present invention, it has increased to the amount of the incident light of photo-electric conversion element, and has lower noise in this image picking system, and the image picking system with good signal-to noise ratio can be provided.
As mentioned above, the present invention also provides higher-quality photoelectric conversion device and higher-quality image picking system.In addition, the material and the manufacture method that are selected from the group of piling up quantity etc. of the conduction type, dot structure, distributing and other second electric conductor that comprise Semiconductor substrate will be not limited to each embodiment, but will suitably be provided with.
Illustrated with reference to the embodiment that enumerates when and to be to be understood that to the invention is not restricted to the disclosed embodiment of enumerating when of the present invention.Therefore the scope of following claim is the most broadly explained, thereby is contained all such modifications and equivalent structure and function.
Claims (13)
1. the manufacture method of a photoelectric conversion device, described photoelectric conversion device comprises:
Photo-electric conversion element,
A plurality of MOS transistor, it comprises the transfer MOS transistor and the amplifying mos transistor that is used for coming based on the electric charge that shifts read output signal that is used for electric charge is transferred to from photo-electric conversion element first semiconductor region,
The wiring layer that comprises a plurality of wirings,
A plurality of interlayer insulating films, it comprises first interlayer insulating film that covers described photo-electric conversion element and a plurality of MOS transistor, and is layered in second interlayer insulating film on described first interlayer insulating film,
Wherein, described photoelectric conversion device also comprises first and second electric conductors,
Described first electric conductor is embedded in first hole that is formed in described first interlayer insulating film, is used for not being electrically connected by the wiring that is included in wiring layer the gate electrode of described first semiconductor region and amplifying mos transistor,
Described second electric conductor is electrically connected second semiconductor region and is included in the wiring of first in the wiring layer, second semiconductor region is different with described first semiconductor region, and described second electric conductor comprises the 3rd electric conductor and the 4th electric conductor that piles up mutually and be electrically connected, described the 3rd electric conductor is embedded in second hole that is formed in described first interlayer insulating film, described the 4th electric conductor is embedded in the 3rd hole that is formed in described second interlayer insulating film, and described method step has:
Described first electric conductor of embedding in described first hole; And
Described the 3rd electric conductor of embedding in described second hole; Wherein
The step of the step of described embedding first electric conductor and embedding the 3rd electric conductor is carried out simultaneously.
2. according to the manufacture method of claim 1, wherein, the described first and the 3rd electric conductor has equal height.
3. according to the manufacture method of claim 1; Wherein, Described opto-electronic conversion device also comprises the 5th electric conductor; Be used for to be electrically connected second wiring that is included in wiring layer and to be included in a plurality of MOS transistors but to be different from the gate electrode of the MOS transistor of amplifying mos transistor; And described the 5th electric conductor comprises the 6th electric conductor that is embedded in the 4th hole that is formed in described first interlayer insulating film and the 7th electric conductor that is embedded in the 5th hole that is formed in described second interlayer insulating film; The the described the 6th and the 7th electric conductor is stacking and electrical connection mutually; And wherein
Described in first hole embedding first electric conductor step and in the 4th hole the step of embedding the 6th electric conductor carry out simultaneously.
4. according to the manufacture method of claim 1, wherein, described second semiconductor region forms one or more electrode districts of a plurality of MOS transistor.
5. according to the manufacture method of claim 1, also comprise the steps:
In first hole, before the step of embedding the 3rd electric conductor, in described first and second holes, form double-deck barrier film before the step of embedding first electric conductor and in second hole, and
In the 3rd hole, before the step of embedding the 4th electric conductor, in the 3rd hole, form the individual layer barrier film.
6. according to the manufacture method of claim 5, wherein,
Described first, third and fourth electric conductor is formed by tungsten, and
Described individual layer barrier film is by any formation the in titanium nitride, tantalum nitride, tungsten nitride and the tungsten silicide.
7. according to the manufacture method of claim 1, wherein,
Described wiring layer also comprises the 3rd wiring at least a portion that is arranged in the first electric conductor area just above on second interlayer insulating film.
8. according to the manufacture method of claim 7, wherein,
Described the 3rd wiring is the power line that is used for to amplifying mos transistor power supply voltage, perhaps through its holding wire from the amplifying mos transistor output signal.
9. according to the manufacture method of claim 1, wherein, the second area that described first electric conductor comprises the first area that is arranged in the first semiconductor region area just above and is arranged in the gate electrode area just above of amplifying mos transistor, make and described first and second zones between the direction of boundary-intersected on, the length of described first area and the length ratio of second area are 0.6-1.
10. according to the manufacture method of claim 9, wherein, described ratio is 0.7 or bigger.
11. according to the manufacture method of claim 1, wherein,
Described gate electrode is arranged such that the part of described gate electrode is positioned at the element isolation zone top, and described element isolation zone is formed by STI.
12. the manufacture method of a photoelectric conversion device, described photoelectric conversion device comprises:
A plurality of photo-electric conversion elements,
Be used for electric charge is transferred to the transfer MOS transistor of first semiconductor region from photo-electric conversion element, and
Be used for coming the amplifying mos transistor of read output signal based on the electric charge that shifts,
Described method comprises the steps:
On Semiconductor substrate, form photo-electric conversion element, first semiconductor region, shift MOS transistor and amplifying mos transistor;
First interlayer insulating film that form and cover described photo-electric conversion element, shifts MOS transistor and amplifying mos transistor;
In described first interlayer insulating film, form single hole, comprise the zone of the part of the part of gate electrode of amplifying mos transistor and first semiconductor region with exposure;
In described first interlayer insulating film, form the hole, comprise the zone of at least a portion of the electrode district of amplifying mos transistor with exposure;
Embedding first electric conductor in described single hole;
Comprise embedding second electric conductor in the hole in zone of at least a portion of electrode district of amplifying mos transistor in described exposure;
Form second interlayer insulating film that covers described first and second electric conductors;
Zone corresponding at least a portion that comprises second electric conductor in second interlayer insulating film forms the hole;
Embedding the 3rd electric conductor in corresponding to the hole in the zone of at least a portion that comprises second electric conductor; And
On described the 3rd electric conductor, form the wiring that is electrically connected with described the 3rd electric conductor,
Wherein, the step of the step of embedding first electric conductor and embedding second electric conductor is carried out simultaneously.
13. manufacture method according to claim 12, wherein, described photoelectric conversion device also comprises the 5th electric conductor, be used for being electrically connected second wiring that is included in wiring layer and be included in a plurality of MOS transistor but be different from the gate electrode of the MOS transistor of described amplifying mos transistor, and described the 5th electric conductor comprises the 6th electric conductor and the 7th electric conductor, and wherein
Described method comprises the steps:
Embedding the 6th electric conductor in the 4th hole in being formed on described first interlayer insulating film; And
Embedding the 7th electric conductor in the 5th hole in being formed on described second interlayer insulating film, the described the 6th and the 7th electric conductor piles up mutually and is electrically connected, and wherein,
Described in first hole embedding first electric conductor step and in the 4th hole the step of embedding the 6th electric conductor carry out simultaneously.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006235936 | 2006-08-31 | ||
| JP2006236760 | 2006-08-31 | ||
| JP2006235936 | 2006-08-31 | ||
| JP2007189447 | 2007-07-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101136367A true CN101136367A (en) | 2008-03-05 |
| CN100590846C CN100590846C (en) | 2010-02-17 |
Family
ID=39160348
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710148317A Expired - Fee Related CN100590846C (en) | 2006-08-31 | 2007-08-31 | Manufacturing method of photoelectric conversion device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100590846C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728326A (en) * | 2008-10-23 | 2010-06-09 | 东部高科股份有限公司 | Image sensor and method of fabricating the same |
| CN102201420A (en) * | 2010-03-25 | 2011-09-28 | 佳能株式会社 | Photoelectric conversion apparatus, image pickup system, and manufacturing method therefor |
| WO2012041033A1 (en) * | 2010-09-30 | 2012-04-05 | 中国科学院微电子研究所 | Method for forming metal interconnection structure, through hole between metallization layers and interconnect metallization lines |
| US8575019B2 (en) | 2010-09-30 | 2013-11-05 | Institute of Microelectronics, Chinese Academy of Sciences | Metal interconnection structure and method for forming metal interlayer via and metal interconnection line |
| CN104079844A (en) * | 2013-03-28 | 2014-10-01 | 佳能株式会社 | Imaging device, driving method of imaging device, and imaging system |
| CN106775063A (en) * | 2016-11-25 | 2017-05-31 | 京东方科技集团股份有限公司 | Contact panel and preparation method thereof, display device |
| CN113630517A (en) * | 2021-10-08 | 2021-11-09 | 清华大学 | Intelligent imaging method and device for light-electric inductance calculation integrated light field |
| US11569279B2 (en) | 2017-10-27 | 2023-01-31 | Sony Semiconductor Solutions Corporation | Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7023021B2 (en) * | 2000-02-22 | 2006-04-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
-
2007
- 2007-08-31 CN CN200710148317A patent/CN100590846C/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728326A (en) * | 2008-10-23 | 2010-06-09 | 东部高科股份有限公司 | Image sensor and method of fabricating the same |
| CN102201420B (en) * | 2010-03-25 | 2013-12-11 | 佳能株式会社 | Photoelectric conversion apparatus, image pickup system, and manufacturing method therefor |
| CN102201420A (en) * | 2010-03-25 | 2011-09-28 | 佳能株式会社 | Photoelectric conversion apparatus, image pickup system, and manufacturing method therefor |
| US9171799B2 (en) | 2010-03-25 | 2015-10-27 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus, image pickup system, and manufacturing method therefor |
| CN102446811B (en) * | 2010-09-30 | 2014-06-25 | 中国科学院微电子研究所 | Metal interconnecting structure and methods for forming metal interlayer through holes and interconnecting metal wire |
| US8575019B2 (en) | 2010-09-30 | 2013-11-05 | Institute of Microelectronics, Chinese Academy of Sciences | Metal interconnection structure and method for forming metal interlayer via and metal interconnection line |
| CN102446811A (en) * | 2010-09-30 | 2012-05-09 | 中国科学院微电子研究所 | Metal interconnecting structure and methods for forming metal interlayer through holes and interconnecting metal wire |
| WO2012041033A1 (en) * | 2010-09-30 | 2012-04-05 | 中国科学院微电子研究所 | Method for forming metal interconnection structure, through hole between metallization layers and interconnect metallization lines |
| CN104079844A (en) * | 2013-03-28 | 2014-10-01 | 佳能株式会社 | Imaging device, driving method of imaging device, and imaging system |
| CN104079844B (en) * | 2013-03-28 | 2017-07-14 | 佳能株式会社 | Imaging device, the driving method of imaging device and imaging system |
| CN106775063A (en) * | 2016-11-25 | 2017-05-31 | 京东方科技集团股份有限公司 | Contact panel and preparation method thereof, display device |
| CN106775063B (en) * | 2016-11-25 | 2020-04-21 | 京东方科技集团股份有限公司 | Touch panel, manufacturing method thereof and display device |
| US11569279B2 (en) | 2017-10-27 | 2023-01-31 | Sony Semiconductor Solutions Corporation | Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus |
| CN113630517A (en) * | 2021-10-08 | 2021-11-09 | 清华大学 | Intelligent imaging method and device for light-electric inductance calculation integrated light field |
| US11425292B1 (en) | 2021-10-08 | 2022-08-23 | Tsinghua University | Method and apparatus for camera-free light field imaging with optoelectronic intelligent computing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100590846C (en) | 2010-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11177310B2 (en) | Solid-state image pickup device | |
| EP1962345B1 (en) | Photoelectric conversion apparatus with dual-damascene interconnections and image pickup system using the same | |
| JP5305622B2 (en) | Method for manufacturing photoelectric conversion device | |
| CN100590846C (en) | Manufacturing method of photoelectric conversion device | |
| US9385152B2 (en) | Solid-state image pickup device and image pickup system | |
| KR101411800B1 (en) | Solid-state imaging device and imaging system | |
| US8853852B2 (en) | Semiconductor apparatus and electronic equipment | |
| US7683451B2 (en) | CMOS image sensors with light shielding patterns | |
| CN102201417A (en) | Solid-state imaging device, method of manufacturing the same, and electronic apparatus | |
| JP2009099626A (en) | Imaging device | |
| CN105023930B (en) | Solid-state image pickup apparatus and image picking system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100217 Termination date: 20200831 |