CN101131329A - Correction circuit for coder signal - Google Patents
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- CN101131329A CN101131329A CNA2007101437805A CN200710143780A CN101131329A CN 101131329 A CN101131329 A CN 101131329A CN A2007101437805 A CNA2007101437805 A CN A2007101437805A CN 200710143780 A CN200710143780 A CN 200710143780A CN 101131329 A CN101131329 A CN 101131329A
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Abstract
A correcting circuit of the encoder signal with a high position detecting precision can also correct the phase error with a simple arithmetic processing at the condition that the frequency of the 2-phase sign signal which is used for interpolating is high. The position detector comprises the following components: a peak detector which detects the output signal of the AD convertor, namely the peak value of A1 signal and B1 signal; an excursion/amplitude correcting circuit which uses the detected peak value, corrects the error of the excursion and the amplitude, and generates A2 and B2 signal; a phase error detector which detects the intersection value between the A2 signal and the B2 signal; a phase correcting circuit which calculates the correction index of the A2 signal and B2 signal according to the intersection value detected by the phase error detector; a position data converting circuit which converts the sine signal of A phase and B phase to the position data, and the position detector is also arranged with the following components: a speed detector which detects the frequency of the sine signal of A phase and B phase; and a correction judging circuit which judges the update of the correction value that is switched to excursion, amplitude and phase is valid or invalid.
Description
Technical Field
The present invention relates to a circuit for correcting an offset, an amplitude, and a phase of a sinusoidal signal of 2 phases in an encoder for obtaining high resolution by interpolating an orthogonal sinusoidal signal of 2 phases.
Background
In general, a rotary (or linear) encoder is configured to detect a position of the encoder by a light emitting element, a light receiving element, and a rotary (or movable) body having a lattice-shaped slit (slit) formed therebetween, and a resolution is determined by a lattice-shaped slit interval. Therefore, the slit interval is reduced for improving the resolution, but there is a limit to improve the resolution in this method because of the processing accuracy or the diffraction phenomenon of light.
Accordingly, the following methods are generally performed in recent years: sinusoidal analog signals of A and B phases having a phase difference of 90 degrees are generated in synchronization with signals between slits of a rotating body (or a moving body), and a signal obtained by interpolating the analog signals and a signal obtained by the slits are synthesized, thereby improving resolution.
In order to further increase the resolution of the encoder, it is necessary to increase the resolution of the interpolation process, that is, to increase the resolution of an AD converter that converts an analog signal into a digital signal, thereby increasing the overall resolution. The AD converter can be built in a microcomputer (micro computer) or LSI, but the resolution of the built-in AD converter is 10bit higher, and the accuracy is generally poor, and in particular, it is necessary to use a single AD converter IC in order to improve the resolution.
The AD converter IC, the microcomputer, or the LSI has a parallel system and a serial system, but the serial system is effective in terms of downsizing and cost. However, the serial method has a problem that a sampling period of transmission data becomes long. For example, when the sampling period of the AD converter is long, the number of detections per period decreases when the frequency of the sinusoidal signal of 2 phases increases, and it is difficult to perform correction of the offset, amplitude, and phase required for improving the accuracy of the interpolation process with high accuracy.
As a means for solving these problems, for example, in Japanese patent application laid-open No. Hei 7-218288, such a method is adopted: the attenuation coefficient of the amplitude of the 2-phase sinusoidal signal when the frequency becomes high is stored in advance in the memory, and the amplitude correction amount is changed to compensate for the attenuation amount. However, although the attenuation amount of the 2-phase sinusoidal signal can be corrected, if the sampling period becomes long and the frequency of the 2-phase sinusoidal signal becomes high, the maximum value or the minimum value cannot be accurately detected, and an error occurs in the correction value.
Fig. 11 is a diagram showing detected waveforms of the maximum value and the minimum value when the frequencies of the 2-phase sinusoidal signals A1 and B1 are high, and fig. 12 is a diagram showing waveforms of intersections C45 and C225 where the 2-phase sinusoidal signals are detected in order to detect the phase error amount. When the frequency is high, the influence of a long conversion sampling period of the AD converter appears, and the converted sinusoidal signal has a staircase shape as shown in fig. 11 and 12, and therefore it is difficult to accurately detect the maximum value/minimum value and the phase error.
In a state including the maximum value/minimum value and the phase error, the waveform obtained by correcting the 2-phase sinusoidal signal becomes a distorted waveform as shown in fig. 13. In the case of such a high frequency, the following problems occur: even if the amplitude attenuation coefficient is corrected, errors occur in the correction values of the offset, amplitude, and phase, and the accuracy of the interpolation process deteriorates.
Disclosure of Invention
The encoder signal correction circuit of the present invention has the following configuration. The position detector includes an AD converter for converting sinusoidal signals of orthogonal A-phase and B-phase into digital data to generate an A1 signal and a B1 signal; a peak detector detecting a maximum value and a minimum value of the A1 signal and the B1 signal; an offset/amplitude correction circuit for obtaining offset and amplitude correction values from the errors of the offset and amplitude using the maximum value and the minimum value detected by the peak detector, correcting the offset and the amplitude, and generating an A2 signal and a B2 signal; a phase error detector for detecting the amount of phase error between the A2 signal and the B2 signal; a phase correction circuit for obtaining a phase correction value based on the phase error amount detected by the phase error detector, and generating an A3 signal and a B3 signal having a phase difference of 90 degrees; a position data conversion circuit which converts the A3 signal and the B3 signal into position data, and which further includes: a speed detector that detects the frequencies of the A phase and the B phase; and a correction determination circuit that makes the update of the correction value of the offset and amplitude and the correction value of the phase effective or ineffective. A correction determination circuit that invalidates the update of the correction values of the offset and amplitude and the correction value of the phase when the frequency detected by the speed detector exceeds a set frequency; when the frequency detected by the speed detector is equal to or lower than the set frequency, the correction determination circuit effectively updates the correction values of the offset and amplitude and the correction value of the phase.
According to the above configuration, it is possible to obtain an encoder signal correction circuit that can correct the offset amounts with high accuracy even if the 2-phase sinusoidal signal shifts or fluctuates in amplitude or phase due to aging, and that does not suffer from an influence due to a sparse sampling period when the frequency of the 2-phase sinusoidal signal is high.
Drawings
Fig. 1 is a block diagram of an encoder circuit in a first embodiment of the present invention.
Fig. 2 is an explanatory diagram of an operation waveform of the peak detector in the first embodiment.
Fig. 3 is an explanatory diagram of an operation waveform of the phase error detector in the first embodiment.
Fig. 4 is an explanatory diagram of a result of interpolation processing performed on a sinusoidal signal not using the correction determining means when the number of samples in one cycle of the sinusoidal signal is 14.
Fig. 5 is an explanatory diagram of the result of the interpolation process performed on the sinusoidal signal in the first embodiment when the number of samples in one cycle of the sinusoidal signal is 14.
Fig. 6 is a block diagram of an encoder circuit in the second embodiment.
Fig. 7 is an explanatory diagram of amplitude-temperature characteristics in the second embodiment.
Fig. 8 is an explanatory diagram of offset-temperature characteristics in the second embodiment.
Fig. 9 is a block diagram of an encoder circuit in the third embodiment.
Fig. 10 is a block diagram of an encoder circuit in the fourth embodiment.
Fig. 11 is an explanatory diagram of detecting the maximum value/minimum value of a sinusoidal signal in the conventional example.
Fig. 12 is an explanatory diagram of an error amount of a detected phase in the conventional example.
Fig. 13 is an explanatory diagram of a corrected sinusoidal signal in the conventional example.
Detailed Description
(first embodiment)
A phase correction circuit for an encoder signal according to the present invention will be described with reference to fig. 1 to 8. Fig. 1 is a block diagram showing an encoder signal processing circuit including offset/amplitude correction and phase correction, fig. 2 is an operation waveform showing a peak detector, fig. 3 is an operation waveform showing a phase error detector, and fig. 4 and 5 are operation waveforms showing a peak detector and a phase error detector at a high frequency.
In fig. 1, the A0 signal and the B0 signal simulated in the original signal output from the encoder are sinusoidal signals of a phase and B phase having a phase difference of 90 degrees. Generally, the light emitting element, the light receiving element, and the slit plate are provided.
The light-emitting element uses an LED or a laser, and the light-receiving element uses a photodiode or a light-emitting transistor. The slit plate is made of glass or a resin material that transmits light, and a grid-like mask that blocks light is provided on the slit plate. The light receiving element receives light transmitted through the slit plate from the light emitting element, and the slit plate is provided on the rotating body of the encoder, so that the slit plate is formed into a lattice shape such that a sinusoidal waveform is output from the light receiving element during rotation.
The AD converter 2 converts the analog signals A0 and B0 output from the encoder into digital signals. Since the amplitude of the analog signal output from the encoder is several hundred mV, the analog signal is amplified by several tens times using an amplifier or the like, converted into a voltage that matches the input range (range) of the AD converter 2, and used, whereby the accuracy of the digital signal can be improved.
The peak detector 15 detects the maximum value/minimum value of the A1 signal and the B1 signal which are output signals of the AD converter 2. Fig. 2 shows an operation waveform of the peak detector 15, and a maximum value/minimum value detection method will be described using this.
In fig. 2, the | A1| signal and the | B1| signal are signals obtained by converting the absolute values of the A1 signal and the B1 signal, respectively. The intersections of the | A1| signal and the | B1| signal are detected to generate intersection signals 18a, 18B, 18c, and 18d. As shown in fig. 2, the intersection signal is divided into a region 1 to a region 4 in one cycle, where the region 1 is a region for detecting the maximum value of the A1 signal, the region 2 is a region for detecting the minimum value of the B1 signal, the region 3 is a region for detecting the minimum value of the A1 signal, and the region 4 is a region for detecting the maximum value of the B1 signal.
To explain the operation of the area 1, first, when the intersection signal 18a is detected, the previous value and the present value of the A1 signal are compared, and when the present value is large, the latch data 16a (max) is updated, and when the present value is small, the latch data 16a (max) is not updated. This operation is repeated in the section of the area 1, and when the intersection signal 18b is detected, the latch data 16a (max) is determined as the maximum value of the A1 signal. The operations of the area 2, the area 3, and the area 4 are the same as those of the area 1, and therefore are omitted. In this way, the maximum/minimum values of the A1 signal and the B1 signal can be detected.
The offset/amplitude correction circuit 4 performs offset removal and amplitude normalization on the A1 signal and the B1 signal using the maximum value/minimum value signal 16 detected by the peak detector 15.
Using the maximum/minimum value signal 16, the offsets (OS _ DETa ) of the A1 signal and the B1 signal can be obtained from equation 1. Further, if the corrected offset value is set to OS _ LEVEL and the signal from which the offset is removed is set to the A1d signal and the B1d signal, the offset can be removed according to equation 2.
Using the maximum/minimum value signal 16, the amplitude values (PP _ DETa, PP _ DETb) of the A1 signal and the B1 signal can also be found from equation 3. Further, if the normalized magnitude of the amplitude is K, the A2 signal and the B2 signal in which the offset and the error in the amplitude are corrected can be obtained from equation 4.
The phase correction module 9 is composed of a phase correction circuit 6 and a phase error detector 7, and functions as follows: the phase error of the A2 signal and the B2 signal, the offset and amplitude of which have been corrected, is detected by the phase error detector 7, and the a correction signal and the B correction signal, which correct the phase error of the A2 signal and the B2 signal, are used by the phase correction circuit 6 based on the amount of error detected by the phase error detector 7, thereby outputting the A3 signal and the B3 signal having a phase difference of 90 degrees.
Details of this operation will be described with reference to fig. 3. Fig. 3 is an example in which only the phase of the B2 signal is advanced by α radians with reference to the A2 signal. Since the amplitudes are normalized to the magnitude K by the offset/amplitude correction circuit 4, the amplitudes of the A2 signal and the B2d signal become K.
The phase error detector 7 detects the size of the intersection of the A2 signal and the B2d signal when the intersection signals 18a, 18B, 18c, and 18d are detected, and calculates and derives a phase correction amount from the intersection value. The A2 signal and the B2d signal can be expressed as in equation 5. The intersections of the A2 signal and the B2d signal at this time intersect each other at (π/4- α/2) radians and (5 π/4- α/2) radians, and the size of the intersections becomes Ksin (π/4- α/2) and Ksin (5 π/4- α/2).
Since the sizes are equal to each other, when C45= Ksin (pi/4-alpha/2) and C225= Ksin (5 pi/4-alpha/2), the phase error α/2 can be obtained from equation 6. In addition, since the B correction signal is obtained based on the A2 signal in equation 6, sin is used as a basis -1 But obviously also based on the B2d signal, according to cos -1 The formula (c) is obtained.
The phase correction circuit 6 can correct the phase error according to equations 7 and 8. Where Kp1 and Kp2 are phase correction gains for obtaining the a correction signal and the B correction signal, and the phase correction gains are set so that the phase difference between the A3 signal and the B3 signal becomes 90 degrees.
A3= A2+ Kp1 · B2d = Ksin θ + Kp1 · Kcos (θ + α). · where (formula 7)
B3= B2d + Kp2 · A2= Kcos (θ + α) + Kp2 · Ksin θ. (formula 8)
Next, the method for obtaining Kp1 and Kp2 will be described. In equation 7, θ = - α/2, since the A3 signal may be set to 0, kp1 can be obtained from equation 9.
Similarly, in formula 8, when θ = pi/2- α/2, B3 may be set to 0, and therefore Kp2 can be obtained from formula 10.
Kp1 and Kp2 obtained from expressions 9 and 10 can be expressed by the same expression, and therefore the burden of calculation processing is reduced by half. The A2 signal and the B2 signal (B2 d signal) are subjected to α/2 calculation by equation 6, and the phase correction gain is calculated by equation 9 or equation 10, and the A3 signal and the B3 signal with the phase offset corrected can be obtained by using equations 7 and 8.
Next, the magnitude of the phase-corrected A3 signal and B3 signal will be described. Since the maximum values of the amplitudes of expressions 7 and 8 are points θ = pi/2- α/2 and θ = - α/2, respectively, when these expressions 7 and 8 are taken, the A3 signal and the B3 signal are expressed by expressions 11 and 12, and can be corrected to have the same magnitude as shown in fig. 3. Since two intersections exist in one cycle of the 2-phase signal, the two intersections may be averaged with Kp obtained from the respective intersections.
Next, the position data conversion circuit 10 will be described. Using the A3 signal and the B3 signal having a phase difference of 90 degrees, the interpolated angle data θ IP (14) can be easily converted using equation 13.
θIP＝tan -1 (A3/B3.)... (formula 13)
Next, correction value update circuit 23 of the present invention is explained. The correction value update circuit 23 is constituted by the speed detector 21 and the correction determination circuit 22. The speed detector 21 detects the frequency signal 19 of the 2-phase sinusoidal signal. Since the frequency is the amount of shift between the samples of the A1 signal and the B1 signal detected by the AD conversion unit 2, it can be easily determined by calculating the difference between the previous detection value and the current detection value.
As another method, the frequency can be obtained by comparing sinusoidal signals of 2 phases at the center value of each sinusoidal wave and converting the signals into rectangular waves, and measuring the time between the edges of the converted rectangular waves. The correction determination circuit 22 receives the frequency information of the frequency signal 19 obtained by the speed detector 21, and outputs a correction value update signal 20 (for example, a signal L when updating of the correction value is invalid) to the peak detector 15 and the phase error detector 7 so that the correction values of the offset, the amplitude, and the phase are not updated when the frequency signal 19 is higher than a certain set frequency.
When the frequency signal 19 is lower than the set frequency, a correction value update signal 20 (for example, a signal H when updating of the correction value is enabled) is output to the peak detector 15 and the phase error detector 7 in order to update the correction values of the offset, the amplitude, and the phase.
The frequency of the switching correction value update signal 20 is set to a value that enables correct detection of the correction value. The frequency is set so that 72 divisions (sampling every 5 degrees) or more can be detected during one cycle of the 2-phase sinusoidal signal, and the error of the correction value can be suppressed to be small. When the 2-phase sinusoidal signal is likely to fluctuate due to the influence of temperature, power supply voltage, and noise, the number of divisions (for example, sampling every 10 degrees) may be set to a small number, although the position detection accuracy of the encoder deteriorates.
Further, the setting of the frequency of updating the correction value is made to have hysteresis characteristics, and the setting of switching from the invalid to the valid frequency is made to be lower than the setting of switching from the valid to the invalid frequency, whereby a stable switching operation can be achieved.
Fig. 4 and 5 show the result of interpolation processing of 2-phase sinusoidal signals, and both show the case where the AD conversion unit 2 samples 14 times during one cycle of a sinusoidal wave in the high-frequency operation state. Fig. 4 shows a case where the correction determination means is not provided in the conventional method, and fig. 5 shows waveforms in a case where the correction determination circuit of the present invention is provided and the update of the correction value is invalidated. In the conventional method, the detection of the correction value cannot be performed normally, and therefore, the difference between samples varies, but the method of the present invention may be substantially constant.
As described above, by the circuit configuration and the arithmetic processing according to the first embodiment, it is possible to obtain a high-resolution encoder that can correct the shift amounts with high accuracy even if the shift, amplitude, and phase of the 2-phase sinusoidal signal vary with time, and that does not suffer from the influence of the thinning of the sampling period when the frequency of the 2-phase sinusoidal signal is high.
(second embodiment)
A second embodiment of the present invention will be described with reference to fig. 6 to 8. The difference from the first embodiment is that the temperature detector 24 is provided to measure the temperature around the circuit and the offset or the correction amount of the amplitude is corrected by the temperature.
Fig. 6 is a diagram for calculating angle data θ IP (14) using sinusoidal signals A0 and B0 of 2 phases in the same manner as in fig. 1, and this configuration is different from fig. 1 in that temperature data 33 is output to peak detector 15.
The temperature detector 24 measures the temperature around the circuit, and can easily detect the temperature by using a thermistor or a temperature sensor IC. When the correction determination circuit 22 outputs a signal (correction value update signal 20) that renders updating of the correction value ineffective, the peak detector 15 stores the correction amounts of the offset and amplitude at that time and the temperature at that time.
The temperature data 33 from the temperature detector 24 is periodically inputted to the peak value detector 15, and compared with the stored temperature, and if a temperature difference is generated, correction of correction values of offset and amplitude is performed in accordance with the temperature.
Fig. 7 and 8 are graphs showing the amplitude-temperature characteristic and the offset-temperature characteristic, respectively, and temperature coefficients are obtained in advance from these temperature characteristics. In addition, when the data is nonlinear, the ROM is set with a rate of change with temperature, so that the temperature can be easily corrected.
As described above, according to the circuit configuration and the arithmetic processing of the second embodiment, it is possible to obtain a high-resolution encoder capable of correcting the shift amount with high accuracy even if the shift amount or the amplitude/phase variation of the 2-phase sinusoidal signal is caused by a temperature change or a time-dependent change, and free from an influence due to a sparse sampling cycle even when the frequency of the 2-phase sinusoidal signal is high.
(third embodiment)
A third embodiment of the present invention will be described with reference to fig. 9. A circuit configuration in which the LED light amount correction circuit 31 is added to the configuration for generating the 2-phase sinusoidal signals A0 and B0, and the amplitude of the A0 signal and the B0 signal is kept constant without being affected by the deterioration of the LED (light emitting element) or the temperature characteristics of the LED and the light receiving element, which is different from the second embodiment, will be described.
The LED light amount correction circuit 31 is constituted by the LED light emitting circuit 25, the LED light receiving circuit 27, and the LED light amount control circuit 29. The LED lighting circuit 25 is constituted by an LED (light emitting element) and a transistor for regulating a current flowing to the LED.
By increasing the current flowing through the LED, the LED light emission amount 26 can be increased. The LED light receiving circuit 27 is composed of a light receiving element such as a PD (photodiode) or a PTR (light emitting transistor) and an operational amplifier.
When light from the LED is received, the light receiving element converts the light into a voltage according to the amount of the light and outputs the voltage. These voltages are very small voltage values of several hundreds mV, and are therefore amplified by the operational amplifier. The LED light receiving circuit 27 is provided with not only a light receiving element for generating a sinusoidal signal but also a light receiving element for measuring the amount of light, and the measured amount of light is output as a measured light amount 28.
The LED light amount control circuit 29 compares the measured light amount 28 with a predetermined reference voltage, and generates a light amount control signal 30 so that they are equal to each other by a control circuit such as proportional-integral control. The generated light amount control signal 30 is input to the LED lighting circuit 25 for adjusting the current flowing to the LED.
The reference voltage set in the LED light amount control circuit 29 may be set so that the amplitudes of the 2-phase sinusoidal signals A0 and B0 generated by the LED light amount correction circuit 31 are within the measurable level of the AD conversion circuit 2.
As described above, according to the circuit configuration and the arithmetic processing of the third embodiment, by providing the LED light amount correction circuit 31, the amplitude fluctuation of the 2-phase sinusoidal signals A0 and B0 can be reduced, and therefore, a high-resolution encoder that is resistant to temperature change and aging change and that is not affected by the thinning of the sampling period when the frequency of the 2-phase sinusoidal signal is high can be obtained.
(fourth embodiment)
A fourth embodiment of the present invention will be described with reference to fig. 10. The correction determination circuit 22 has 2 kinds of set frequencies for determination, which is different from the third embodiment, and this will be described.
The correction determination circuit 22 may individually set signals for enabling or disabling the updating of the correction values of the offset and amplitude, and the correction value of the phase, respectively. When the frequencies of the 2-phase sinusoidal signal A0 signal and the B0 signal are high, the sampling period of the AD conversion circuit 2 is long, and thus the detection interval is sparse.
The A1 signal and the B1 signal of the 2-phase sinusoidal signal detected by the peak detector 15 are less affected by the thinning of the sampling period because the change in the magnitude of the value around the peak is small. Therefore, the 1 st setting frequency for determining the update of the correction values of the offset and the amplitude can be set high in the correction determination circuit 22.
For example, even if an offset of ± 8 degrees is generated, the peak value is attenuated by 1%. In a system where 1% variation is allowable, the number of samples per cycle of the 2-phase sinusoidal signal may be allowed up to a frequency of 22.5 (360/16). The phase correction value detects the intersection of the A2 signal and the B2 signal of the 2-phase sinusoidal signal, and when the intersection value changes by 1%, the range of the angle becomes ± 0.6 degrees. Therefore, the 2 nd setting frequency for determining the update of the phase correction value is set lower than the 1 st setting frequency in the correction determination circuit 22.
As described above, by adopting the 2 configurations in which the frequencies set in the correction determining circuit 22 of the fourth embodiment are set separately for offset and amplitude correction and phase correction, it is possible to reduce the amplitude variation of the sinusoidal signals A0 and B0 of the 2 phases, and therefore, it is possible to obtain a high-resolution encoder that is resistant to temperature change and aging change and that is not affected by the sparseness of the sampling period when the frequency of the sinusoidal signal of the 2 phases is high.
(fifth embodiment)
A fifth embodiment of the present invention will be explained. The correction determination circuit 22 is configured to determine whether or not updating of the offset and amplitude correction values or the phase correction values is valid or invalid, which is different from the first to fourth embodiments, and this will be described in detail. In a system in which the frequencies of the A0 signal and the B0 signal of the 2-phase sinusoidal signal are low, since the fluctuation of the amplitude can be ignored as described above, there is no problem in that the updating of the offset and the correction value of the amplitude is always effective. At this time, it is detected whether only the update of the correction value of the phase correction is valid or invalid.
In addition, in a linear detection element (linear scale) or the like, the amount of phase shift may be determined by the accuracy of the grid-like slit plate, and in this case, the phase correction circuit 6 may perform only the shift and amplitude correction without performing the phase correction processing. The correction determination circuit 22 may determine whether the update of the correction values of the offset and the amplitude is valid or invalid.
As described above, the correction determination circuit 22 may be configured to determine whether the update of the correction value of the offset and the amplitude is valid or invalid or whether the update of the phase correction value is valid or invalid, and since the circuit scale can be suppressed to be small, a high-resolution encoder that is less likely to be affected by the thinning of the sampling period when the frequency of the 2-phase sinusoidal signal is high, while reducing the cost and preventing the temperature change and the aging change can be obtained.
In addition, although the phase 2 signal is described as a sine wave in the first to fifth embodiments, a pseudo sine wave or a triangular wave having a distorted waveform may be corrected in phase with the same configuration.
Claims (5)
1. A correction circuit for an encoder signal,
the position detector includes: an AD conversion circuit for converting sinusoidal signals of an orthogonal A phase and a B phase into digital data to generate an A1 signal and a B1 signal; a peak detector detecting a maximum value and a minimum value of the A1 signal and the B1 signal; an offset/amplitude correction circuit which obtains correction values of offset and amplitude from errors of the offset and amplitude using the maximum value and the minimum value detected by the peak detector, corrects the offset and the amplitude, and generates an A2 signal and a B2 signal; a phase error detector that detects a phase error amount of the A2 signal and the B2 signal; a phase correction circuit for obtaining a phase correction value based on the phase error amount detected by the phase error detector, and generating an A3 signal and a B3 signal having a phase difference of 90 degrees; a position data conversion circuit which converts the A3 signal and the B3 signal into position data, and which further includes:
a speed detector that detects the frequencies of the A-phase and the B-phase; and a correction determination circuit that sets the correction values of the offset and amplitude and the update of the correction value of the phase to be valid or invalid,
the correction determination circuit invalidates the updates of the correction values of the offset and amplitude and the correction value of the phase when the frequency detected by the speed detector exceeds a set frequency; the correction determination circuit is effective to update the correction values of the offset and amplitude and the correction value of the phase when the frequency detected by the speed detector is equal to or less than a set frequency.
2. The correction circuit for an encoder signal according to claim 1, further comprising a temperature detector for measuring a temperature around the circuit,
when the correction values of the offset and amplitude and the update of the correction value of the phase are invalidated by the correction determination circuit, the correction values of the offset and amplitude are corrected based on the temperature coefficients of the sinusoidal signals of the a phase and the B phase, which are obtained in advance from the temperature detected by the temperature detector and the temperature difference when the correction values of the offset and amplitude are calculated.
3. The correction circuit of an encoder signal according to claim 1,
an LED light amount correction circuit for controlling the amplitude of the sinusoidal signals of the A phase and the B phase to be constant is provided at a stage preceding the AD conversion means.
4. The correction circuit of an encoder signal according to claim 1,
the correction determination circuit invalidates the update of the correction values of the offset and the amplitude when the frequency detected by the speed detector exceeds a1 st set frequency; the correction determining circuit updates the correction values of the offset and the amplitude when the frequency detected by the speed detector is equal to or less than a1 st set frequency; the correction determination circuit invalidates the update of the correction value of the phase when the frequency detected by the speed detector exceeds a2 nd set frequency; the correction determination circuit updates the correction value of the phase to be valid when the frequency detected by the speed detector is equal to or less than a2 nd set frequency.
5. The correction circuit for an encoder signal according to claim 1,
the correction determination circuit enables or disables updating of the correction value by one of the offset and amplitude correction circuit and the phase correction circuit.
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| JP224872/06 | 2006-08-22 | ||
| JP2006224872A JP4277887B2 (en) | 2006-08-22 | 2006-08-22 | Encoder signal correction circuit |
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| CN101131329B CN101131329B (en) | 2011-01-05 |
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| JP2008051507A (en) | 2008-03-06 |
| JP4277887B2 (en) | 2009-06-10 |
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