CN101127527A - Frequency mixer and frequency mixing method - Google Patents
Frequency mixer and frequency mixing method Download PDFInfo
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Abstract
The utility model relates to a multi-frequency synthesizer used for generating MB-OFDM UWB system. The frequencies comprises a first frequency to a fourteenth frequency from high to low, a basic interval frequency is provided between any two adjacent frequencies. The multi-frequency synthesizer comprises a lock phase circuit, the frequency generated by the lock phase circuit is equal to the original signal of the second frequency; an interval frequency generator, the frequency generated by the interval frequency generator is equal to the first to third interval signal of the interval frequency integral times from low to high, and the generated frequency is equal to the fourth interval signal of the basic interval frequency, the series-connected first to third mixers receives the fourth interval frequency respectively and any one among the first to third frequency, and the first interval frequency respectively generates the first to third frequency, the fourth to the ninth frequency and the thirteen to the fourteen frequency, and the tenth to the twelfth frequency.
Description
Technical field
The invention relates to frequency synthesizer (Frequency synthesizer), and be particularly to a kind of multi-band orthogonal frequency division multiplex (MUX) (Multi-Band Orthogonal Frequency DivisionMultiplexing; MB-OFDM) super wideband (Ultra Wideband; UWB) frequency synthesizer of system.
Background technology
The super broadband system of multi-band orthogonal frequency division multiplex (MUX) (being designated hereinafter simply as MB-OFDM UWB system) is that the frequency band with 3.1 to 10.6G hertz is distinguished into the inferior frequency band that ten frequency ranges are the 528M hertz.Fig. 1 is the band diagram that shows MB-OFDM UWB system.As shown in the figure, the centre frequency of frequency band (hereinafter referred to as the first to the 14 frequency f l to f14) from left to right is 3432M hertz, 3960M hertz, 4488M hertz, 5016M hertz, 5544M hertz, 6072M hertz, 6600M hertz, 7128M hertz, 7656M hertz, 8184M hertz, 8712M hertz, 9240M hertz, 9768M hertz, 10296M hertz, and wantonly two these adjacent equifrequents are separated by basic interval frequency f dm (528M hertz).
According to the demand of MB-OFDM UWB system, the frequency synthesizer that produces these 14 frequency bands must have high frequency band switch speed, and must be lower than 9.5ns switching time.Existing several super wideband frequency synthesizers disclose to produce the frequency band of 3～8G hertz, in the middle of representative be known technology [1]: J.Lee, and D.W.Chiu, " A 7-Band 3-8GHz frequency synthesizer with lnsband-switching time in 0.18um CMOS technology; " ISSCC Dig of Tech.Papers, pp.204-205, Feb.2005, known technology [2]: C.C.Lin, and C.K Wang, " A regenerative semi-dynamic frequency divider for mode-1 MB-OFDM UWBhopping carrier generation; " ISSCC Dig of Tech.Papers, pp.206-207, Feb.2005, known technology [3]: A.Ismail, and A.Abidi, " A 3.1 to 8.2GHz directconversion receiver for MB-OFDM UWB communications; " ISSCC Dig of Tech.Papers, pp.206-207, Feb.2005, and known technology [4]: D.Leenaerts et al., " A SiGe BiCMOS lns frequency hopping frequency synthesizer for UWBradio; " ISSCC Dig of Tech.Papers, pp.202-203, Feb.2005.
Yet, centrally can produce whole in the MB-OFDM UWB system 14 frequency bands without any a frequency synthesizer.This is because will contain the frequency band of broadness like this, often needs considerable phase-locked loop and frequency mixer.This not only causes chip area excessive, and power dissipation is too high, also produce side frequency (spur) energy too high with switching time difficulty be lower than the problem of 9.5ns.
The high-rate wireless transmission certainly will be the target of following Development of Communication, adds that super wideband device has communication function in addition.Therefore, a kind ofly can contain as far as possible that the first to the 14 frequency in the MB-OFDM UWB system, frequency are switched fast, not want too high MB-OFDM UWB frequency synthesizer be necessary to some extent to the side frequency energy.
Summary of the invention
The present invention provides a kind of frequency combining method, in order to 14 frequencies of generation MB-OFDM UWB system, and a kind of frequency synthesizer of using this frequency combining method.Frequency synthesizer of the present invention not only includes only two phase-locked loops and three frequency mixers, and it is low to have a side frequency energy, and power dissipation is low, the advantage that switching rate is fast.
The present invention provides a kind of frequency combining method, in order to produce a plurality of frequencies of MB-OFDM UWB system, this equifrequent comprises the first to the 14 frequency from low to high, wantonly two these adjacent equifrequents are separated by the basic interval frequency are arranged, this method comprises: this equifrequent is divided into first to the 5th group of frequencies, wherein this first to the 5th group of frequencies comprises this first to the 3rd frequency respectively, the the 4th to the 6th frequency, the the 7th to the 9th frequency, and the 13 to 14 frequency, then produce this first frequency group, then to this first frequency group carry out mixing program with produce this second, three and five group of frequencies, and at last the 5th group of frequencies is carried out the mixing program to produce the 4th group of frequencies.
The present invention provides a kind of frequency combining method, in order to produce a plurality of frequencies of MB-OFDM UWB system, this equifrequent comprises the first to the 14 frequency from low to high, wantonly two these adjacent equifrequents are separated by the basic interval frequency are arranged, this method comprises: produce first to the 3rd spacing frequency from low to high, wherein this first to the 3rd spacing frequency is the integral multiple of this basic interval frequency, and be the interval output frequency one of in the middle of selecting, one of produce in the middle of this first to the 3rd frequency is first output frequency, this first output frequency and this interval output frequency are carried out Frequency mixing processing, in order to produce second output frequency, wherein this second output frequency is the 4th to the 9th frequency, one of in the middle of the 13 to 14 frequency and the 15 frequency, and with this second output frequency and this first at interval output frequency carry out Frequency mixing processing and produce the 3rd output frequency, wherein the 3rd output frequency is one of in the middle of the tenth to 12 frequency.
The present invention provides a kind of frequency synthesizer, and in order to produce a plurality of frequencies of MB-OFDM UWB system, this equifrequent comprises the first to the 14 frequency from low to high, and wantonly two these adjacent equifrequents are separated by the basic interval frequency is arranged.This frequency synthesizer comprises: phase-locked loop, spacing frequency generator, and first to three-mixer.This phase-locked loop produces initialize signal, and wherein the frequency of this initialize signal is to equal this second frequency.This spacing frequency generator, produce frequency first to the 3rd blank signal from low to high, wherein the frequency of this first to the 3rd blank signal is the integral multiple that equals this basic interval frequency, and the 4th spacing frequency, wherein the frequency of the 4th blank signal equals this basic interval frequency, and one of optionally exports in the middle of this first to the 3rd blank signal and to be output signal at interval.This first frequency mixer carries out optionally Frequency mixing processing with this initialize signal and the 4th blank signal, and produces first output signal, and wherein first output signal frequency is one of in the middle of this first to the 3rd frequency.This second frequency mixer carries out Frequency mixing processing with this first output signal and this interval output signal, and produce second output signal, one of wherein this second output signal frequency is the 4th to the 9th frequency, the 13 and the 14 frequency, and in the middle of the 15 frequency.This three-mixer carries out Frequency mixing processing with this second output signal and this first blank signal, and produces the 3rd output signal, and wherein the 3rd output signal frequency one of equals in the middle of the tenth to the 12 frequency.
Description of drawings
Fig. 1 is the band diagram that shows MB-OFDM UWB system.
Fig. 2 A and 2B show respectively and an embodiment of the flow chart of the method for the first to the 14 frequency of frequency generation plan schematic diagram of the present invention and the super wideband of generation multi-band orthogonal frequency division multiplex (MUX) provided by the present invention;
Fig. 2 C is a preferred embodiment of flow chart shown in the displayed map 2B;
Fig. 3 is an embodiment of structure calcspar who shows the frequency synthesizer of application method shown in Figure 3 proposed by the invention;
Fig. 4 is an embodiment of structure calcspar who shows the spacing frequency generator of Fig. 3 provided by the present invention;
Fig. 5 is shown in this preferred embodiment, an embodiment of the circuit structure diagram of voltage controlled oscillator provided by the present invention;
Fig. 6 shows the embodiment of four phase places provided by the present invention except that three circuit circuit structure diagram;
Fig. 7 is presented among the embodiment of application drawing 6, when first output frequency is chosen as when being the 3rd frequency (4488M hertz) energy of first output signal and the graph of a relation of frequency;
Fig. 8 A and 8B are the embodiment of circuit structure diagram of first frequency mixer of displayed map 3;
Fig. 9 is an embodiment of circuit structure diagram who shows second frequency mixer of Fig. 3 provided by the present invention;
Figure 10 A, 10B and 10C show when second output frequency belongs to the 5th group of frequencies, the 3rd group of frequencies and second frequency group the frequency response schematic diagram that two inductance capacitance resonant cavities of Fig. 9 have respectively; And
Figure 11 is presented among the embodiment of second frequency mixer of application drawing 9, when first output frequency is chosen as the 8th frequency, and the energy of first output signal and the graph of a relation of frequency.
[main element label declaration]
| 300～ |
302～ |
| 304～phase-locked |
306～the |
| 308～the |
310～the three- |
| 312～ |
410～phase-locked |
| 411～phase- |
412～ |
| 414～ |
416～voltage controlled |
| 420～the |
430～the |
| 440～the |
450～ |
| 452～two pairs one multiplexers | 454～two pairs one multiplexers |
| 501-504～normal phase input end | 505-508～inverting input |
| 510-540～first to fourth differential delay unit | 511-514～positive output end |
| 515-518～reversed-phase output | 611-613～first is to the 3rd D-type latch |
| 621-623～4th is to the 6th D-type latch | 631,632～first and second inverter |
| 640～phase alignment buffer module | 641-646～buffer |
| 802,804～input | 810～the first tristate buffers |
| 812,822～switch | 813,823～the first ends |
| 814,824～the second ends | 815,825～the 3rd ends |
| 816,826～inverter | 818,828～ |
| 820～the second tristate buffers | 830～the |
| 840～the second mixting circuits | 832,834～ |
| 850～inductance capacitance resonant cavity | 850 '～inductance capacitance |
| 900～monolateral |
910～ |
| 950～inductance capacitance resonant cavity | 861,862～first and second mixing |
| In-phase output end | |
| B11, b12, b21, b22～first to fourth capacitance switch | B1, b2～first is to second capacitance switch |
| C1 1、C1 2、C2 1、C2 2～first to fourth electric capacity | Co1, Co2～first is to second output capacitance |
| CLK～clock end | COM1-COM4～common-mode point |
| D～data input pin | F0-I, Q～initialize signal |
| F1-f15～the first to the 15 frequency | Fd1-fd4～first to fourth spacing frequency |
| Fd1-I, Q-fd4-I, Q～first to fourth blank signal | Fd1-I～first be in-phase signal at interval |
| Fd1-Q～first be orthogonal signalling at interval | Fd3-I (+)～3rd be the positive phase signals of in-phase signal at interval |
| Fd3-I (-)～3rd be the inversion signal of in-phase signal at interval | Fd3-Q (+)～3rd be the positive phase signals of orthogonal signalling at interval |
| Fd3-Q (-)～3rd be the inversion signal of orthogonal signalling at interval | Fd4-I (+)～4th be the positive phase signals of in-phase signal at interval |
| Fd4-I (-)～4th be the inversion signal of in-phase signal at interval | Fd4-Q (+)～4th be the positive phase signals of orthogonal signalling at interval |
| Fd4-Q (-)～4th be the inversion signal of orthogonal signalling at interval | The positive phase signals of in-phase signal is exported at fdo-I (+)～interval |
| The inversion signal of in-phase signal is exported at fdo-I (-)～interval | The positive phase signals of fdo-Q (+)～interval output orthogonal signal |
| The inversion signal of fdo-Q (-)～interval output orthogonal signal | Fd4-I～4th be in-phase signal at interval |
| Fd4-Q～4th be orthogonal signalling at interval | Fdo-I, Q～interval output signal |
| Fdm～minimum spacing frequency | Ff～final output frequency |
| Ff-I, Q～final output signal | Fo1-I, Q-fo3-I, Q～first is to the 3rd output signal |
| The positive of fo2-I (+)～second output in-phase signal | Fo2-I (-)～second output homophase |
| Signal | The inversion signal of signal |
| Fo2-I (+) ', fo2-I (-) '～mixing output positive and inversion signal | Fp～phase-locked input signal |
| Fr～reference signal | Group1-Group5～first is to the 5th group of frequencies |
| I1, I2, I3～first are to the 3rd constant current source | L1, L2～first and second inductance |
| Lo1, Lo2～first and second outputting inductance | The positive phase signals of LO-I (+)～mixing in-phase signal |
| The inversion signal of LO-I (-)～mixing in-phase signal | The positive phase signals of LO-Q (+)～mixing orthogonal signalling |
| The inversion signal of LO-Q (-)～mixing orthogonal signalling | M1-M12～first is to the tenth bi-NMOS transistor |
| R1-R4～first to fourth resistance | Mo1, mo2～first and second output nmos transistor |
| Q～data output end | VDD～direct voltage source |
Embodiment
Fig. 2 A shows frequency generation plan schematic diagram provided by the present invention, and Fig. 2 B is the flow chart of method that shows the first to the 14 frequency of generation MB-OFDM UWB provided by the present invention system.Now referring to Fig. 2 A, be to show the first to the 14 frequency f 1 to f14 respectively from the right side by a left side among the figure, represent respectively the required generation of the super wideband of multi-band orthogonal frequency division multiplex (MUX) 3432M, 3960M, 4488M ... 9768M, 10296M hertz, and wantonly two these adjacent equifrequents are separated by basic interval frequency f dm (528M hertz) is arranged.In addition, more than among the figure the 15 frequency f 15, it is the 10824M hertz, also is spaced apart basic interval frequency f dm (528M hertz) with the 14th frequency (10296M hertz).
Now referring to Fig. 2 B, and still simultaneously with reference to figure 2A to promote understanding.At first carry out step 200.In step 200, this first to the 14 frequency f 1 to f14 from low to high, per three frequencies are classified into one group, are classified into first to the 5th group of frequencies Group1 to Group5 altogether.
Then carry out step 202.In step 202, Group1 generates with this first frequency group.In a preferred embodiment, at first produce second frequency f2 (3960M hertz) and the 4th spacing frequency fd4 (528M hertz), then this second frequency and the 4th spacing frequency are carried out Frequency mixing processing and produce this first frequency group.
Next carry out step 204.Step 204 is that the first frequency group is carried out the mixing program, in order to this second and third and five group of frequencies Group2, Group3 and Group5 generate.In one embodiment, at first produce frequency from low to high and be all first to the 3rd spacing frequency fd1 to fd 3 of basic interval integral multiple, then this first frequency group Group1 and this first to the 3rd spacing frequency fd1 to fd 3 are carried out Frequency mixing processing to produce this second and third and five group of frequencies Group1, Group2 and Group5.
Next, carry out step 206,, and carry out the mixing program to produce the 4th group of frequencies Group4 according to the 5th group of frequencies Group5.In one embodiment, at first produce the first spacing frequency fd1, then the 5th group of frequencies Group5 and this first spacing frequency fd1 are carried out Frequency mixing processing to produce the 4th group of frequencies Group4.
Fig. 2 C is a preferred embodiment of flow chart shown in the displayed map 2B.Now referring to Fig. 2 C, and still simultaneously with reference to figure 2A and 2B to promote understanding.Step 212 is to produce from low to high and frequency is all first to the 3rd spacing frequency fd1 to fd3 of basic interval frequency f dm integral multiple, and be interval output frequency fdo one of in the middle of selecting.In this step, the 4th spacing frequency fd4, it equals basic interval frequency (528M hertz), also generates.In one embodiment, first to the 3rd spacing frequency fd1 to fd3 is respectively three times, six times and the twelvefold of basic interval frequency f dm, promptly is respectively 1584M hertz, 3168M hertz, and the 6336M hertz.
In an embodiment of step 212, second and third spacing frequency fd2 and fd3 (3168M hertz and 6336M hertz) are at first generated, for example be to use phase-locked loop, this phase-locked loop to comprise phase-frequency detector, eight-phase voltage controlled oscillator and first to the 3rd divider.At first use this phase-frequency detector to receive reference frequency fr (being the 66M hertz for example) and phase-locked incoming frequency fp, re-use this eight-phase voltage controlled oscillator and produce second spacing frequency fd2 of four phase places and the 3rd spacing frequency fd3 of four phase places.Next, with this second spacing frequency fd2 divided by first integer (for example be 2) to produce this first spacing frequency fd1, with this first spacing frequency fd1 divided by second integer (for example be 3) producing the 4th spacing frequency fd4, and with the 4th spacing frequency fd4 divided by the 3rd integer (being 8 for example) to produce this phase-locked incoming frequency fp.
Next carry out step 216.In step 216, first output frequency fo1 that step 214 produced and the interval output frequency fdo that step 212 produced are implemented Frequency mixing processing, in order to produce the second output frequency fo2=, first output frequency fo1+ output frequency fdo at interval.This Frequency mixing processing can use frequency mixer to reach, and preferable going up is monolateral frequency mixer.When (fo1, fdo) be selected as (f1, fd1), (f2, fd1), (f3, fd1), (f1, fd2), (f2, fd2), (f3, fd2), (f1, fd3), (f2, fd3), and (f3, fd3) time, the second output frequency fdo2 is respectively the 4th frequency f 4, the 5th frequency f 5, the 6th frequency f 6, the 7th frequency f 7, the 8th frequency f 8, the 9th frequency f the 9, the 13 frequency f the 13, the 14 frequency f 14 and the 15 frequency f 15 among Fig. 2 A.Summary, when interval output frequency fdo that step 212 produced was chosen as the first spacing frequency fd1 (1584M hertz), then the second output frequency fo2 may be selected to be the component frequency of second frequency group Group2, promptly one of in the middle of f4, f5, the f6; When interval output frequency fdo that step 212 produced was chosen as the second spacing frequency fd2 (3168 hertz), then the second output frequency fo2 may be selected to be the component frequency of the 3rd group of frequencies Group 3, promptly one of in the middle of f7, f8, the f9; When interval output frequency fdo that step 212 produced was chosen as the 3rd spacing frequency fd3 (6336 hertz), then the second output frequency fo2 may be selected to be the component frequency of the 5th group of frequencies Group5, promptly one of in the middle of f13, f14, the f15.In other words, step 216 is the steps 204 that correspond to Fig. 2 B, is used for producing second, third and the 5th group of frequencies Group2 shown in Fig. 2 A, Group 3, Group5.
In step 218, when the second output frequency fo2 is chosen as when belonging to the 5th group of frequencies Group5, second output frequency fo2 that step 216 produced and the first interval output frequency fd1 (1584 hertz) that step 202 produced are to accept Frequency mixing processing, in order to produce the 3rd output frequency fo3=(the second output frequency fo2-, the first spacing frequency fd1).This Frequency mixing processing can use frequency mixer to reach, and preferable going up is monolateral frequency mixer.Therefore when the second output frequency fdo2 was chosen as f13, f14 among Fig. 2 A and f15, the 3rd output frequency fo3 was respectively f10, f11 and f12.In other words, step 218 is the steps 206 corresponding to Fig. 2 B, is used for producing the 4th group of frequencies Group4 shown in Fig. 2 A.
At last, carry out step 220.In step 220, be selected as final output frequency ff one of in the middle of first to the 3rd output frequency fo1 to fo3, therefore final output frequency ff one of is chosen in the middle of the first to the 14 frequency f 1 to f14.Must note, because the 15 frequency f 15 is not to fall within the frequency band range of the super wideband of multi-band orthogonal frequency division multiplex (MUX), therefore even the second output frequency fo2 is chosen as the 15 frequency f 15, the second output frequency fo2 are selected as final output frequency ff in this step situation and can take place.
Fig. 3 is an embodiment who shows the structure calcspar of the frequency synthesizer 300 of method shown in application drawing 2B proposed by the invention and the 2C.As shown in the figure, frequency synthesizer 300 comprises spacing frequency generator 302, phase-locked loop 304, first frequency mixer 306, second frequency mixer 308, three-mixer 310 and multiplexer 312.
Phase-locked loop 304, in order to produce initial in-phase signal f0-I and initial orthogonal signalling f0-Q (below be referred to as initialize signal f0-I, Q), both frequencies are all the second frequency f2 shown in Fig. 3 (3960 hertz) and 90 ° of phase phasic differences.
Three-mixer 310, when spacing frequency generator 302 is output as the 3rd blank signal fd3-I, Q (frequency is 6336 hertz) thus make the second output signal fo2-I, when the frequency f o2 of Q belongs to the 5th group of frequencies Group5, with this second output signal fo2-I, Q and this first blank signal fd1-I, Q (frequency is the 1584M hertz) carries out Frequency mixing processing, then produce that frequency equates and the 3rd output in-phase signal fo3-I of 90 ° of phase phasic differences and the 3rd output orthogonal signal fo3-Q (below be referred to as the second output signal fo3-I, Q).The 3rd output signal fo3-I that this Frequency mixing processing produced, the frequency of Q (hereinafter referred to as the 3rd output frequency fo3) is to equal the second output frequency fo2-, the first spacing frequency fd1.Thus, when the second output frequency fo2 was the 13 frequency f the 13, the 14 frequency f 14 among Fig. 2 A and the 15 frequency f 15, the 3rd output frequency fo3 promptly equaled the tenth frequency f the 10, the 11 frequency f 11 and the 12 frequency f 12 respectively.Correspond to Fig. 2 C, three-mixer 310 execution in step 218.
Must note, first, second to three-mixer 306,308 and 310 are four phase mixer.Therefore, the initialize signal f0-I shown in the figure, Q, first to the 3rd output signal fo1-I, Q to fo3-I, Q, first to fourth blank signal fd1-I, Q to fd4-I, Q, and interval output signal fdo-I, in fact Q is all four phase signals.In-phase signal system comprises that positive and inversion signal, orthogonal signalling also comprise positive and inversion signal.For example, the second in-phase signal f2-I comprises positive phase signals f2-I (+) and inversion signal f2-I (-), and the second orthogonal signalling f2-Q also comprises in-phase signal f2-Q (+) and inversion signal f2-Q (-).
In addition, also must notice that for convenience of description, the circuit structure diagram shown in following Fig. 4 and 6 all presents with single-ended, is actually the both-end structure.Those skilled in the art when can scheme thus to push away easily this both-end structure.
Fig. 4 is an embodiment of structure calcspar who shows the spacing frequency generator 302 of Fig. 3 provided by the present invention.Spacing frequency generator 302 comprises phase-locked loop 410 and multiplexer module 450 as shown in the figure.This phase-locked loop 410 comprises phase-frequency detector 411, charge pump 412, low pass filter 414 and voltage controlled oscillator 416 and first to the 3rd divider 420,430 and 440 of serial connection.
The reference signal Sfr of phase-frequency detector 411 receive frequencies (being the 66M hertz for example), it has reference frequency fr, and phase-locked input signal Sfp, and it has phase-locked incoming frequency fp.Voltage controlled oscillator 416 is in order to produce this second and third blank signal fd2-I, Q and fd3-I, Q.
The second spacing frequency fd2 that first divider 420 is exported phase-locked loop 410 is the first blank signal fd1-I of fd2/N1 divided by first Integer N 1 (is 2 at this embodiment) in order to produce frequency, Q.
The first spacing frequency fd1 that second divider 430 is exported first divider 420 is the 4th blank signal fd4-I of fd1/N2 divided by second Integer N 2 (is 3 at this embodiment) in order to produce frequency, Q.
The 3rd divider 440, the 4th spacing frequency fd4 that second divider 430 is exported is the phase-locked input signal Sfp of fd4/N3 divided by the 3rd Integer N 3 (being 8 for example) in order to produce frequency.
Fig. 5 is an embodiment who shows the circuit structure diagram of voltage controlled oscillator 416 provided by the present invention.If utilize traditional mode with voltage controlled oscillator 416 direct controls at the 6336M hertz, again divided by 2 to produce the 3168M hertz, will expend sizable circuit area and power afterwards.Producing for fear of this problem, in the embodiment shown in this figure, is that the frequency of oscillation with voltage controlled oscillator 416 reduces by half, and pulls out the signal of doubled frequency again from its common-mode point.As shown in the figure, voltage controlled oscillator 416 comprises first to fourth differential delay unit (Differential Delay Cell) 510,520,530 and 540 of four serial connections, have positive and inverting input 501 to 504 and 505 to 508 respectively, positive and reversed-phase output 511 to 514 and 515 to 518, and common-mode point COM1 to COM4.The phase place of 511 to 514 output signals of positive output end is respectively 180 °, 225 °, 270 ° and 315 °, and the phase place of 515 to 518 output signals of reversed-phase output is respectively 0 °, 45 °, 90 ° and 135 °.Low pass filter 414 produces direct voltage and controls this voltage controlled oscillator 416.Because voltage controlled oscillator 416 can provide the eight-phase signal, therefore common-mode point COM1-COM4 can directly produce four phase signals of two frequencys multiplication (6336M hertz), be that to produce frequency respectively be 6336M hertz and phase place is respectively 0 ° to common-mode point COM1-COM4,90 °, the signal of 180 ° and 270 °, it is respectively as the 3rd positive phase signals fd3-I (+) of in-phase signal fd3-I at interval, the positive phase signals fd3-Q (+) of the 3rd interval orthogonal signalling fd3-Q, the inversion signal fd3-I (-) of the 3rd interval in-phase signal fd3-I, and the inversion signal fd3-Q (-) of the 3rd interval orthogonal signalling fd3-Q.First to fourth differential delay unit 510,520,530 and 540 internal structure are that those skilled in the art know, and for simplicity's sake, seldom do explanation at this.
In one embodiment, voltage controlled oscillator in the phase-locked loop 304 (not showing with diagram) also can use circuit structure shown in Figure 5 to reach, difference only is that the positive of second differential delay unit 502 and inverting input 512 and 516 are that incoming frequency is the positive and the inversion signal of input signal of original frequency f0 1/2nd (1980M hertz), and common-mode point COM1-COM4 is the positive phase signals f0-I (+) of the initial in-phase signal f0-I of 3960M hertz with the living frequency of changing products respectively, the positive phase signals f0-Q (+) of initial orthogonal signalling, the inversion signal f0-I (-) of initial positive phase signals f0-I, and the inversion signal f0-Q (-) of initial orthogonal signalling f0-Q.
Fig. 6 is shown in the embodiment shown in Figure 4, an embodiment of the circuit structure diagram of second divider 430 provided by the present invention.Second divider 430 shown in this figure is that four phase places are removed three-circuit.As shown in the figure, second divider 430 comprises first oscillator 610, it is made of first to the 3rd D-type latch 611 to 613, second oscillator 620, it is made of the 4th to the 6th D-type latch 621 to 623, first inverter 631 is coupled between the data input pin D of the data output end Q of the 3rd latch 613 and first latch 611, second inverter 632 is coupled between the data input pin D of the data output end Q of the 6th latch 623 and quad latch 621, and phase alignment buffer module 640, be arranged between this first and second oscillator 610 and 620, it constitutes to hex buffer 641 to 646 by first.
First and second oscillator 610 and 620 produces the 4th interval in-phase signal fd4-I and the 4th orthogonal signalling fd4-Q (the 4th spacing frequency fd4=528M hertz) at interval according to injection locking (Injection Lock) mechanism.In first oscillator 610, the input end of clock CLK of first D-latch 611 receives the first interval in-phase signal fd1-I, and the phase place of the output Q institute output signal of first to the 3rd D-type latch 611 to 613 is respectively 0 °, 60 ° and 120 °, and the output signal that the output Q of the 3rd D-type latch 613 is produced is the input D that feeds back to first D-type latch 611 by first inverter 631.The output signal of the output Q of second D-type latch 612 therefore can be as the 4th interval in-phase signal fd4-I.Similarly, in second oscillator 620, the input end of clock CLK of 4 d latch 531 receives this first interval orthogonal signalling fd1-Q, and the phase place of the output Q institute output signal of the 4th to the 6th D-type latch 621 to 623 is respectively 30 °, 90 ° and 150 °, and the output signal of the output Q of the 6th D-type latch 623 is the input D that feeds back to the 4th D-type latch 621 by second inverter 632.The output signal of the output Q of the 6th D-type latch 623 therefore can be as the 4th interval orthogonal signalling fd4-Q.Phase alignment buffer module 640 is used for guaranteeing that the 4th interval in-phase signal fd4-I can accurately aim at each other with the phase order of the 4th interval orthogonal signalling fd4-Q.
Must notice that owing to this figure presents with single-ended, and homophase, the inversion signal of each signal are to produce simultaneously in the double end converter, therefore in fact second divider 430 need not comprise first and second inverter 631 and 632.
Most of tradition is removed three-circuit all (duty cycle) distortion of serious work period, and lacks that four phase signals produce and the problem that can't export monolateral frequency mixer to.The new Miller frequency eliminator that proposes also has serious side frequency effect problem because of the coupling that is subject in the chip in order to address the above problem.Yet second divider 430 of Fig. 6 not only can provide for 50% work period, also can provide four phase signals (i.e. the 4th spacing frequency fd4) to give monolateral frequency mixer (i.e. first frequency mixer 306).The most important thing is that because this four phase signal has accurate phase relation, so the first output frequency fo1 that first frequency mixer 306 is produced does not have serious side frequency composition.
Fig. 7 shows when use second divider 430 shown in Figure 6 and when the first output frequency fo1 is chosen as the 3rd frequency f 3 (4488M hertz) the first output signal fo1-I, the energy of Q and the graph of a relation of frequency.As shown in the figure, the first output signal fo1-I, it is to be higher than more than the first frequency f1 40dB of place that the energy of Q is located in the 3rd frequency f 3 (4488M hertz).Anticipate promptly, the side frequency composition that surpasses 40dB can be suppressed.
Fig. 8 A and 8B are the embodiment of circuit structure diagram of first frequency mixer 306 of displayed map 3.Because the first output signal fo1-I that first frequency mixer 306 is produced, the frequency range of R only is the frequency range of first frequency group Group1, and therefore traditional monolateral frequency mixer can have been dealt with required.As shown in the figure, first frequency mixer 306 comprises first and second tristate buffer 810 and 820 and first and second mixting circuit 830 and 840, and wherein this first and second mixting circuit 830 and 840 is to constitute monolateral frequency mixting circuit.Must notice that the structure of monolateral frequency mixting circuit has all different possibilities, this figure only makes an example, does not make the usefulness of restriction.
It has input 802 first tristate buffer, in order to receive positive phase signals fd4-I (+) and the inversion signal fd4-I (-) (the 4th spacing frequency fd4 is the 528M hertz) of the 4th interval in-phase signal fd4-I, output 832, positive phase signals LO-I (+) and inversion signal LO-I (-) in order to output mixing in-phase signal LO-I, switch 812, it has first to the 3rd end 813 to 815, inverter 816, and direct voltage source 818, its output DC is flat.When this switch 812 switched to first end 813, second end 814 and the 3rd end 815, the mixing in-phase signal LO-I that output 832 is exported was respectively positive phase signals fd4-I (+), inversion signal fd4-I (-) and this DC level of the 4th interval in-phase signal fd4-I.Similarly, second tristate buffer 820 has input 804, in order to receive positive phase signals fd4-Q (+) and the inversion signal fd4-Q (-) of the 4th interval orthogonal signalling fd4-Q, output 834 is in order to positive phase signals LO-Q (+) and the inversion signal LO-Q (-) of output mixing orthogonal signalling LO-Q, switch 822, it has first to the 3rd end 823 to 825, inverter 826, and direct voltage source 828, it exports this DC level.When this switch 822 switched to first and second and three ends 823,824 and 825 respectively, the mixing orthogonal signalling LO-Q that output 834 is exported was respectively the 4th positive phase signals fd4-Q (+), inversion signal fd4-Q (-) and this DC level of orthogonal signalling fd4-Q at interval.
First mixting circuit 830 comprises that first to the 6th nmos pass transistor M1 to M6, first to second resistance R 1 and R2 are connected to the first constant current source I1, and first inductance L 1 is connected to direct voltage source VDD, and first and second capacitor C 1
1And C1
2Be connected to first and second capacitance switch b1 respectively
1And b1
2The grid of the first and the 4th nmos pass transistor M1 and M4 receives the positive phase signals LO-I (+) of mixing in-phase signal LO-I, and the grid of second and third nmos pass transistor M2 and M3 receives the inversion signal LO-I (-) of mixing in-phase signal LO-I.The grid of the 5th and the 6th nmos pass transistor M5 and M6 receives positive phase signals f0-I (+) and the inversion signal f0-I (-) of initial in-phase signal f0-I respectively.Similarly, second mixting circuit 840 comprises the 7th to the tenth bi-NMOS transistor M7 to M12, and the 3rd to the 4th resistance R 3 and R4 are connected to the second constant current source I2, and second inductance L 2 is connected to this direct voltage VDD, and the 3rd and the 4th capacitor C 2
1And C2
2Be connected to the 3rd and the 4th capacitance switch b2 respectively
1And b2
2The grid of the 7th and the 11 nmos pass transistor M7 and M11 receives the positive phase signals LO-Q (+) of mixing orthogonal signalling LO-Q.The grid of the 8th and the 9th nmos pass transistor M8 and M9 receives the inversion signal LO-Q (-) of mixing orthogonal signalling LO-Q.The grid of the 11 and the tenth bi-NMOS transistor M11 and M12 receives inversion signal f0-Q (-) and the positive phase signals f0-Q (+) of initial orthogonal signalling f0-Q (original frequency f0 is the 3960M hertz) respectively.First and second mixing in-phase output end 861 and 862 is exported inversion signal fo1-I (-) and the inversion signal fo1-I (+) of the first output in-phase signal fo1-I respectively.
First and second inductance L 1 and L2, first to fourth capacitor C 1
1, C1
2, C2
1And C2
2And first to fourth capacitance switch b1
1, b1
2, b2
1And b2
2Be to constitute inductance capacitance resonant cavity (LC tank) 850, with so that the first output signal fo1-I, the energy of Q can optionally amplify.The first output signal fo1-I that is exported when first frequency mixer 306, when the first output frequency fo1 of Q was first frequency f1 (3432M hertz), second frequency f2 (3960M hertz) and the 3rd frequency f 3 (4488M hertz), the on off state of first to fourth capacitance switch was respectively (b1
1, b1
2, b2
1, b2
2)=(1,1,1,1), (1,0,1,0) or (0,1,0,1) and (0,0,0,0), wherein 0 and 1 is to represent respectively to cut off and conducting.Thus, thus frequency reduces the effect that the institute's quality factor that causes reduction causes gaining and selectivity is low can be remedied.Because the structure of first and second mixting circuit 830 and 840 is to belong to known technology, those skilled in the art at this for simplicity's sake, seldom do explanation when being familiar with its operation principles.
Similar with first frequency mixer 306, because the 3rd output signal fo3-I that three-mixer 310 is produced, the frequency range of Q only is the frequency range of the 4th group of frequencies Group4, and therefore traditional monolateral frequency mixer can have been dealt with required.The circuit structure diagram of Fig. 8 also can be used to realize three-mixer 310.Difference only is that three-mixer 310 does not need first and second tristate buffer 810 and 820.
Fig. 9 is an embodiment of circuit structure diagram who shows second frequency mixer 308 of Fig. 3 provided by the present invention.Up to about 6G hertz, therefore second frequency mixer 308 must have enough selectivity to reduce the side frequency effect because the frequency output area of second frequency mixer 308 includes second, third and the 5th group of frequencies Group2, Group3 and Group5.Utilize traditional in parallel or series connection spike (Peaking) technology,, be difficult to reach the function of high-gain and high selectivity though wide and flat response can be provided.And use inductance capacitance resonant cavity (LC tank) separately though can reach wideband in the mode of switch-capacitor, yet along with frequency reduces, the quality factor of inductance capacitance resonant cavity (Quality Factor) decreases, and is inconjunction with gain of inductance capacitance resonant cavity and selectivity and all can reduces.For head it off, in the embodiment shown in this figure, second frequency mixer 308 is to utilize the inductance capacitance resonant cavity of two serial connections to realize the requirement of wideband.
As shown in the figure, second frequency mixer 308 comprises monolateral frequency mixting circuit 900 and output circuit 910.Monolateral frequency mixting circuit 900 only is not have first and second tristate buffer 810 and 820 with first frequency mixer, 306 differences of Fig. 8, and inductance capacitance resonant cavity 850 changes inductance capacitance resonant cavity 850 ' into.Inductance capacitance sense resonant cavity 850 ' and 850 difference are first to fourth capacitor C 1
1, C1
2, C2
1And C2
2Be reduced to first and second capacitor C 1 and C2, and first to fourth capacitance switch b1
1, b1
2, b2
1And b2
2Be reduced to first and second capacitance switch b1 and b2.Output circuit 910 comprises first and second output nmos transistor mo1 and mo2, inductance capacitance resonant cavity 950 and the 3rd constant current source I 3.Also must notice that the structure of monolateral frequency mixting circuit 900 has all different possibilities, this figure only makes an example, does not make the usefulness of restriction.
The source electrode of first and second output nmos transistor mo1 and mo2 is to be connected to the 3rd constant current source I3, its grid is connected to the mixing of being exported from monolateral frequency mixting circuit 900 respectively and exports positive phase signals fo2-I (+) ' and mixing output inversion signal fo2-I (-) ', with and drain electrode export positive and the inversion signal fo2-I (+) and the fo2-I (-) of the second output in-phase signal respectively.Inductance capacitance resonant cavity 950 similar comprise first and second outputting inductance Lo1 and Lo2 in inductance capacitance resonant cavity 850 ', and first and second output capacitance Co1 and Co2 are connected to first and second output capacitance switch bo1 and bo2 respectively.Inductance capacitance resonant cavity 950 optionally amplifies time to produce positive and the inversion signal fo2-I (+) and the fo2-I (-) of the second output in-phase signal once again in order to exporting positive phase signals fo2-I (+) ' and mixing output inversion signal fo2-I (-) ' through the mixing of inductance capacitance resonant cavity 850 ' selected property amplification.
First and second capacitance switch b1 of inductance capacitance resonant cavity 850 ' and conducting or the cut-out of b2, and first and second output capacitance switch bo1 in the inductance capacitance resonant cavity 950 and conducting or the cut-out of bo2 programmed, in order to producing enough big and flat gain in the frequency range of institute's desire output.In one embodiment, when the second output frequency fo2 belonged to the 5th group of frequencies Group5, the 3rd group of frequencies Group3 and second frequency group Group2 respectively, conducting or the dissengaged positions of first and second capacitance switch b1 and b2 and first and second output capacitance bo1 and bo2 were respectively (b1, b2, bo1, bo2)=(0,0,0,0), (1,1,0,0) or (0,0,1,1) and (1,1,1,1), wherein " 0 " expression is cut off and " 1 " expression conducting.Utilizing under the embodiment shown in this figure, in the frequency range of each group of frequencies (the 5th group of frequencies Group5, the 3rd group of frequencies Group3 or second frequency group Group2), change in gain amount (gap of maximum gain and least gain) only is 3dB, and in the frequency range of the group of frequencies of not wanting to export, can reach the decay of per ten times-80dB.
Figure 10 A, 10B and 10C are presented to utilize second frequency mixer shown in Figure 9 308 times, when the second output frequency fo2 belongs to the 5th group of frequencies Group5, the 3rd group of frequencies Group 3 and second frequency group Group2, two inductance capacitance resonant cavities 850 and the 950 frequency response schematic diagrames that have respectively.As shown in the figure, the response peak of two resonant cavities is closer to each other along with the reduction of frequency, and frequency reduces institute's quality factor that causes and reduces and gain and effect that selectivity is low thereby can be remedied.
Figure 11 is presented among the embodiment of second frequency mixer 308 of application drawing 9, when the second output frequency fo2 is chosen as the centre frequency (i.e. the 8th frequency f 8=7128M hertz) of the 3rd Group3 of group, the second output signal fo2-I, the graph of a relation of R energy and frequency.As shown in the figure, the energy of the second output frequency fo2 is located to be higher than other side frequency (spurs) in the 8th frequency (7128M hertz) and is reached more than the 35dB.
Two phase-locked loops of 300 needs of frequency synthesizer of the present invention can produce the first to the 14 frequency f 1 to f14, can't increase the burden of additional hardware compared to the prior art.In addition, because in monolateral frequency mixer, all incoming frequencies all are four phase signals, traditional voltage controlled oscillator and divider be can't satisfy required, yet the present invention has also overcome the difficulty in the design.In addition, except suitably using the frequency multiplication skill to reduce the power consumption of two phase-locked loops 304 and 410, the present invention and proposition can produce four phase places of precise phase and remove three-circuit as second divider 430, thereby reduce by the first output signal fo1-I that first frequency mixer 306 is exported, the side frequency composition of Q.In addition, the present invention also proposes to comprise two capacitance resistance resonant cavities 850 ' and 950 and can contain second frequency mixer 308 of broad range.In addition, the most important thing is, because the single order side frequency that second and third frequency mixer 308 and 310 smears produce all can drop on outside the whole super broadband system frequency band, therefore all frequencies of being produced of frequency synthesizer 300 of the present invention can be releived because of being connected in series the first side frequency accumulation that causes to three-mixer 306 to 310.Can reach 3ns following (not showing) switching time of frequency synthesizer 300 of the present invention with diagram.
Table 1 is the comparison that shows frequency synthesizer 300 of the present invention and given frequency synthesizer.Table as can be known thus, the present invention can use 0.18 μ m CMOS processing procedure to make, and only need use two phase-locked loops, and power consumption is 160mW only, and can produce 14 frequency bands that known technology can't produce, the number of frequency bands (maximum number is seven) that this is higher than known technology far away and is produced.In addition, the present invention also has side frequency and suppresses to be higher than 35dB, and the advantage of exportable four phase signals.
Table 1
| Known technology [1] | Known technology [2] | Known technology [3] | Known technology [4] | The present invention | |
| Processing procedure | 0.18μm CMOS | 0.18μm CMOS | 0.18μm CMOS | 0.25 μ m SiGe CMOS | 0.18μm CMOS |
| The phase-locked loop number | 2 | 0 | 1 | 2 | 2 |
| (chip external signal) | |||||
| Produce number of frequency bands | 7 | 3 | 7 | 3 | 14 |
| Side frequency suppresses | ＞37dB | ＞15dB | There is not explanation | ＞35dB | ＞35dB |
| Could produce four phase place output signals | Not | Not | Can | Can | Can |
| Power loss | 48mW | 18mW | 178mW | 73mW | 160mW |
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (34)
1. frequency combining method, in order to produce a plurality of frequencies of the super wideband of multi-band orthogonal frequency division multiplex (MUX), this equifrequent comprises the first to the 14 frequency from low to high, and wantonly two these adjacent equifrequents are separated by the basic interval frequency are arranged, and this method comprises:
This equifrequent is divided into first to the 5th group of frequencies, comprises this first to the 3rd frequency, the 4th to the 6th frequency, the 7th to the 9th frequency and the 13 to 14 frequency respectively;
Produce this first frequency group;
This first frequency group is carried out mixing program to produce this second and third and five group of frequencies; And
The 5th group of frequencies is carried out the mixing program to produce the 4th group of frequencies.
2. frequency combining method according to claim 1, the step that wherein produces the first frequency group comprises:
Produce this second frequency;
Produce the 4th spacing frequency, wherein the 4th spacing frequency equals this basic interval frequency; And
This second frequency and the 4th spacing frequency are carried out selectivity mixing program to produce this first frequency group.
3. frequency combining method according to claim 1, wherein will to the first frequency group carry out the mixing program with produce this second and third and the step of five group of frequencies comprise:
Produce first to the 3rd spacing frequency, wherein this first to the 3rd spacing frequency is the integral multiple of this basic interval frequency; And
This first frequency group and this first to the 3rd spacing frequency are carried out Frequency mixing processing to produce this second and third and five group of frequencies respectively.
4. frequency combining method according to claim 3, wherein this first to the 3rd spacing frequency is respectively three times, six times and twelvefold of this basic interval frequency.
5. frequency combining method according to claim 1, wherein the 5th group of frequencies is carried out the mixing program and comprise with the step that produces the 4th group of frequencies:
Produce first spacing frequency, wherein this first spacing frequency integral multiple that is this basic interval frequency; And
The 5th group of frequencies and this first spacing frequency are carried out mixing to produce the 4th group of frequencies.
6. frequency combining method according to claim 4, wherein this first spacing frequency is respectively three times of this basic interval frequency.
7. frequency combining method, in order to produce a plurality of frequencies of the super wideband of multi-band orthogonal frequency division multiplex (MUX), this equifrequent comprises the first to the 14 frequency from low to high, and wantonly two these adjacent equifrequents are separated by the basic interval frequency are arranged, and this method comprises:
Produce first to the 3rd spacing frequency from low to high, wherein this first to the 3rd spacing frequency be the integral multiple of this basic interval frequency, and is the interval output frequency one of in the middle of selecting;
One of produce in the middle of this first to the 3rd frequency is first output frequency;
This first output frequency and this interval output frequency are carried out Frequency mixing processing, and in order to produce second output frequency, wherein this second output frequency is one of in the middle of the 4th to the 9th frequency, the 13 to 14 frequency and the 15 frequency; And
With this second output frequency and this first at interval output frequency carry out Frequency mixing processing and produce the 3rd output frequency, wherein the 3rd output frequency is one of in the middle of the tenth to 12 frequency.
8. frequency combining method according to claim 7, wherein this first to the 3rd spacing frequency is respectively three times, six times and twelvefold of this basic interval frequency.
9. frequency combining method according to claim 7, one of wherein producing in the middle of this first to the 3rd frequency is that the step of first output frequency comprises:
Produce this second frequency;
Produce the 4th spacing frequency, wherein the 4th spacing frequency equals this basic interval frequency; And
This second frequency and the 4th spacing frequency are carried out the selectivity Frequency mixing processing, with produce this first, second or the 3rd frequency for this first output frequency.
10. frequency combining method according to claim 7, the step that wherein produces this second frequency is to utilize the phase-locked loop.
11. frequency combining method according to claim 7, wherein this first to the 3rd spacing frequency is respectively three times, six times and twelvefold of this basic interval frequency.
12. frequency combining method according to claim 7, the step that wherein produces this first to the 3rd spacing frequency comprises:
Produce this second and third spacing frequency; And
With this second spacing frequency divided by first integer to produce this first spacing frequency.
13. frequency combining method according to claim 12, the step that wherein produces this second and third spacing frequency is to use the eight-phase oscillator, in order to produce this second and third spacing frequency of four phase places.
14. frequency combining method according to claim 9,
The step that wherein produces this first to the 3rd spacing frequency comprises:
Produce this second and third spacing frequency; And with this second spacing frequency divided by first integer to produce this first at interval frequently; And
The step that wherein produces the 4th spacing frequency comprises this first spacing frequency divided by second integer to produce the 4th spacing frequency.
15. frequency combining method according to claim 12, wherein this first integer is two.
16. frequency combining method according to claim 14, wherein this first and second integer is respectively two and three.
17. frequency combining method according to claim 9, the step of wherein this second frequency and the 4th spacing frequency being carried out the selectivity Frequency mixing processing is to utilize monolateral frequency mixer.
18. frequency combining method according to claim 5, wherein the step that this first output frequency and this interval output frequency are carried out Frequency mixing processing is to utilize monolateral frequency mixer.
19. frequency combining method according to claim 5, wherein with this second output frequency and this first at interval the output frequency step of carrying out Frequency mixing processing be to utilize monolateral frequency mixer.
20. a frequency synthesizer, in order to produce a plurality of frequencies of the super wideband of multi-band orthogonal frequency division multiplex (MUX), this equifrequent comprises the first to the 14 frequency from low to high, and wantonly two these adjacent equifrequents are separated by the basic interval frequency is arranged, and this frequency synthesizer comprises:
First phase-locked loop and first frequency mixer, in order to produce this first frequency group, wherein this first frequency group comprises this first to the 3rd frequency;
Second frequency mixer, in order to this first frequency group is carried out mixing program to produce second and third and five group of frequencies, wherein this second and third and five group of frequencies comprise the 4th to the 6th frequency, the 7th to the 9th frequency respectively, and the 13 and 14 frequencies; And
Three-mixer in order to according to the 5th group of frequencies, and is carried out the mixing program to produce the 4th group of frequencies, and wherein the 4th group of frequencies comprises the tenth to 12 frequency.
21. frequency synthesizer according to claim 20 also comprises the spacing frequency generator, equals this basic interval frequency in order to produce the 4th spacing frequency; And wherein this first phase-locked loop is in order to producing this second frequency, and this first frequency mixer carries out Frequency mixing processing to produce this first frequency group with this second frequency and the 4th spacing frequency.
22. frequency synthesizer according to claim 20 also comprises the spacing frequency generator, in order to produce first to the 3rd spacing frequency, wherein this first to the 3rd spacing frequency is the integral multiple of this basic interval frequency; And wherein this second frequency mixer carries out Frequency mixing processing to produce this second and third and five group of frequencies respectively with this first frequency group and this first to the 3rd spacing frequency.
23. frequency synthesizer according to claim 20, also comprise the spacing frequency generator, in order to produce first spacing frequency, this first spacing frequency integral multiple that is this basic interval frequency wherein, and wherein this three-mixer carries out Frequency mixing processing to produce the 4th group of frequencies with the 5th group of frequencies and this first spacing frequency.
24. frequency synthesizer according to claim 21,
Wherein this spacing frequency generator also produces first to the 3rd spacing frequency, and wherein this first to the 3rd spacing frequency is the integral multiple of this basic interval frequency;
Wherein this second frequency mixer carries out Frequency mixing processing to produce this second and third and five group of frequencies respectively with this first frequency group and this first to the 3rd spacing frequency; And
Wherein this three-mixer carries out Frequency mixing processing to produce the 4th group of frequencies with the 5th group of frequencies and this first spacing frequency.
25. a frequency synthesizer, in order to the method for a plurality of frequencies of producing the super wideband of multi-band orthogonal frequency division multiplex (MUX), this equifrequent comprises the first to the 14 frequency from low to high, and wantonly two these adjacent equifrequents are separated by the basic interval frequency is arranged, and this frequency synthesizer comprises:
First phase-locked loop, in order to produce initialize signal, wherein the frequency of this initialize signal is to equal this second frequency;
The spacing frequency generator, in order to produce frequency first to the 3rd blank signal from low to high, wherein the frequency of this first to the 3rd blank signal is the integral multiple that equals this basic interval frequency, and produce the 4th spacing frequency, wherein the frequency of the 4th blank signal equals this basic interval frequency, and one of optionally exports in the middle of this first to the 3rd blank signal and to be output signal at interval;
First frequency mixer in order to this initialize signal and the 4th blank signal are carried out optionally Frequency mixing processing, and produces first output signal, and wherein first output signal frequency is one of in the middle of this first to the 3rd frequency;
Second frequency mixer, in order to this first output signal and this interval output signal are carried out Frequency mixing processing, and produce second output signal, wherein this second output signal frequency is one of in the middle of the 4th to the 9th frequency, the 13 and the 14 frequency and the 15 frequency; And
Three-mixer in order to this second output signal and this first blank signal are carried out Frequency mixing processing, and produces the 3rd output signal, and wherein the 3rd output signal frequency one of equals in the middle of the tenth to the 12 frequency.
26. frequency synthesizer according to claim 25 also comprises multiplexer, in order to receiving this first to the 3rd output signal, and is final output signal one of in the middle of the output optionally.
27. frequency synthesizer according to claim 25, wherein this first to the 3rd spacing frequency is respectively three times, six times and twelvefold of this basic interval frequency.
28. frequency synthesizer according to claim 25, wherein this spacing frequency generator comprises:
Second phase-locked loop, it comprises:
Phase-frequency detector is in order to receive reference signal and phase-locked input signal;
Voltage controlled oscillator is in order to produce this second and third blank signal;
First divider, in order to the frequency of this second blank signal divided by first integer to produce this first blank signal;
Second divider, in order to the frequency of this first blank signal divided by second integer to produce the 4th blank signal; And
The 3rd divider, in order to the frequency of the 4th blank signal divided by the 3rd integer to produce this phase-locked input signal; And
The multiplexer module in order to receiving this first to the 3rd blank signal, and one of is optionally exported in the middle of this first to the 3rd blank signal and to be this interval output signal.
29. frequency synthesizer according to claim 28, wherein this voltage controlled oscillator comprises:
First to fourth differential delay unit, serial connection has positive and inverting input respectively each other, positive and reversed-phase output, and common-mode point,
Wherein positive and the reversed-phase output one of in the middle of these differential delay unit receives positive and rp input signal, wherein the frequency of this positive and rp input signal is the frequency that equals this second blank signal, this positive of each these differential delay unit and reversed-phase output are the two phase signals that produces in the middle of the eight-phase signal of this second blank signal, and this common-mode point of each this differential delay unit is a phase signal one of in the middle of four phase signals of output the 3rd blank signal.
30. frequency synthesizer according to claim 25, wherein this first phase-locked loop comprises voltage controlled oscillator, and wherein this voltage controlled oscillator comprises:
First to fourth differential delay unit, serial connection has positive and inverting input respectively each other, positive and reversed-phase output, and common-mode point,
Positive one of in the middle of these differential delay unit and the reversed-phase output positive and the inversion signal that are receiving inputted signal wherein, wherein the frequency of this input signal is to equal 1/2nd of this second frequency, this positive of each these differential delay unit and reversed-phase output are the two phase signals that produces in the middle of the eight-phase signal of this input signal, and this common-mode point of each this differential delay unit is a phase signal one of in the middle of four phase signals of this initialize signal of output.
31. frequency synthesizer according to claim 28, wherein this first to the 3rd integer is respectively two, three and eight.
32. frequency synthesizer according to claim 31, wherein this second divider comprises:
First oscillator comprises first to the 3rd D-type latch of serial connection mutually, and wherein the clock end of each this D-type latch receives the in-phase signal of this first blank signal, and the output of this second D-type latch produces the in-phase signal of the 4th blank signal;
Second oscillator comprises the 3rd to the 6th D-type latch of serial connection mutually, and wherein the clock end of each this D-type latch receives the orthogonal signalling of this first blank signal, and the output of the 6th D-type latch produces the orthogonal signalling of the 4th blank signal; And
The phase alignment buffer module, it is coupled between this first and second oscillator and comprises first to hex buffer, in order to the phase order of the orthogonal signalling of the in-phase signal of aiming at the 4th blank signal and the 4th blank signal.
33. frequency synthesizer according to claim 25, wherein this first, second comprise monolateral frequency mixer respectively to three-mixer.
34. frequency synthesizer according to claim 25, wherein this second frequency mixer comprises:
Monolateral frequency mixting circuit in order to this first output signal and this interval output signal are carried out Frequency mixing processing, and produces the positive and the inversion signal of output signal; And
Output circuit, it comprises:
Constant current source;
The inductance capacitance resonant cavity, it comprises first and second outputting inductance, first and second output capacitance, and first and second output capacitance switch is connected to this first and second output capacitance; And
First and second transistor, its grid receive the positive and the inversion signal of this output signal respectively, and its first source/drain electrode connects this inductance capacitance resonant cavity and exports the anti-phase and positive phase signals of this second output signal respectively.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101820283A (en) * | 2010-04-16 | 2010-09-01 | 上海复高软件开发有限公司 | Frequency synthesis device with digital added analogue framework |
| CN101505151B (en) * | 2009-03-06 | 2011-01-26 | 中国科学院微电子研究所 | Full-band frequency generator |
| CN102957446A (en) * | 2011-08-25 | 2013-03-06 | 立积电子股份有限公司 | Radio frequency circuit and mixer |
| CN110968146A (en) * | 2019-12-12 | 2020-04-07 | 深圳星河半导体技术有限公司 | Charge pump circuit for phase-locked loop |
| CN113630132A (en) * | 2018-08-03 | 2021-11-09 | 华为技术有限公司 | Multi-phase signal generation |
-
2006
- 2006-08-18 CN CN2006101155433A patent/CN101127527B/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101505151B (en) * | 2009-03-06 | 2011-01-26 | 中国科学院微电子研究所 | Full-band frequency generator |
| CN101820283A (en) * | 2010-04-16 | 2010-09-01 | 上海复高软件开发有限公司 | Frequency synthesis device with digital added analogue framework |
| CN102957446A (en) * | 2011-08-25 | 2013-03-06 | 立积电子股份有限公司 | Radio frequency circuit and mixer |
| CN113630132A (en) * | 2018-08-03 | 2021-11-09 | 华为技术有限公司 | Multi-phase signal generation |
| CN113630132B (en) * | 2018-08-03 | 2022-03-29 | 华为技术有限公司 | Multi-phase signal generation |
| US11782475B2 (en) | 2018-08-03 | 2023-10-10 | Huawei Technologies Co., Ltd. | Multi-phase signal generation |
| CN110968146A (en) * | 2019-12-12 | 2020-04-07 | 深圳星河半导体技术有限公司 | Charge pump circuit for phase-locked loop |
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| CN101127527B (en) | 2011-08-24 |
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