CN101127507A - A method and device for frequency control based on calibration algorithm - Google Patents
A method and device for frequency control based on calibration algorithm Download PDFInfo
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- CN101127507A CN101127507A CNA2007100461351A CN200710046135A CN101127507A CN 101127507 A CN101127507 A CN 101127507A CN A2007100461351 A CNA2007100461351 A CN A2007100461351A CN 200710046135 A CN200710046135 A CN 200710046135A CN 101127507 A CN101127507 A CN 101127507A
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Abstract
The utility model relates to a method and a device for frequency control using calibration algorithm, belonging to the voltage-controlled oscillator circuit design field. The utility model comprises the following steps: 1, the output frequency of the voltage-controlled oscillator and the reference frequency of a PLL are compared using the calibration algorithm, a resistor is selected according to the result; 2, the output frequency of the voltage controlled oscillator is fine-tuned by the control voltage. The utility model at least comprises a third MOS tube, a fourth MOS tube, a first current source, a second current source, a differential input end, a differential output end, a power supply, a grounding end, a first resistor array, and a second resistor array. The utility model has advantages that the parameter of the voltage-controlled oscillator circuit is adjusted to a proper value when the process condition is changed, and the phase noise is not affected.
Description
Technical field
The present invention relates to voltage-controlled oscillator circuit design field, particularly relate to a kind of circuit design method and device that utilizes calibration algorithm to realize FREQUENCY CONTROL.
Background technology
The frequency of oscillator can be by voltage control, and such circuit is called a voltage controlled oscillator.Two kinds of structures of the general employing of voltage controlled oscillator: LC mode of resonance voltage controlled oscillator and annular voltage controlled oscillator.LC mode of resonance voltage controlled oscillator utilizes the parallel resonance of inductance and electric capacity to produce frequency
Sine wave, and the capacitance C by control voltage-regulation variable capacitance diode, thus realize adjusting to frequency.The advantage of LC mode of resonance voltage controlled oscillator is that output voltage swing is big, and phase noise is low; The shortcoming of LC mode of resonance voltage controlled oscillator is that current drain is big, and tuning range is little, and area is bigger owing to used the inductance integrated inductor.The annular voltage controlled oscillator implementation has multiple, but its principle basically identical, generally being joined end to end successively by the odd number delay unit forms, if the transmission delay of every grade (each delay unit) is Td, and output frequency f=1/ (2*N*Td) then, N is a progression.Annular voltage controlled oscillator is realized adjusting to frequency by the transmission delay Td that regulates every grade of control voltage-regulation.The advantage of annular voltage controlled oscillator is simple in structure, and frequency tuning range is big, and current drain is little, and area is little; The shortcoming of annular voltage controlled oscillator is the frequency-selecting poor-performing, and frequency accuracy is not high, the phase noise height, thus limited its range of application.
Voltage controlled oscillator is an important module in the phase-locked loop systems, can adjust its reference frequency output by the size of adjusting control voltage.When phase-locked loop systems is locked in a certain Frequency point, require the output frequency of voltage controlled oscillator also should be on a certain Frequency point.But the output frequency with process deviation and variations in temperature voltage-controlled oscillator circuit parameter can produce great changes.In order to guarantee that phase-locked loop can both be locked in the frequency band or the frequency of appointment under various process conditions, voltage controlled oscillator need cover very big reference frequency output.In the prior art, this just needs voltage controlled oscillator to control voltage to the value big (Kvco=Δ f/ Δ V) of the gain Kvco of output frequency, yet big Kvco value can influence the phase noise that phase-locked loop is finally exported.And, because the control voltage adjusting range is limited,, then output frequency can't be adjusted on the desired value if exceeded voltage adjusting range.With the voltage controlled oscillator that goes in ring is example, and the transmission delay that annular voltage controlled oscillator is every grade is Td=R*C, and output frequency is f=1/ (2*N*Td).
Delay unit can adopt single-ended structure or differential configuration.Annular voltage controlled oscillator is should be by progression minimum to be the loop that 3 delay unit is formed.Fig. 1 is the structural representation of typical annular voltage controlled oscillator.As shown in Figure 1, typical annular voltage controlled oscillator forms by the delay unit of 3 grades of differential configurations is end to end successively.The input of described delay unit be (Vinp, Vinn), output be (Voutn, Voutp).
Fig. 2 is the structural representation of typical annular voltage controlled oscillator equivalent electric circuit.As shown in Figure 2, R is the equivalent resistance of every grade of delay unit, and C is the equivalent capacity of every grade of delay unit.
Fig. 3 is the circuit diagram of prior art delay unit.Delay unit can adopt single-ended or differential configuration, and prior art delay unit circuit diagram as shown in Figure 3 is a differential configuration delay circuit commonly used.Vinp and Vinn are the difference input; Voutn and Voutp are difference output; M1 is first metal-oxide-semiconductor, and M2 is second metal-oxide-semiconductor, and described M1 and M2 are the load resistance that is connected into the diode form; M3 is the 3rd metal-oxide-semiconductor, and M4 is the 4th a metal-oxide-semiconductor reason, and described M3 and M4 are right for the interactive mode coupling that negative resistance is provided; M5 is the 5th metal-oxide-semiconductor, and M6 is the 6th metal-oxide-semiconductor, and described M5 and M6 are the input amplifier tube; Vdd is a power supply; Gnd is an earth terminal; I1 is first current source, and I2 is second current source.Described friendship M3, M4 produces negative resistance-1/gm1, and described M1, M2 are as load, and resistance is 1/gm2.Described M3, negative resistance-1/gm1 and described M1 that M4 produces, the load 1/gm2 parallel connection that M2 produces is as the load resistance of output.Because the value of gm (mutual conductance) is relevant with factors such as technology, temperature, must rely on control voltage to adjust gm.Therefore by formula C=CoxWL (wherein Cox is a unit are gate oxide electric capacity, and W is the wide of metal-oxide-semiconductor, and L is the length of metal-oxide-semiconductor), when the gm of metal-oxide-semiconductor being adjusted, certainly will influences the capacitance of this node, thereby cause the variation of two parameters.By
The variable quantity of gm also will influence the variation of output frequency greatly, and this will influence circuit performance greatly.For example, changed 10% as gm, f also will change 10%, and for radio band, f changes 10% variable quantity that the hundreds of megahertz is arranged.
In sum, owing to do not have calibration algorithm usually in the technology now, and only can adjust reference frequency output by control voltage, and therefore need be that great value is adjusted in the voltage controlled oscillator gain usually with the adjusting range of control voltage, this will greatly influence phase noise.Limited by related process, circuit parameter R, the C of annular voltage controlled oscillator can not accomplish not only little but also accurate, limited the output frequency size of annular voltage controlled oscillator.Therefore, all can be locked in a certain frequency under various conditions in order to make phase-locked loop, and not influence phase noise, even the voltage controlled oscillator that just must guarantee to go in ring still can arrive suitable value with the parameter adjustment of voltage-controlled oscillator circuit when process conditions change.
Summary of the invention
In order under the situation that does not influence phase noise, to realize the control of the output frequency of voltage controlled oscillator, propose a kind of method and device that utilizes calibration algorithm to realize FREQUENCY CONTROL, can effectively utilize calibration algorithm the output frequency of voltage controlled oscillator is adjusted in the adjusting range of control voltage.
The present invention includes following steps: step 1, utilize calibration algorithm, by the output frequency of voltage controlled oscillator and the reference frequency of phase-locked loop are compared, according to comparative result resistance is selected, make every grade transmission delay approaching with desired value as far as possible, thereby make the output frequency of voltage controlled oscillator be arrived in the adjusting range of control voltage by coarse adjustment; Step 2 is finely tuned the output frequency of voltage controlled oscillator by control voltage then, thereby phase-locked loop can be locked on a certain Frequency point under various conditions.
Described step 1 comprises further: step 1.1 at first compares the output frequency of voltage controlled oscillator and the reference frequency of phase-locked loop; Step 1.2 is selected R according to described comparative result, promptly allows Td reach desired value, finishes the coarse adjustment of frequency.
The implementation procedure of described calibration algorithm is as follows: the voltage controlled oscillator output frequency is through behind the frequency division, compares with the reference frequency of phase-locked loop; If reference frequency less than phase-locked loop, then reduce the resistance of electric resistance array, increase the voltage controlled oscillator output frequency, if reference frequency greater than phase-locked loop, then increase the resistance of electric resistance array, reduce the voltage controlled oscillator output frequency, if the gap of the reference frequency of voltage controlled oscillator output frequency and phase-locked loop within arithmetic accuracy, then relatively finishes; Otherwise carry out once more relatively, all finish until comparing step number
Structure of the present invention comprises the 3rd metal-oxide-semiconductor (M5) at least, the 4th metal-oxide-semiconductor (M6), first current source (I1), second current source (I2), differential input end (Vinp, Vinn), difference output end (Voutn, Voutp), power supply (Vdd), earth terminal (gnd), it is characterized in that also comprising first electric resistance array (Rn1) and second electric resistance array (Rn2), described first electric resistance array (Rn1) and second electric resistance array (Rn2) are together in series in parallel with the negative resistance that the 3rd metal-oxide-semiconductor (M3) and the 4th metal-oxide-semiconductor (M4) are formed by connecting as load resistance, and (Vinp Vinn) connects with output.
Described electric resistance array comprises regulates resistance (R0), first resistance (R1), second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9), the tenth resistance (R10), the 11 resistance (R11), the 12 resistance (R12), the 13 resistance (R13), the 14 resistance (R14), the 15 resistance (R15); Gating switch (S0), first gating switch (S1), second gating switch (S2), the 3rd gating switch (S3), the 4th gating switch (S4), the 5th gating switch (S5), the 6th gating switch (S6), the 7th gating switch (S7), the 8th gating switch (S8), the 9th gating switch (S9), the tenth gating switch (S10), the 11 gating switch (S11), the 12 gating switch (S12), the 13 gating switch (S13), the 14 gating switch (S14), the 15 gating switch (S15); The corresponding gating switch of each resistance, described gating switch is controlled the gating of this resistance, and described electric resistance array at every turn can only switch of gating.
The gating of described electric resistance array gating switch determines by control bit, and described control bit is directly by the output frequency of voltage controlled oscillator and the comparative result decision of the reference frequency of ring mutually of contracting.
The span of described control bit number is 2～6, and the best value of described control bit number is 4.
The resistance number of described control bit number decision electric resistance array.
When the control bit number was 2, the resistance number of electric resistance array was 4; When the control bit number was 3, the resistance number of electric resistance array was 8; When the control bit number was 4, the resistance number of electric resistance array was 16; When the control bit number was 5, the resistance number of electric resistance array was 32; When the control bit number was 6, the resistance number of electric resistance array was 64.
The present invention has only increased, and the logic control circuit of electric resistance array, control bit and gating switch all can be integrated in chip internal, need not any external devices, and cost simple in structure is low; The present invention adopts calibration algorithm, guarantees the pressuring controlling oscillator frequency tuning range, and does not influence phase noise; The present invention replaces the metal-oxide-semiconductor of the load resistance of prior art with electric resistance array, can formulate the variable quantity of step number and each step electric resistance array resistance according to the deviation range of electric resistance array resistance under required required precision control voltage range and the various condition.
Description of drawings
Fig. 1 is the structural representation of typical annular voltage controlled oscillator;
Fig. 2 is the structural representation of typical annular voltage controlled oscillator equivalent electric circuit;
Fig. 3 is the circuit diagram of prior art delay unit;
Fig. 4 is a flow chart of steps of the present invention;
Fig. 5 is the circuit diagram of electric resistance array of the present invention;
Fig. 6 is a calibration algorithm schematic flow sheet of the present invention;
Fig. 7 is the decoding table of comparisons of control bit of the present invention and resistance gating switch;
Fig. 8 is the circuit diagram of delay unit of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is elaborated.
Fig. 4 is a flow chart of steps of the present invention.As shown in Figure 4, the step of the inventive method comprises:
Step 1, utilize calibration algorithm, compare, resistance is selected according to comparative result by output frequency and reference frequency with voltage controlled oscillator, make every grade transmission delay approaching with desired value as far as possible, thereby make the voltage controlled oscillator output frequency be arrived in the adjusting range of control voltage by coarse adjustment;
Step 2 is finely tuned the voltage controlled oscillator output frequency by control voltage then, thereby phase-locked loop can be locked on a certain Frequency point under various conditions.
Further, step 1 also comprises the steps:
Step 1.1, at first output frequency and the reference frequency with voltage controlled oscillator compares;
Step 1.2 is selected R according to described comparative result, promptly allows Td reach desired value, finishes the coarse adjustment of frequency.
Fig. 5 is an electric resistance array circuit diagram of the present invention.As shown in Figure 5, R1, R2......R15 are the resistance that resistance equates, the big I of regulating resistance R 0 value is provided with according to actual needs, and each resistance size changes required precision by each step of circuit and determines; S0, S1......S15 are the gating switch of each resistance correspondence.Synchronization has only a switch to be in conducting state, and the gating of different switches has determined the resistance size of place in circuit.If S0 is open-minded, the equivalent resistance of electric resistance array of the present invention is R0; If S1 is open-minded, if the equivalent resistance of electric resistance array of the present invention is that R0+R1...... S15 is open-minded, the equivalent resistance of electric resistance array of the present invention is R0+R1+R2+R3+R4+R5+R6+R7+R8+R9+R10+R11+R12+R13+R14+R15.
Fig. 6 is the decoding table of comparisons of control bit of the present invention and resistance gating switch.As shown in Figure 6, left column is a control bit, is determined by the reference frequency of phase-locked loop and the comparative result of locking frequency, produces the switching gate signal by 4-16 decoding; The switch of gating is classified on the right side as, at every turn can only switch of gating, and by the numerical value decision of control bit.As shown in Figure 6, when control bit is 0000, gating switch S0; When control bit is 0001, when gating switch S1...... is 1111 when control bit, gating switch S15.
Fig. 7 is a calibration algorithm schematic flow sheet of the present invention.Calibration algorithm of the present invention adopts dichotomy, and initial value is made as 1000, and then divider ratio is 1000.It is 1V that initial condition when calibration algorithm of the present invention begins is defaulted as control voltage, and control bit is 1000, i.e. switch S 8 gatings.As shown in Figure 7, the course of work of calibration algorithm is: voltage controlled oscillator output frequency f through 1000 frequency divisions after for f '.F ' is compared with the reference frequency of phase-locked loop,, increase f if f ' then reduces R (then the control bit redirect is 0100, i.e. the S7 gating) less than the reference frequency of phase-locked loop; If f ', then increases R (then control position redirect is 1100, i.e. the S12 gating) greater than the reference frequency of phase-locked loop, reduce f; If the gap of the reference frequency of f ' and phase-locked loop within arithmetic accuracy, then relatively finishes (being that calibration algorithm points to end).Otherwise carry out once more relatively, carry out once more more still according to the voltage controlled oscillator output frequency behind frequency division value and the reference frequency of phase-locked loop compare.If the value of voltage controlled oscillator output frequency behind frequency division then jumps to next stage left greater than the reference frequency of phase-locked loop; If the value of voltage controlled oscillator output frequency behind frequency division then jumps to next stage to the right less than the reference frequency of phase-locked loop; All finish until comparing step number.Can formulate the variable quantity of step number and each step electric resistance array resistance according to the deviation range of electric resistance array resistance under required required precision control voltage range and the various condition.
Fig. 8 is the circuit diagram of delay unit of the present invention.As shown in Figure 8, Vinp and Vinn are differential input end; Voutn and Voutp are difference output end; Rn1 is first electric resistance array, and Rn2 is second electric resistance array, the load resistance that the equivalence that links together is; M3 is the 3rd metal-oxide-semiconductor, and M4 is the 4th metal-oxide-semiconductor, and described M3 and M4 are right for the interactive mode coupling that negative resistance is provided; M5 is the 5th metal-oxide-semiconductor, and M6 is the 6th metal-oxide-semiconductor, and described M5 and M6 are the input amplifier tube; Vdd is a power supply; Gnd is an earth terminal; I1 is first current source, and I2 is second current source.On circuit was realized, the present invention will be as the M1 of load pipe, and M2 directly uses the first electric resistance array Rn1, and the 2nd Rn2 substitutes.The present invention adopts electric resistance array, the electric capacity of this node can be considered as definite value, and only resistance value be regulated.Described electric resistance array is in series by a series of resistance, decides the resistance of place in circuit resistance by the gating of switch.Whether the gating of described switch is determined by control bit.Described control bit is directly by the output frequency of voltage controlled oscillator and the comparative result decision of reference frequency.
Comprehensive accompanying drawing Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, principle of the present invention is as follows: the transmission delay that annular voltage controlled oscillator is every grade can be explained with the value of resistance and electric capacity, i.e. Td=R*C.Because output frequency f=1/ (2NTd), if described Td is a constant, then f is a definite value.Under different process deviations and temperature, R and C can change, and change along with the variation of R and C and Td is also inevitable, cause f also can change.Therefore, the present invention utilizes calibration algorithm, compare by output frequency and reference frequency voltage controlled oscillator, according to described comparative result R is selected then, can make Td close with desired value as far as possible, and the output frequency of voltage controlled oscillator is also arrived in the adjusting range of control voltage by coarse adjustment.By control voltage frequency is finely tuned then, even phase-locked loop also can be locked on a certain Frequency point under the external condition.The present invention can realize with the control of calibration algorithm to the output frequency of voltage-controlled voltage, thereby phase-locked loop is locked on a certain Frequency point under various conditions.
In this specific embodiment, the progression N of delay unit is 3, and the reference frequency of phase-locked loop is 1MHz, and the locking frequency of phase-locked loop is 1GHz.Structure of the present invention and effect describe as just present embodiment, and technological thought of the present invention and core constitute and effect is not limited thereto.
Fig. 4 in conjunction with the accompanying drawings, Fig. 5, Fig. 6, Fig. 7, Fig. 8 adopts calibration algorithm that the output frequency of voltage controlled oscillator is carried out coarse adjustment in the present embodiment, process is as follows: the control voltage when calibration algorithm of the present invention begins is set to 1V, control bit is 1000, i.e. S8 gating, and the resistance R of place in circuit is (R0+R1+R2+...+R7+R8).Voltage controlled oscillator output frequency f is f1 after through 1000 frequency divisions.The reference frequency 1MHz of f1 and phase-locked loop is compared, if f1＜1MHz, then control bit transfers 0100 to, i.e. S4 gating, and the resistance R of place in circuit becomes (R0+R1+...R4), and R has reduced, and f has increased; If f1＞1MHz, then control bit transfers 1100 to, i.e. S12 gating, and the resistance R of place in circuit is (R0+R1+...R11+R12), and R has increased, and f has reduced; If the gap of the reference frequency 1MHz of f1 and phase-locked loop within arithmetic accuracy, then relatively finishes, otherwise compare with the frequency and the reference frequency of voltage controlled oscillator behind the R places in circuit of control bit 0100 or 1100 decisions again, all finish until the comparison step number.Can be according to required required precision, the control voltage range, the deviation range of R is formulated the variable quantity of step number and each step R under the various conditions, thus the output frequency of finishing voltage controlled oscillator carries out coarse adjustment.
After calibration algorithm finishes, control voltage is reverted to the voltage of being controlled by cycle of phase-locked loop, again the frequency of voltage controlled oscillator is finely tuned, guarantee the locking of phase-locked loop.
The above only for the preferred embodiment of invention, is not limited to the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a method of utilizing calibration algorithm to realize FREQUENCY CONTROL is characterized in that comprising the steps:
Step 1, utilize calibration algorithm, by the output frequency of voltage controlled oscillator and the reference frequency of phase-locked loop are compared, according to comparative result resistance is selected, make every grade transmission delay approaching with desired value as far as possible, thereby make the output frequency of voltage controlled oscillator be arrived in the adjusting range of control voltage by coarse adjustment;
Step 2 is finely tuned the output frequency of voltage controlled oscillator by control voltage then, thereby phase-locked loop can be locked on a certain Frequency point under various conditions.
2. a kind of method of utilizing calibration algorithm to realize FREQUENCY CONTROL as claimed in claim 1 is characterized in that described step 1 comprises further:
Step 1.1 at first compares the output frequency of voltage controlled oscillator and the reference frequency of phase-locked loop;
Step 1.2 is selected R according to described comparative result, promptly allows Td reach desired value, finishes the coarse adjustment of frequency.
3. a kind of method of utilizing calibration algorithm to realize FREQUENCY CONTROL as claimed in claim 1 is characterized in that the implementation procedure of described calibration algorithm is as follows: the voltage controlled oscillator output frequency is through behind the frequency division, compares with the reference frequency of phase-locked loop; If reference frequency less than phase-locked loop, then reduce the resistance of electric resistance array, increase the voltage controlled oscillator output frequency, if reference frequency greater than phase-locked loop, then increase the resistance of electric resistance array, reduce the voltage controlled oscillator output frequency, if the gap of the reference frequency of voltage controlled oscillator output frequency and phase-locked loop within arithmetic accuracy, then relatively finishes; Otherwise carry out once more relatively, all finish until comparing step number
4. device that utilizes calibration algorithm to realize FREQUENCY CONTROL, its structure comprises the 3rd metal-oxide-semiconductor (M5) at least, the 4th metal-oxide-semiconductor (M6), first current source (I1), second current source (I2), differential input end (Vinp, Vinn), and difference output end (Voutn, Voutp), power supply (Vdd), earth terminal (gnd) is characterized in that also comprising first electric resistance array (Rn1) and second electric resistance array (Rn2), and described first electric resistance array (Rn1) and second electric resistance array (Rn2) are together in series in parallel with the negative resistance that the 3rd metal-oxide-semiconductor (M3) and the 4th metal-oxide-semiconductor (M4) are formed by connecting as load resistance, (Vinp Vinn) connects with output.
5. a kind of method of utilizing calibration algorithm to realize FREQUENCY CONTROL as claimed in claim 4, it is characterized in that described electric resistance array comprises adjusting resistance (R0), first resistance (R1), second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9), the tenth resistance (R10), the 11 resistance (R11), the 12 resistance (R12), the 13 resistance (R13), the 14 resistance (R14), the 15 resistance (R15); Gating switch (S0), first gating switch (S1), second gating switch (S2), the 3rd gating switch (S3), the 4th gating switch (S4), the 5th gating switch (S5), the 6th gating switch (S6), the 7th gating switch (S7), the 8th gating switch (S8), the 9th gating switch (S9), the tenth gating switch (S10), the 11 gating switch (S11), the 12 gating switch (S12), the 13 gating switch (S13), the 14 gating switch (S14), the 15 gating switch (S15); The corresponding gating switch of each resistance, described gating switch is controlled the gating of this resistance, and described electric resistance array at every turn can only switch of gating.
6. a kind of method of utilizing calibration algorithm to realize FREQUENCY CONTROL as claimed in claim 5, it is characterized in that: the gating of described electric resistance array gating switch determines by control bit, and described control bit is directly by the output frequency of voltage controlled oscillator and the comparative result decision of the reference frequency of ring mutually of contracting.
7. a kind of method of utilizing calibration algorithm to realize FREQUENCY CONTROL as claimed in claim 6, it is characterized in that: the span of described control bit number is 2～6, the best value of described control bit number is 4.
8. a kind of method of utilizing calibration algorithm to realize FREQUENCY CONTROL as claimed in claim 7 is characterized in that: the resistance number of described control bit number decision electric resistance array.
9. a kind of method of utilizing calibration algorithm to realize FREQUENCY CONTROL as claimed in claim 8, it is characterized in that: when the control bit number was 2, the resistance number of electric resistance array was 4; When the control bit number was 3, the resistance number of electric resistance array was 8; When the control bit number was 4, the resistance number of electric resistance array was 16; When the control bit number was 5, the resistance number of electric resistance array was 32; When the control bit number was 6, the resistance number of electric resistance array was 64.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102185663A (en) * | 2011-02-16 | 2011-09-14 | 意法·爱立信半导体（北京）有限公司 | Frequency calibration method and device |
| CN102195646A (en) * | 2010-03-18 | 2011-09-21 | 上海华虹Nec电子有限公司 | Automatic clock oscillator calibration method and circuit |
| CN103368566A (en) * | 2012-04-01 | 2013-10-23 | 北京新岸线移动多媒体技术有限公司 | Clock control circuit and clock control method |
| CN103812317A (en) * | 2012-11-14 | 2014-05-21 | 台达电子工业股份有限公司 | Clamping absorption circuit and impedance adjusting method thereof |
| CN104300972A (en) * | 2014-09-30 | 2015-01-21 | 杭州电子科技大学 | Annular voltage-controlled oscillator circuit combining coarse tuning and fine tuning |
| CN105515576A (en) * | 2015-12-18 | 2016-04-20 | 河北新华北集成电路有限公司 | Ring voltage-controlled oscillator with coarse tuning and fine tuning, and phase-locked loop |
| CN106130547A (en) * | 2016-06-20 | 2016-11-16 | 大唐微电子技术有限公司 | A kind of clock frequency calibration steps and device |
| CN111384896A (en) * | 2018-12-27 | 2020-07-07 | 原睿科技股份有限公司 | Method, communication electronic device and processing circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102195646A (en) * | 2010-03-18 | 2011-09-21 | 上海华虹Nec电子有限公司 | Automatic clock oscillator calibration method and circuit |
| CN102185663A (en) * | 2011-02-16 | 2011-09-14 | 意法·爱立信半导体（北京）有限公司 | Frequency calibration method and device |
| CN102185663B (en) * | 2011-02-16 | 2014-07-30 | 意法·爱立信半导体（北京）有限公司 | Frequency calibration method and device |
| CN103368566A (en) * | 2012-04-01 | 2013-10-23 | 北京新岸线移动多媒体技术有限公司 | Clock control circuit and clock control method |
| CN103368566B (en) * | 2012-04-01 | 2018-02-06 | 北京新岸线移动多媒体技术有限公司 | Clock control circuit and clock control method |
| CN103812317A (en) * | 2012-11-14 | 2014-05-21 | 台达电子工业股份有限公司 | Clamping absorption circuit and impedance adjusting method thereof |
| CN103812317B (en) * | 2012-11-14 | 2016-08-24 | 台达电子工业股份有限公司 | Clamp absorbing circuit and impedance control method thereof |
| CN104300972A (en) * | 2014-09-30 | 2015-01-21 | 杭州电子科技大学 | Annular voltage-controlled oscillator circuit combining coarse tuning and fine tuning |
| CN105515576A (en) * | 2015-12-18 | 2016-04-20 | 河北新华北集成电路有限公司 | Ring voltage-controlled oscillator with coarse tuning and fine tuning, and phase-locked loop |
| CN105515576B (en) * | 2015-12-18 | 2018-10-12 | 河北新华北集成电路有限公司 | Annular voltage controlled oscillator with coarse adjustment and fine tuning and phaselocked loop |
| CN106130547A (en) * | 2016-06-20 | 2016-11-16 | 大唐微电子技术有限公司 | A kind of clock frequency calibration steps and device |
| CN111384896A (en) * | 2018-12-27 | 2020-07-07 | 原睿科技股份有限公司 | Method, communication electronic device and processing circuit |
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