CN101126974A - Improved Booth2 multiplier structure - Google Patents

Abstract

The utility model relates to an improved Booth 2 multiplier structure, which comprises two partial products realized by hardware and an adder for adding the two partial products; wherein, a bit adding circuit is respectively added on the highest two bits of the two partial product circuits; all partial product bits of the adder are made into same length, at the same time, the number of the partial products does not increase. The utility model has the advantages of small circuit area, simple and regular structure and small influence on the circuit performance.

Description

A kind of improved Booth 2 multiplier architectures

Technical field

The present invention relates to a kind of improved Booth 2 multiplier architectures.

Background technology

The Booth algorithm is at two's complement data form, and in the process of multiply operation, it is long-pending mainly to be responsible for generating portion.The core of Booth algorithm is the long-pending generation form of Booth coded portion of two's complement data.For example, consider the two A=(a of a N position _N-1, a _N-2..., a ₀), its Booth coding form is as follows:

A＝-a _N-1·2 ^N-1+∑a _i·2 ⁱ＝∑(a _i-1-a _i)2 ⁱ (1)

Wherein (i=0,1 ..., N-1); a _-1=0

So:

P＝A×B＝∑(a _i-1-a _i)×B×2 ⁱ (2)

Above formula is Booth 1 rank codings, can obtain actual Booth 1 coding schedule by formula, and the operation of corresponding partial product, and is as shown in table 1.

Table 11 rank Booth coding schedule

a i	a i-1	The Booth coding	Corresponding multiply operation
				0	0	0	Partial product moves to left one
0	1	1	Add B to partial product, and the result is moved to left one
				1	0	-1	Add-B is to partial product, and the result is moved to left one
1	1	0	Partial product moves to left one

·Booth 2

Cry again and improve Booth algorithm (Modified Booth Method).The partial product number that produces is few more, and the multiplication iterations is few more, and speed is fast more.Here, multiplier is divided into the form of 2 hytes, when still carrying out Booth decoding, once checks 3, and wherein 2 is the group of current decoding, and 1 is the low level in the adjacent high hyte in addition.Times multiplying factor of partial product is that { ± 2, ± 1,0} just can realize by simple displacement and supplement.The number of partial product is

(n is the multiplier bit wide), the iteration that promptly only need carry out about right and wrong Booth mode one demidegree just can be finished and take advantage of operation.

·Booth 3

Similar with Booth 2, multiplier bit is divided into the form of 3 hytes, 4 hytes that each iteration inspection overlaps.The number of partial product is

Than Booth 2 still less.Shortcoming is that not only Booth decoding logic complexity rises, and partial product generation logic scale is very big.Especially times multiplying factor of correspondence ± 4, ± 3, ± 2, ± 1, among the 0}, take advantage of for ± 3 times and can not only realize by displacement and supplement, also need adding of a carry propagation, bring the area of partial product generation and the sharp increase of time-delay.

Booth 4 algorithms can also be arranged, further reduce the number of partial product.But, times multiplying factor in Booth 4 algorithms become ± 8, ± 7, ± 6, ± 5, ± 4, ± 3, ± 2, ± 1,0}, a times multiplying factor that needs special carry propagate adder to realize has ± 7, ± 5, ± 3 three classes.Not only carry propagate adder is many, and area is very huge, and combinatorial path is also very long, and the Booth decoding logic is also quite complicated.

Because Booth 2 algorithms are at the complement code design, if directly realization is the most significant digit that sign bit expands to array with regard to the most significant digit that requires each partial product.So will make the scale of PPA partial product array become very big, and the length of each partial product is inconsistent, has brought the difficulty of design.The method that prevents sign extended is discussed below.

Multiplier with the 16*16 position is an example, supposes that at first all partial products all are positive, adopts Booth 2 algorithms, and the synoptic diagram that can obtain array as shown in Figure 1.Each stain is represented of partial product among Fig. 1, notices among Fig. 1 overflowing when preventing positive and negative 2 times of situations, and except last partial product, remaining partial product all is 17.Because last partial product can not overflowed, so it is 16 owing to mend two 0 in the multiplier front.Opposite with the situation of Fig. 1, Fig. 2 has provided all partial products and has been negative situation.At this moment, all partial products all will become anti-and add 1 in the position, end, are equivalent to become complement code.And the sign bit of front must polishing during the complement code addition.

1 of upper left corner sign bit among Fig. 2 can be obtained in advance, is added in the array as a fixing value.Be without loss of generality, suppose that multiplication is to carry out between the multiplicand A of a n position and the multiplier B of m position (m is an even number), adopt Booth 2 algorithms.All partial products are all born, will to each partial product all use 1 the expansion, so 1 of all sign extended and be:

$\mathrm{signs}=\underset{i=0}{\overset{m/2-1}{\mathrm{\Σ}}}(2^{n+m}-2^{n+1+2i})\mathrm{mod}{2}^{n+m}=-2^{n+1}\underset{i=0}{\overset{m/2-1}{\mathrm{\Σ}}}{2}^{2i}$

$=-(2^{m-2}+2^{m-4}+\·\·\·2^2+2^0)\·2^{n+1}$

(3)

This number can be used as a fixing value and is added in the partial product, its total m position, and the weights of lowest order are 2 ^N+1So just obtained Fig. 3.

Previously discussed all is that partial product is entirely for just or entirely being negative situation.If for the situation of Fig. 3, suppose that some partial products are non-negative, be equivalent on the lowest order of sign bit, add one 1, so become a stringly 0 in a string 1 of partial product front, this moment, Fig. 3 just became the situation of Fig. 4.S represents sign bit, and partial product is for negative when s=1, and corresponding partial product is wanted the step-by-step negate.

To the situation of Fig. 4, two " 11 " that first partial product adds previously just can with

Merge, thereby make the height of PPA partial product array reduce.Promptly $11+\stackrel{\‾}{s}=\stackrel{\‾}{s}\mathrm{ss}.$ Fig. 5 is so just arranged, and first partial product is Duoed one than the long-pending figure place of other parts in Fig. 5.

For the signed number of complement representation, revise as long as carry out some on the basis in front.For the multiplication of data without sign, utilize Booth 2 algorithms, the generation of last partial product is owing to fill two 0 as sign bit in the multiplier front, does not just need to have done like this for signed number.Be equivalent to reduce a partial product, but can not guarantee that last partial product is non-negative than the situation of front.Can obtain Fig. 6.The length of first partial product and other parts are long-pending different as can be seen from Figure 6, and needing increases by 3, and are regular so inadequately.Realize well that for hardware the another kind of scheme of proposition is also arranged, 1 of each partial product front among Fig. 6 is added in the array as a partial product separately, get the method shown in Fig. 7.This method various piece is long-pending equally long, and all being increases by two, but has increased a partial product.So existing design exists the partial product circuit not reuse, and perhaps needs to increase the shortcoming of partial product number, makes that circuit area consumption is big, complex structure, the irregular shortcoming of circuit.

Summary of the invention

Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of chip occupying area improvement Booth little, simple in structure is provided 2 multiplier circuit structures.

Technical solution of the present invention: a kind of improved Booth 2 multiplier architectures that symbol is arranged, its characteristics are: comprise that hard-wired first partial product and second partial product reach the totalizer to described two partial product additions; A circuit is added in the highest two interpolations first at described first partial product, adds a circuit in the highest two interpolations second of described second partial product, thereby makes the long-pending figure place of various piece of multiplier equally long, and the partial product number does not increase simultaneously.

Described multiplier also comprises a Booth coding unit and the 2nd Booth coding unit, is connected on the input end of 3-2 totalizer in first partial product and the second portion respectively.

The input termination control end of most significant digit full adder in the described first partial product

With power vd D, control end Be to be produced through reverser by control signal C, time high-order full adder input end adds control signal C in the first partial product; Two of the most significant digit full adder input end grounding GND in the second partial product, an input of time high-order full adder termination power vd D in the second partial product makes hardware multiplexing.

The length of described first partial product and second portion is random length.

The coding number that a described Booth coding unit and the 2nd Booth coding unit produce is an any number.

Principle of the present invention is: make that by simple increase control end the long-pending figure place of various piece is equally long, the partial product number does not increase simultaneously.Consider that there is following relation in binary number

$E+1=E\stackrel{\‾}{E},\stackrel{\‾}{E}+1=\stackrel{\‾}{E}E,E+\stackrel{\‾}{E}=1---\left(4\right)$

Can derive

$(\stackrel{\_}{E}+1)E=\stackrel{\‾}{E}\mathrm{EE}$

$(E+1)\stackrel{\‾}{E}=E\stackrel{\‾}{\mathrm{EE}}$ (5)

$E(\stackrel{\‾}{E}+1)=(E+\stackrel{\‾}{E})E=1E---\left(6\right)$

$\stackrel{\‾}{E}(E+1)=(\stackrel{\‾}{E}+E)\stackrel{\‾}{E}=1\stackrel{\‾}{E}---\left(7\right)$

According to top equation Fig. 6 is improved to Fig. 8 method.

Because it is that the serial timesharing produces that Booth multiplier partial product produces, when first partial product produces $C=0,\stackrel{\‾}{C}=1,$ Other parts are amassed when producing then $C=1,\stackrel{\‾}{C}=0.$ At this moment promptly produce the situation of Fig. 9, Fig. 9 is of equal value according to the equation relation with Fig. 6.

The present invention's advantage compared with prior art is: the present invention promptly adds a circuit by increasing simple control end, makes the long-pending figure place of various piece of multiplier equally long, and the partial product number does not increase simultaneously.The present invention has little, the simple in structure rule of circuit area, circuit performance is influenced little characteristics.

Description of drawings

Fig. 1 is positive Booth 2 algorithm patterns for partial product;

Booth 2 algorithm patterns when Fig. 2 is negative for partial product;

The negative PPA partial product array figure that Fig. 3 sues for peace in advance for sign bit;

Fig. 4 is PPA partial product array figure completely;

The completely PPA partial product array figure of Fig. 5 for highly reducing;

Fig. 6 is the PPA partial product array figure of signed number multiplication;

Fig. 7 is the array of figure of partial product equal in length;

Fig. 8 is the improved PPA partial product array figure that the sign multiplication device is arranged of the present invention;

The improved partial array figure that the sign multiplication device is arranged when Fig. 9 considers the C value for the present invention;

Figure 10 improves Booth 2 multiplier circuit figure for the present invention;

Figure 11 is Booth 2 codings of coefficient among the ROM among the present invention.

Embodiment

Improved Booth2 multiplier of specific implementation of the present invention uses method shown in Figure 9.Concrete detailed circuit such as Figure 10.In Figure 10, adopt the 3-2 totalizer to come to the partial product computing.Figure 10 provide can be multiplexing first partial product 117 and second partial product 118.Add first respectively and add a circuit 115 and second and add a circuit 116 the highest two of described first partial product 117 and second partial product 118, thereby make the long-pending figure place of various piece of multiplier equally long, the partial product number does not increase simultaneously.First partial product 117 is made of 20 3-2 totalizers 113 and 21 full adder FA, and the concrete totalizer and the number of full adder constitute and can determine that present embodiment adopts above-mentioned quantity according to designing requirement.3-2 totalizer 113 by 2 with door, 1 or and 1 XOR gate composition.Second partial product 118 is made of 20 3-2 totalizers 114 and 21 full adder FA, 3-2 totalizer 132 respectively by 2 with door, 1 or and 1 with or door composition.

Figure 10 has shown the highest two methods of adding the position of first partial product 117, second partial product 118.Increase by first in the first partial product 117 and add a circuit 115, the input termination control end of first partial product 117 full adder FA 120

With power vd D, full adder FA 121 input ends add C in the first partial product 117,

Be to produce through reverser by control signal C; Increase by second in the second partial product 118 and add a circuit 116, two of full adder 123 input end grounding GND in the second partial product 118,124 1 inputs of full adder termination power vd D in the second partial product 118, thus can be so that hardware multiplexing.

Multiplier of the present invention also comprises a Booth coding unit 110 and the 2nd Booth coding unit 111, is connected on the input end of 3-2 totalizer in first partial product 117 and the second partial product 118 respectively.Corresponding is output coefficient in the ROM112 unit (as the multiplier of multiplier) therewith.The coefficient of storing among the ROM112 generates 1 times of multiplicand 1M, 2 times multiplicand 2M and sign bit S through a Booth 2 coding units 110, the 2nd Booth 2 coding units 111 among Figure 10.The one Booth coding unit 110 and the 2nd Booth 2 coding units 111 by one with or, an XOR and one or non-the composition.Suppose that coefficient is 13,13 potential coefficients through Booth 2 coding as shown in figure 11, such one has 8 partial products, two partial products of computing during every beating-in, 1. 2., 3. 4., 5. 6. and 7. 8., each multiplication divides 4 to clap and finish.Owing to adopt to add the control signal circuit, thus 3. 4., 5. 6. and 7. 8. partial product can adopt 117 and 118 circuit, so each partial product length is the same, rule simple in structure has been saved hardware area.Result after the summation of two partial products of every bat enters latch to wait for the summation that adds up again of partial product with next bat, clapping computing up to 4 all finishes, then this number has realized that 13 with multiplier are all finished multiplying, enter last latch units after all partial products all add.

The length of first partial product 117 and second partial product 118 can be random length, and two Booth coding units 110 and the 111 coding numbers that produce can be for arbitrarily, this example calculation be 18*13, this multiplier architecture all is suitable for any n*m position multiplication.

Claims (5)

1. improved Booth 2 multiplier architectures is characterized in that: comprise that hard-wired first partial product (117) and second partial product (118) reach the totalizer (109) to described two partial product additions; A circuit (115) is added in the highest two interpolations first at described first partial product (117), add a circuit (116) in the highest two interpolations second of described second partial product (118), thereby the long-pending figure place of the various piece that makes whole multiplier is equally long, and the partial product number does not increase simultaneously.

2. a kind of improved Booth 2 multiplier architectures according to claim 1, it is characterized in that: described multiplier also comprises a Booth coding unit (110) and the 2nd Booth coding unit (111), is connected on the input end of 3-2 totalizer in first partial product (117) and the second partial product (118) respectively.

3. a kind of improved Booth 2 multiplier architectures according to claim 1 and 2 is characterized in that: the input termination control end of most significant digit full adder (120) in the described first partial product (117)

With power vd D, control end Be to be produced through reverser by control signal C, time high-order full adder (121) input end adds control signal C in the first partial product (117); Two input end grounding GND of most significant digit full adder (123) in the second partial product (118), (124) inputs of time high-order full adder termination power vd D in the second partial product (118) makes hardware multiplexing.

4. a kind of improved Booth 2 multiplier architectures according to claim 1 and 2, it is characterized in that: the length of described first partial product (117) and second partial product (118) is random length.

5. a kind of improved Booth 2 multiplier architectures according to claim 2 is characterized in that: the coding number that a described Booth coding unit (110) and the 2nd Booth coding unit (111) produce is an any number.

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