CN101119190A - Method for loading clock signal to ethernet linkage - Google Patents

Abstract

The present invention relates to method to carry clock signals on Ethernet links. The 5B encode blocks which are designed illegal by Standard 802.3 are chosen and reserve one of the blocks as CLK of clock signal encode block. When a carrying clock signal is needed, the sender inserts a preset clock signal encode block CLK into the 5B encode block group. The receiver checks each 5B encode block in the 5B encode block group. When the receiver detects the reserved clock signal encode block CLK, the receiver extracts the clock signal encode block CLK and outputs a signal impulse. The beneficial effect of the present invention is that the present invention can carry clock signal under the premise of accordance with the standard 802.3, and to realize good synchronization of the clocks of the application layer on two ends of the link, thus preventing error code cause by slip code of the two ends. The present inventionhas significant meaning and effectiveness on enhancing transferring quality for TDMoverIP, i.e. using IP technology to start TDM businesses including telephones, faxes, and high quality audio/video.

Description

The method of loading clock signal on ethernet link

Technical field

The present invention relates to digital communicating field, mainly be a kind of on ethernet link the method for loading clock signal.

Background introduction

The synchronous of clock frequency is vital for carrying out of TDMoverIP business.If the equipment of both link ends all adopts the free oscillation mode, although the precision of then modern high accuracy crystal oscillator can be controlled at 10ppm with interior (1ppm be exactly 1,000,000/), the nuance of two ends speed still can cause " slip " through long accumulation, thereby causes the error rate to rise.The clock of Ethernet interface itself then is independently, and is irrelevant with the clock of system applies layer, also do not become simple multiple relation on the frequency, thereby can not be as the foundation of clock synchronization.So the existing Ethernet technology can not be transmitted the application layer clock information, clock synchronization is a difficult problem for TDMoverIP.The invention provides a kind of on ethernet link the method for loading clock signal, make the equipment at ethernet link two ends can reach good synchronously.

For this reason, to introduce some relevant in ethernet technology characteristics earlier.

Press the regulation of IEEE 802.3 standards, the flow of 100 m ethernet per second 100 megabits is with the frequency transmission of 125 megabits physically in fact.When sending, physical layer PHY will with from the link layer low layer, be that 4 logics " hyte (Nible) " of media access control sublayer convert one 5 physics " code character (Code Group) " earlier to, on physical medium, send again.And the recipient then wants earlier the 5 bit code groups that receive to be converted to 4 hytes, it is submitted to the MAC layer of Ethernet again.In the relevant document this conversion back and forth is called 4B5B, i.e. conversion between 4 hytes and the 5 bit code groups.In this manual, the conversion from 4B to 5B is write as 4B/5B or 4Bto5B, otherwise is then write as 5B/4B or 5Bto4B.The 5B code character is also referred to as " symbol (Symbol) ", and can represent with an English alphabet.

Interface between MAC layer and the PHY layer is called MII, means " with concrete media independent ".On the MII interface, exchange is the 4B hyte between the upper and lower layer.And, then have a circuit module to be called PCS in PHY layer inside, handled mainly is exactly 4B5B, and " stirring (Scrambling) " and the reduction that also will carry out the physical signalling waveform under the situation that adopts category 5 twisted pair, to reduce electromagnetic radiation.

At transmit leg, later through the processing of PCS has been exactly the transmission on concrete medium, and this part circuit is different because of concrete medium certainly.The recipient, then just in proper order conversely.

Conversion from 4B to 5B means in all possible 5B code character, have many 5B code characters (value) not use.Because 4 hyte has only 16 kinds of possible combinations, and 5 code character has 32 kinds of possible combinations, the difference of the two is up to 16.802.3 standard is at first therefrom selected 16 kinds of 5B code characters, and is corresponding with 16 kinds of 4B hytes, again 16 kinds of remaining 5B code characters made following regulation:

As " idle running (Idle) " sign indicating number, and represent it with wherein a kind of (5 complete 1) with alphabetical I.When not having data to send, just on link, constantly repeat to send the idle running sign indicating number;

Connect together as the initial symbol of physical frame with wherein two, be called SSD (Start of Stream Delimiter), these of two 5B code characters are expressed as J, and another is expressed as K; Perhaps be expressed as SSD1 and SSD2, two 5B code characters must send just meaningful in succession, and other code character can not be inserted in the centre.

Use wherein two again and connect together as the end mark of physical frame, be called ESD (End of Stream Delimiter), these of two 5B code characters are expressed as R, and another is expressed as T; Perhaps be expressed as ESD1 and ESD2, these two 5B code characters also are to send just meaningfully in succession, and other code character can not be inserted in the centre.

Also have a 5B code character H, it is encoded to 00100, is used for notifying the other side that certain mistake has taken place.

Except that these, remaining 10 5B code character is " illegal (Invalid) " code character, and transmit leg is to send these 5B code characters, just illustrates that error code has been arranged on the link if the recipient has received these code characters.Left these " illegally " 5B code character has 00000,00001,00010,00011,00101,00110,01000,01100,10000 and 11001.

The basic ideas of the method for the invention are exactly: in the time will sending the rising edge of an application layer clock signal, for example clock pulse, transmit leg is just sending a 5B code character predetermined, be defined as " illegally " in 802.3 standards on the link.This specific 5B code character yes one of above-mentioned 10 kinds of " illegally " 5B code characters; Anyly then belong to the realization details as for select actually, and do not influence essence of the present invention; But 00000 obviously is inappropriate, because 0 expression is unglazed on fiber medium.And the recipient, then that this is specific " illegally " 5B code character is extracted out from the code character of routine stream, and at clock pulse rising edge of this locality output, just the 5B code character stream of routine is carried out the 4B/5B conversion then.

Trailing edge as for clock pulse is then unimportant because for clock synchronization the position of pulse importantly, rather than its width.

So, clock signal is to carry on ethernet traffic with the form of " illegally " 5B code character, because the recipient is just extracting this " illegally " 5B code character out before sending to MAC on the flow that receives, the conventional legal 5B code character that is still that MAC sees on the MII interface flows, thereby the lift-launch of clock signal is transparent.On the other hand, even if the recipient is the common Ethernet chip with clock signal extract function, also think on the link error code is arranged for no other reason than that detect " illegally " 5B code character, think just that at most link-quality descends to some extent, and think that still the other side's (transmit leg) is the ethernet node that meets 802.3 standards.Certainly, in the application that does not need loading clock signal, transmit leg should be closed this and be inserted clock signal, the i.e. function of specific " illegally " 5B code character.

Ethernet interface chip in actual the use has two classes.One class is that the function of MAC layer and PHY layer is integrated in in the chip piece, is called Ethernet " controller " (Controler).In this class chip, PCS comprises that 4B5B is the circuit of chip internal, so can't be from outside change.Another kind of MAC and PHY are made two chips respectively, thereby become a chipset, PHY chip wherein often is called Ethernet " transceiver ".Connection interface between MAC chip and the PHY chip then is called MII, and the meaning is " with the interface of media independent ".What transmit on the MII interface all is the 4B hyte, in 802.3 texts there are detailed regulation and explanation in this interface.In the product of this class, most PHY chips are all supported a kind of " PCSBP pattern ", the pattern of promptly " walking around PCS ", are also referred to as " 5B pattern of symbol ", can realize the 4B5B conversion separately in the PHY chip exterior, and this just provides convenience for enforcement of the present invention.But, even in the circuit of the ethernet controller of one, also still can in the circuit design of chip, adopt method of the present invention.

Summary of the invention

Purpose of the present invention is exactly to overcome the shortcoming that existing ethernet technology can not be transmitted the application layer clock information, provide a kind of on ethernet link the method for loading clock signal, mainly being a kind of particular code group that will represent clock signal inserts common ethernet traffic and idle running code stream and is extracted the recipient at transmit leg, realizing the synchronous method of clock frequency between the adjacent ethernet node, purpose is that to keep good clock frequency between the upstream and downstream of TDMovrIP flow synchronous.

The present invention solves the technical scheme that its technical problem adopts:

Ethernet chip group based on the MII interface comprises MAC and two kinds of chips of PHY, most PHY chips are all supported the PCSBP pattern, allow to walk around the 4B5B conversion (and " stirring (Scrambling) " and reduction of physical signalling stream) in the chip exactly, and direct I/O 5B code character allows the MAC layer can realize own special 4B5B conversion.

Method of the present invention adopts the PHY chip of supporting the PCSBP pattern, plants therewith at the MAC chip and inserts circuit or the function that is used for clock signal lift-launch/extraction between the PHY chip.The basic skills of loading clock signal is:

By 802.3 standard definitions be select in the illegal 5B code character and predetermined one of them as clock signal code character CLK;

Transmit leg inserts preset clock signal code character CLK in the 5B code character stream that is sent, the predetermined clock signal that inserts 5B code character stream can be single 5B code character, also can be the particular combinations of several predetermined 5B code characters;

The recipient then detects and takes out CLK code character (or particular combinations of several predetermined 5B code characters) and export clock pulse from the 5B code character stream that receives.

Following narration is an example with the CLK of single 5B code character, divides to send and receive two sides further to be illustrated.In the narration below, except that the application layer clock signal clk that is carried, also relate to two clock signal TX_CLK and RX_CLK on the MII interface.This is the clock signal of Ethernet interface itself, and the MAC chip is subjected to the driving of TX_CLK to send the 4B hyte, the 4B hyte is consigned to the PHY layer to PHY; And be subjected to the driving of RX_CLK to receive, promptly read in the 4B hyte from the PHY layer.TX_CLK and RX_CLK and carry, need be transferred to far-end the application layer clock signal clk be two different matters fully, ten million can not obscure.

The clock signal of seeing transmit leg is earlier carried circuit.On the basis of original MAC and PHY chip or circuit, transmit leg increases by two parts, and one is that clock signal is inserted circuit, and another is the 4B/5B transducer.It is a finite state machine that clock signal is wherein inserted circuit, and its state variation has realized the main operating process of transmit leg.The 4B/5B transducer then is a table of comparisons, in fact just the original 4B/5B transducer of realizing in the PHY chip, still being bypassed is realized one time in the chip outside again.So key is clock signal insertion circuit.It is the part of PHY layer that clock signal is inserted circuit, can be regarded as the expansion to original PHY layer.

One, the main operating process of transmit leg:

1,, converts the 5B code character by the required 4B/5B change-over circuit of this method to by the regulation of 802.3 standards earlier for passing through the MII interface, paying the 4B hyte that the PHY layer sends by MAC.

If 2 do not insert the request of clock signal, just this 5B code character is handed to the PHY chip that is in the PCSBP pattern and supply to send; And get back to previous step;

If 3 have the request of inserting clock signal, but current 5B code character is one of back in must two 5B code characters of running fire, just wouldn't show interest in the request of this insertion clock signal;

4 otherwise, just:

4.1) cut off the tranmitting data register pulse TX_CLK on the MII interface earlier, MAC is suspended to the PHY layer pay the 4B hyte.

4.2) will represent the 5B code character CLK of clock signal to consign to the PHY chip confession transmission that is in the PCSBP pattern, and remove the request of inserting clock signal.

4.3) recover the tranmitting data register pulse TX_CLK on the MII interface, make MAC continue to pay the 4B hyte to the PHY layer.

5, get back to the first step.

Like this, MAC has postponed the payment of a 4B hyte (to local PHY) when inserting a 5B code character CLK, is recovered then, and this has just realized the insertion of clock signal.If what be used for representing clock signal is not single 5B code character but the sequence of a special code character is just cut off some TX_CLK pulses in succession by corresponding quantity, make MAC postpone the payment of the 4B hyte of respective numbers.

The TX_CLK pulse of cutting off on the MII interface is a simple and easy to do method, but is not unique method.For example, also can be in several 4B hytes of PHY layer buffer memory or 5B code character when inserting clock signal, and then order is sent.But this is the details of specific implementation, does not influence essence of the present invention.

See the recipient again.On the basis of original MAC and PHY chip or circuit, the critical piece that the recipient increased is a clock signal extraction circuit and a 5B/4B transducer.Equally, the clock signal extraction circuit also is a finite state machine, is realizing recipient's main operating process.The 5B/4B transducer then is a table of comparisons, in fact just the original 5B/4B transducer of realizing in the PHY chip, still being bypassed is realized one time in the chip outside again.So key is the clock signal extraction circuit.Equally, the clock signal extraction circuit also is the part of PHY layer, can be regarded as the expansion to original PHY layer.

Two, recipient's main operating process:

1, because the circuit arrangement of transmit leg, the arrival of clock signal code character CLK only may be interim in idle running or the transmission of physical frame during, and can not occur between SSD1 and the SSD2 and between ESD1 and the ESD2.

2, by comparison, if find that the new 5B code character that arrives is the preset clock signal code character,, make MAC postpone reading in the 4B hyte from PHY with regard to the receive clock pulse RX_CLK on the temporarily disconnected MII interface, and the pulse of output corresponding clock; Things are as usual otherwise just.

Above-mentioned flow process has a potential problem, is exactly that clock signal is in the interim lift-launch of idle running.Interim in idle running, what transmit leg sent on link is all "1"s signal.All "1"s signal can make both sides' Ethernet interface clock synchronous as far as possible, but can not distinguish the code character border, if the idle running phase is long, still might make both sides lose the boundary alignment of 5B code character.The particularity of SSD1+SSD2 then makes can align the again border of 5B code character of both sides.So,, then exist because of the border to lose the danger that can not correctly recognize of alignment if also represent clock signal with single 5B code character in the idle running phase.Can above-mentioned realization details be made improvements for this reason again, make and represent the clock signal of being carried in the sequence of the interim usefulness of idle running one " SSD1 SSD2 CLK ESD1 ESD2 ".Like this, the TX_CLK clock pulse of transmit leg on can temporarily disconnected MII interface in case the MAC layer starts transmission (do not have the TX_CLK pulse, MAC just can not start transmission) suddenly, waits to send this 5B code character sequence and give recovery later on again.Like this, the flow process of transmit leg is not complicated more a lot of than original.But recipient's flow process and state machine will be more complicated:

1, from the idle running phase, the next 5B code character of recipient's acceptable is IDLE or SSD1.

2 if IDLE just continues to stay the idle running phase, gets back to previous step.

3 if SSD1 has just begun the reception of a clock signal sequence or a physical frame.The unique acceptable 5B of recipient's this moment code character is SSD2.

4, receiving after the SSD2, if next 5B code character is not CLK, but is to be defined as legal 5B code character (the 4B hyte being arranged correspondingly) in one 802.3 standard, has just begun the reception of a frame.

5, in the middle of the receiving course of frame, clock signal is representative with single CLK code character, so it is identical to state flow process still.

6, the receiving course of frame finishes because of the arrival of ESD1, and this moment, unique acceptable 5B code character was ESD2.

7, in superincumbent the 4th step, receive after the SSD2,,, see next 5B code character then with regard to corresponding output clock pulse if next 5B code character is CLK.

If 8 next 5B code characters are ESD1, just illustrate that this is the clock signal sequence, this moment, unique acceptable 5B code character was ESD2.

9, receive ESD2 and just get back to idling conditions later on, get back to the top first step.

10, in superincumbent the 8th step,, but be to be defined as legal 5B code character (the 4B hyte being arranged correspondingly) in one 802.3 standard, just begun the reception of a frame if next 5B code character is not ESD1.Get back to the 5th top step.

Equally, concrete realization details also has variation, but the difference of details does not influence the essence that the present invention utilizes special code character loading clock signal on ethernet link.

In the above-mentioned flow process of having improved, if the arrival of application layer clock pulse is to send a frame midway, promptly be between a pair of SSD and the ESD, the time (delay) that needs so to wait for is exactly at most 40nS, the i.e. transmitting time of a 5B code character, just can insert into the clock signal clk code character.But, if in the idle running phase, two code characters of SSD1 and SSD2 must be arranged in the CLK front then, just additionally increased by two delays that code character is 80nS, can reach 120nS altogether.The worst situation then occurs between ESD1 and the ESD2, and have three code characters before the CLK this moment, thereby the delay of 160nS has just been arranged.Like this, the CLK that has does not postpone, and the CLK that has has the delay of 160nS, and the small size shake of clock signal has just been arranged.Generally speaking, the jitter problem of 160nS is little, because the cycle of 2MHz signal is 500nS.But this also is a problem after all for the application of having relatively high expectations, and must use in addition frequency stabilization of phase-locked loop so extract a side of clock signal.Meanwhile, also can before single CLK code character, also add another 5B code character, make the relative scope of shake to dwindle.But all these belongs to the realization details.

If an end of ethernet link is an intermediate node, then can also transmit clock signal from updrift side.Certainly, on the ethernet link that needs are transmitted, all to adopt method of the present invention.When need transmitting, carry the clock signal of downstream direction transmitting terminal can from:

The clock signal extraction circuit of updrift side receiving terminal;

With updrift side clock signal that receiving terminal is extracted is the phase-locked loop of reference;

Certain local clock source.

As mentioned above, with respect to the clock pulse rising edge of reality, the transmission of clock signal clk code character postpones to some extent, and sequential is then depended in concrete delay.Under the situation of a plurality of node cascades, such shake might be by station accumulation, thus generally should not directly use the clock signal of being carried when transmitting, and should be through the frequency stabilization of phase-locked loop.Like this, just can reach more accurate Frequency Synchronization between the upstream and downstream.

Here related PHASE-LOCKED LOOP PLL TECHNIQUE is a known technology, does not give unnecessary details so do not add herein, if needed can be with reference to the relevant monographs such as " Phase-LockedLoops " of R.Best.

Based on the above method, can also support ethernet physical layer (PHY) chip of PCSBP pattern to connect back-to-back with two, the centre adds clock signal insertion/extraction circuit of the present invention as auxiliary, to constitute the ethernet repeater (Repeater) that a hold clock signal is carried.Like this, on the interface of two conventional ethernet nodes, respectively seal in a transponder, thus just can between two transponders between two nodes loading clock signal.The benefit of doing like this is that original equipment need not change basically.On the other hand, owing to the both sides of transponder all are the existence that ethernet link need not the MII interface, so the conversion of 4B/5B and 5B/4B just can have been saved.Concrete method is the receiving terminal of a PHY chip to be exported be connected to the clock signal extraction circuit, the 5B code character output of clock signal extraction circuit is connected to the 5B code character input of another PHY chip transmitting terminal again, just can constitute the passage of a direction.Reverse passage then uses clock signal to insert circuit.Like this, two passages are superimposed, just can constitute the ethernet repeater of two-way (full duplex).

Compare with common transponder, this transponder is transmitted conventional ethernet traffic, and can on the ethernet link between two transponders, carry and extract clock signal, but, then played filtered clock signal for the conventional ethernet node that is positioned at transponder " behind ".

Similar on the physical layer principle of gigabit Ethernet to 100,000,000, what just gigabit Ethernet adopted is the 8B/10B code character, and the 100 m ethernet employing is the 4B/5B code character, so the method for the invention can be used in loading clock signal on the gigabit ethernet link equally, difference just is the width of register in the definition, circuit of code character, the length of code character transmission/receiving cycle or the like details.In other words, this method at be " Ethernet " and be not only " 100 m ethernet ".

The effect that the present invention is useful is: can be under the prerequisite that meets 802.3 standard codes on ethernet link loading clock signal, make the clock of application layer on the both link ends equipment reach good synchronously, thereby can prevent the error code that two ends cause because of " slip ".The TDM business that this for TDMoverIP, promptly utilizes the IP technology to carry out to comprise phone, fax, high quality audio/video or the like for improving transmission quality, has great significance and effectiveness.

Description of drawings

Fig. 1 is that the clock signal of transmit leg is carried, and is about to the schematic flow sheet in the clock signal clk insertion Ethernet 5B code character stream;

Fig. 2 is that recipient's clock signal extracts, and promptly upstream node is inserted into the schematic flow sheet that the clock signal clk in the Ethernet 5B code character stream is peeled off out;

Fig. 3 and Fig. 4 are the status transition charts of receiving terminal;

Fig. 5 is the structural representation for ethernet repeater;

Fig. 6 is the schematic diagram that connects existing ethernet device with transponder.

Embodiment

The present invention is further detailed explanation below in conjunction with drawings and Examples.

Accompanying drawing is how to be used for illustrating the schematic diagram of loading clock signal on ethernet link: wherein the 4Bto5B of transmitting terminal and clock signal code character are inserted circuit and can be skipped under the control of a switching value among Fig. 1.If skip, entire circuit just only remaining ethernet physical layer chip PHY also in action, so just be equal to the transmitting terminal of normal ethernet physical layer PHY this moment.Equally, the 5Bto4B of Fig. 2 middle and lower reaches receiving terminal and clock signal code character extraction circuit also can be skipped under the control of a switching value, if skip, entire circuit just only remaining ethernet physical layer chip PHY also in action, so just be equal to the receiving terminal of normal ethernet physical layer PHY this moment.Fig. 3 be idle running interim use single CLK code character the time flow process.This flow process is fairly simple, but as mentioned above the idle running phase grown the danger that loses 5B code character boundary alignment just arranged, so may less stable.Fig. 4 then is the flow process when adopting " SSD1 SSD2 CLK ESD1 ESD2 " sequence in the idle running phase.Fig. 5 is the structural representation of ethernet repeater, note no longer needing to use 5B/4B conversion and 4B/5B change-over circuit here, because PHY is 5 bit code groups from link transmission and reception, 4 bit code groups are just used at the MII interface of having arrived between PHY and the MAC, and do not have the device or the circuit of MAC layer here.On the direction that receives, the 5B code character is extracted the clock signal of being carried from one PHY chip out through the clock signal extraction circuit, just the 5B code character is circulated and gives the PHY chip of other end.On the direction that sends, then just the clock signal extraction circuit is changed into clock signal and insert circuit.Like this, for the existing equipment that does not prop up the hold clock signal lift-launch, as long as such transponder of serial connection is just passable on its Ethernet interface.Device A among Fig. 6 has realized method of the present invention, is that a hold clock signal is carried; But B is existing equipment, does not prop up hold clock signal and carries; On the Ethernet interface of B, be connected in series such transponder for this reason, made equipment B both can obtain the clock signal of being carried, and don't must change original Ethernet interface by transponder.For B, this transponder just looks like to be the filter of clock signal.Conversely, equipment B also can be by the transponder loading clock signal.If device A also is not prop up the existing equipment that hold clock signal is carried, on the Ethernet interface of A, also should be connected in series such transponder so.

Because the speed of Ethernet is very high, the method for the invention should be realized with circuit with hardware mode.Specifically can adopt the ready-made PHY chip of supporting the PCSBP pattern to add that " programmable logic array " is that fpga chip is realized, clock signal insertion circuit, clock signal extraction circuit, 4Bto5B change-over circuit, 5Bto4B change-over circuit are all realized by fpga chip.The Am79c874 of U.S. AMD is exactly an Ethernet PHY chip of supporting the PCSBP pattern, below just enforcement of the present invention is described as example.

In actual use, the physical layer function of transmitting terminal and receiving terminal is always provided by same PHY chip, has for example just comprised a receiving terminal PHY and a transmitting terminal PHY in the Am79c874 chip.Corresponding therewith, clock signal insertion/extraction, the 4Bto5B/5Bto4B circuit of transmitting terminal and receiving terminal also all should integrate, and specifically can be implemented in the fpga chip.

As mentioned above, the 4Bto5B of transmitting terminal and clock signal insertion circuit can be skipped under the control of a switching value.If skip, entire circuit just only remaining ethernet physical layer chip PHY also in action, so just be equal to the transmitting terminal of normal ethernet physical layer PHY this moment.Equally, the 5Bto4B of downstream receiving terminal and clock signal extraction circuit also can be skipped under the control of a switching value, if skip, entire circuit just only remaining ethernet physical layer chip PHY also in action, so just be equal to the receiving terminal of normal ethernet physical layer PHY this moment.

Like this, transmit clock signal just enables the 4Bto5B and the clock signal of upstream and insert circuit, and the clock signal in downstream extracts and the 5Bto4B circuit if desired.If do not need transmit clock signal, then can not enable these adjunct circuits, be conventional ethernet communication fully like that.But, do not insert circuit even if transmitting terminal is not skipped 4Bto5B and clock code character, as long as in fact there is not the clock pulse input, that its signal that sends just is equal to is conventional, the ethernet signal of loading clock signal not; And receiving terminal as long as do not have loading clock signal in the received signal, does not just have clock pulse output naturally yet.

No matter loading clock signal whether, always the MII interface of the standard that MAC saw, the transmission of clock signal then is fully transparent.On the other hand, if do not support the conventional downstream node of our bright method to dock with one the upstream node of supporting our bright method, and upstream node is loading clock signal in the signal that sends, downstream node can not extract clock pulse certainly so, yet this moment, downstream node thought that just the quality of link descends to some extent, seen some these code characters that should not see because of error code takes place, but this ethernet link still meets 802.3 standards over all.Certainly, this might cause the rising of packet loss.Therefore the packet loss that the comes flagrant words that rise can be notified upstream node if feel, allow it close clock signal and carry and get final product.

The used ethernet medium of method supposition recited above is an optical fiber, does not therefore relate to " stirring (Scrambling) " of physical signalling.If on category 5 twisted pair, then need in insertion of clock code character and extraction circuit, increase and stir and go back primary circuit, sort circuit is similar to the CRC check circuit, and has provided its multinomial and circuit diagram in 802.3 standards, and is just needless to say more here.In fact, needing the general of loading clock signal all is the Ethernet that adopts optical fiber, because transmission range is not far when adopting category 5 twisted pair, it is not difficult to add a clock line specially yet.

Be that example illustrates enforcement of the present invention with the Am79c874 chip below, and provide the VHDL language false code description of main circuit.

One, 4Bto5B change-over circuit

entity?4Bto5B?is

port

(

MII_TX_CLK:in std_logic;--from Am79874,25MHz, the cycle is 40nS

MII_TX_ER: in std_logic;--from MII, see the Am79874 specification

MII_TXD: in std_logic_vector (3downto 0)--from MII, see the Am79874 specification

MII_TX_EN: in std logic; One from MII, and expression requires the data of transmission and TXD (3:0) effective

5B_out: out std_logic_vector (4 downto 0)--whereabouts CLK_insert

5B_EN: out std_logic;--whereabouts CLK_insert, expression begins to send

)；

end?4Bto5B；

Architecture?Body?of?4Bto5B?is

begin

process(MII_TX_EN)

Then--the rising edge of TX_EN overlaps with the trailing edge of TX_CLK if MII_TX_EN ' event and MII_TX_EN=' 1 '.

Wait on TX_CLK until TRX_CLK=' 1 ';--wait for the TX_CLK cycle half.

Wait on TX_CLK until TX_CLK=' 0 ';--wait for the TX_CLK cycle again half.

5B_EN=' 1 ';--RX_CLK cycle of whole 4Bto5B circuit delay.

end?if；

If MII_TX_EN ' event and MII_TX_EN=' 0 ' then--trailing edge also is the same.

wait?on?TX_CLK?until?TRX_CLK＝’1’；

wait?on?TX_CLK?until?TX_CLK＝’0’；

5B_EN＝’0’；

end?if；

end?process；

Process (MII_TX_CLK)--the beginning in individual TX_CLK cycle (40nS)

begin

if?MII_TX_CLK’event?and?MII?TX_CLK＝’1’and?MII_TX_EN＝1then

begin

if?MII_TX_ER＝’1’then

5B_out＜=" 00100 ";--send the ERR code character

else

case?5B_input?is

when″0000″＝>5B_out<＝″11110″；

when″0001″＝>5B_out<＝″01001″；

when″0010″＝>5B_out<＝″10100″；

when″0011″＝>5B_out<＝″10101″；

when″0100″＝>5B_out<＝″01010″；

when″0101″＝>5B_out<＝″01011″；

when″0110″＝>5B_out<＝″01110″；

when″0111″＝>5B_out<＝″01111″；

when″1000″＝>5B_out<＝″10010″；

when″1001″＝>5B_out<＝″10011″；

when″1010″＝>5B_out<＝″10110″；

when″1011″＝>5B_out<＝″10111″；

when″1100″＝>5B_out<＝″11010″；

when″1101″＝>5B_out<＝″11011″；

when″1110″＝>5B_out<＝″11100″；

when″1111″＝>5B_out<＝″11101″；

end?case；

end?if；

end?process；

end?Body；

Two, clock carries circuit (transmitting terminal)

entity?CLK_insert?is

generic

(

constant?IDLE_CODE?std_logic_vector(4downto?0):＝’11111’；

constant?SSD1_CODE?std_logic_vector(4downto?0):＝’11000’；

constant?SSD2_CODE?std_logic_vector(4downto?0):＝’10001’；

constant?ESD1_CODE?std_logic_vector(4downto?0):＝’01101’；

constant?ESD2_CODE?std_logic_vector(4downto?0):＝’00111’；

constant?ER_CODE std_logic_vector(4downto?0):＝’00100’；

constant?CLK_CODE?std_logic_vector(4downto?0):＝’00101’；

)；

port

(

5B_in: in std_logic_vector (4downto 0)--from 4Bto5B.

5B_EN: in std_logic;--from 4Bto5B, expression starts transmission.

CLK_sig:in std_logic;--need the clock signal of lift-launch.

TX_CLK: in std_logic;--from Am79874,25MHz, the cycle is 40nS.

--Am79874 takes a sample to TXD, TX_ER and TX_EN at the rising edge of TX_CLK.

MII_TX_CLK:out std_logic;--whereabouts 5Bto4B and MII interface, MAC is driven by MII_TX_CLK.

TX_ER:out std_logic;--whereabouts Am79874, be equivalent to TXD (4), see the Am79874 specification

TXD: out std_logic_vector (3downto 0)--whereabouts Am79874 forms 5 bit vectors with TX_ER.

TX_EN:out std_logic;--whereabouts Am79874, the transmission of expression beginning PHY layer.

)；

end?CLK_insert；

Architecture?TX?of?CLK_insert?is

signal?CLK_req :std_logic；

signal?Blocking :integer?range?0to?5；

Signal TX_state: integer range 0to 5;--0=idle running.

--1=is ready for sending SSD1.

--2=has sent SSD1, is ready for sending SSD2.

--during the normal transmission of 3=

--after the trailing edge of 4=5B_EN, be ready for sending ESD1.

--5=has sent ESD1, is ready for sending ESD2.

begin

Process (CLK_sig)--need the clock signal of lift-launch.

begin

If CLK_sig ' event and CLK_sig=' 1 ' then--request is carried in the rising edge representative.

CLK_req<＝’1’；

If?TX_state＝0then

TX state＜=1;--be ready for sending SSD1.

end?if；

end?if；

end?process；

process(5B_EN)

Then--the rising edge of TX_EN overlaps with the trailing edge of TX_CLK if 5B_EN ' event and 5B_EN=' 1 '.

TX_state＜=1;--start transmission, so be ready for sending SSD1.

Wait on TX_CLK until TX_CLK=' 1 ';--wait for the TX_CLK cycle half.

Wait on TX_CLK until TX_CLK=' 0 ';--wait for the TX_CLK cycle again half.

TX_EN=' 1 ';--the rising edge of TX_EN has postponed a TX_CLK cycle than 5B_EN.

End if;--TX_EN has postponed two TX_CLK cycles altogether than MII_TX_EN like this.

if?5B_EN’event?and?5B_EN＝’0’then

TX_state＜=4;--finish to send, so be ready for sending ESD1.

Wait on TX_CLK until TX_CLK=' 1 ';--wait for the TX_CLK cycle half.

Wait on TX_CLK until TX_CLK=' 0 ';--wait for the TX_CLK cycle again half.

TX_EN=' 0 ';--the trailing edge of TX_EN has also postponed a TX_CLK cycle than 5B_EN.

end?if；

end?process；

Process (TX_CLK)--the TX_CLK from PHY can not get clogged.

begin

if?TX_CLK’event?and?TX_CLK＝1then

MII_TX_CLK＜=' 1 ';--rising edge does not need to block.

end?if；

if?TX_CLK’event?and?TX_CLK＝0and?Blocking＝0thenthen

MII_TX_CLK＜=' 0 ';--block a TX_CLK, it is just passable only to need to block its trailing edge.

end?if；

end?process；

Process (TX_CLK)--the beginning in a 40nS cycle.

variable?5B_out:std_logic_vector(4downto?0)＝IDLE_CODE；

begin

if?TX_CLK’evern?and?TX_CLK＝1then

case?TX_state?is

When 0=〉--just during spinning.

5B_out<＝IDLE_CODE；

When 1=〉--be ready for sending SSD1.

begin

if?CLK_req＝1then

CLK_req＜=' 0 ';--this request is responded.

Blocking＜=1;--block MII_TX_CLK

endif

5B_out<＝SSD1_CODE；

TX_state<＝2；

end；

When 2=〉--be ready for sending SSD2.

begin

5B_out<＝SSD2_CODE；

if?Blocking＝1?then

Blocking=Blocking+1;--so that distinguish the history of status change.

end?if；

TX_state<＝3；

end；

When 3=〉--normally send the phase.

begin

If Blocking〉1 then--the obstruction to MII_TX_CLK started in the idle running phase.

5B_out<＝CLK_CODE； --SSD1?SSD2?CLK

TX_state＜=4;--be ready for sending ESD1.

else

begin

If Blocking=1 then--the obstruction to MII_TX_CLK started in the transmission phase.

Blocking＜=0; So--as long as it is just much of that to block a MII_TX_CLK.

end?if；

if?CLK_req＝1?then

5B_out＜=CLK_ODE;--clock signal is inserted code character stream.

Blocking＜=1;--temporarily block the clock on the MII interface, make MAC postpone sending data.

CLK_req＜=' 0 ';--this request is responded.

else

5B_out＜=5B_in;--the transmission of normal data.

end?if；

If 5B_EN=' 0 ' then--finish to send, be ready for sending ESD1.

TX_state<＝4；

end?if

end；

end?if；

end；

When 4=〉--be ready for sending ESD1.

begin

5B_out<＝ESD1_CODE；

TX_state<＝5；

end；

When 5=〉--be ready for sending ESD2.

begin

5B_out<＝ESD2_CODE；

TX_state＜=0;--get back to idling conditions

Blocking＜=0;--finish to block MII_TX_CLK (if being in blocked state).

end；

end?case；

TXD<＝5B_out(3?downto?0)；

TX_ER<＝5B_out(4)；

end?if；

end?process；

end?TX；

Three, clock extraction circuit (receiving terminal)

entity?CLK_extract?is

generic

(

constant?IDLE_CODE?std_logic_vector(4?downto?0):＝’11111’；

constant?SSD1_CODE?std_logic_vector(4?downto?0):＝’11000’；

constant?SSD2_CODE?std_logic_vector(4?downto?0):＝’10001’；

constant?ESD1_CODE?std_logic_vector(4?downto?0):＝’01101’；

constant?ESD2_CODE?std_logic_vector(4?downto?0):＝’00111’；

constant?ER_CODE std_logic_vector(4?downto?0)?:＝’00100’；

constant?CLK_CODE?std_logic_vector(4?downto?0)?:＝’00101’；

)；

port

(

RX_ER:in std_logic;--from Am79874, be equivalent to RXD (4), see the Am79874 specification.

RXD: in std_logic_vector (3 downto 0)--from Am79874, form 5 bit vectors with RX_ER.

RX_DV: in std_logic;--from Am79874, expression receives code character stream.

RX_CLK: in std_logic;--from Am79874,25MHz, the cycle is 40nS.

MII_RX_CLK:out std_logic;--whereabouts 5Bto4B and MII interface.

MII_RX_ER:out std_logic;--whereabouts MII interface makes MAC can't see PHY because of receiving as clock signal

--illegal code character and the mistake reported.

5B_out: out std_logic_vector (4 downto 0)--whereabouts 5Bto4B

5B_DV: out std_logic;--whereabouts 5Bto4B, 5B_out is effective in expression.

CLK_out:out std_logic;--the clock signal of extraction

)；

end?CLK_extract；

Architecture?RX?of?CLK_extract?is

signal?5B_in :std_logic_vector(4?downto?0)；

signal?blocking:std_logic；

Signal RX_state:integer range 0 to 5;--0=idle running

--1=has received after the SSD1.

--2=has received after the SSD2.

--3=has received normal code character later at SSD2 or CLK.

--4=has received CLK later at SSD2.

--5=has received ESD1.

begin

process(RX_DV)

Then--the rising edge of RX_DV overlaps with the trailing edge of RX_CLK if RX_DV ' event and RX_DV=' 1 '.

Wait on RX_CLK unti1 RX_CLK=' 1 ';--wait for the RX_CLK cycle half.

Wait on RX_CLK until RX_CLK=' 0 ';--wait for the RX_CLK cycle again half.

5B_DV=' 1 ';--in 5Bto4B, also to postpone a RX_CLK cycle again,

End if;--postpone two RX_CLK cycles so altogether.

if?RX_DV’event?and?RX_DV＝’0’then

Wait on RX_CLK until RX_CLK=' 1 ';--trailing edge also is the same.

wait?on?RX_CLK?until?RX_CLK＝’0’；

5B_DV＝’0’；

end?if；

end?process；

Process (RX_CLK)--the beginning in a 40nS cycle.

variable?5B?in:std_logic_vector(4?downto?0):＝IDLE_CODE；

begin

if?RX_CLK’event?and?RX_CLK＝’1’and?RX_DV＝1?then

begin

5B_in(3?downto?0)<＝RXD；

5B_in(4)<＝RX_ER；

CLK_out<＝’0’；

if?5B_in/＝CLK_CODE?then

5B_out＜=5B_in;--interception CLK CODE does not allow enter the 5Bto4B circuit.

end?if；

case?RX_state?is

When 0=〉--just during spinning.

begin

blocking<＝’1’；

If 5B_in=SSD1_CODE then--be the boundary alignment of assurance lift-launch in the clock signal hyte of idle running phase,

RX_state＜=1;--specially before and after CLK_CODE, add SSD and ESD, so

End if;--the idle running phase CLK_CODE can directly not occur.But this is also nonessential.

end；

When 1=〉--received SSD1.

begin

if?5B_in＝SSD2_CODE?then

RX_state<＝2；

else

--ERROR?Condition

end?if；

end；

When 2=〉--received SSD2.

begin

if?5B_in＝CLK_CODE?then

CLK_out＜=' 1 ';--the pulse duration of CLK_out is approximately the cycle of a RX_CLK, promptly about 40nS.

RX_state<＝4；

Else--the normal code character that receive this moment should be PREAMBLE (1010) or SFD (1011).

blocking<＝0；

RX_state<＝3；

5B_DV＜=1;--the code character of SSD back is not CLK_CODE, and this may be the beginning of a frame,

End if;--should be leading code character or SFD in fact, see 802.3 the 22nd joints and 24 joints.

end；

When 3=〉--receive normal code character later at SSD2 or CLK, be in the normal take over period.

begin

if?5B_in＝CLK_CODE；

Blocking＜=1;--extract CLK_CODE out,, the MAC layer is suspended receive so block RX_CLK.

CLK_out<＝‘1’；

else

blocking<＝?‘0’；

end?if；

if?5B_in＝ESD1?then

5B_DV＜=' 0 ';--close 5B_DV.

RX_state<＝5；

end?if；

end；

When 4=〉--having received CLK later at SSD2 or CLK, might be SSD CLK ESD sequence.

begin

If 5B_in=ESD1 then--be SSD CLK ESD sequence really.

RX_state<＝5；

else

RX_state＜=3;--after SSD and the CLK_CODE is not ESD, and this is a normal frame,

5B_DV＜=1;--just CLK just in time has been inserted in the SSD back.Open 5B_DV.

blocking<＝‘0’；

end?if；

end；

When 5=〉--received ESD1.

begin

if?5B_in＝ESD2?then

RX_state<＝0；

else

--ERROR?Condition

end；

end?if；

end?process；

end?RX；

In the superincumbent false code, beginning of frame or " SSD CLK ESD " sequence and end are that arrival with SSD1 and ESD1 is a basis for estimation, but some PHY chip is not because perhaps the reason of specific implementation submits SSD and ESD code character to the upper strata, can use the level of RX_DV instead as basis for estimation this moment, exactly top " if 5B_in=ESD1 then " made into " if RX_DV=0 then ", the rest may be inferred by analogy.Obviously, this also belongs to concrete realization details.

Four, 5Bto4B

entity?5Bto4B?is

generic

(

constant?PREANBLE?std_logic_vector(3?downto?0):＝’1010’；

constant?SFD_CODE?std_logic_vector(3?downto?0):＝’1011’；

)；

port

(

5B_in: in std_logic_vector (4 downto 0)--come white CLK_extract.

5B_DV: in std_logic;--from CLK_extract, 5B_in is effective in the expression input.

RX_CLK: in std_logic;--from Am79874,25MHz, the cycle is 40nS.

MII_RX_CLK:out std_logic;--whereabouts MII, 25MHz, the cycle is 40nS.

MII_RX_ER: out std_logic;--whereabouts MII, see the Am79874 specification.

MII_RXD: out std_logic_vector (3 downto 0)--whereabouts MII, see the Am79874 specification.

MII_RX_DV: out std_logic;--whereabouts MII, the data of expression RXD (3:0) are effective.

)；

end?5Bto4B；

Architecture?Body?of?5Bto4B?is

begin

process(5B_DV)

Then--the rising edge of 5B_DV is consistent with the trailing edge of RX_CLK for if 5B_DV ' event and 5B_DV=' 1 '.

Wait on RX_CLK until RX_CLK=' 1 ';--wait for the RX_CLK cycle half.

Wait on RX_CLK until RX_CLK=' 0 ';--wait for the RX_CLK cycle again half.

MII_RX_DV=' 1 ';--the rising edge of MII_RX_DV is still consistent with the trailing edge of RX_CLK.

End if;--together with the extract circuit, postponed two RX_CLK cycles altogether.

if?5B_DV’event?and?5B_DV＝’0’then

wait?on?RX_CLK?until?RX_CLK＝’1’；

Wait on RX_CLK until RX_CLK=' 0 ';--trailing edge also is the same.

MII_RX_DV＝’0’；

end?if；

end?process；

Process (RX-CLK)--the beginning in a 40nS cycle

begin

if?RX_CLK’event?and?RX_CLK＝’1’and?5B_DV＝1?then

begin

if?5B_input＝″00100″then

MII_TX_ER<＝’1’；

else

MII_TX_ER<＝’0’；

end?if；

case?5B_input?is

when″11110″＝>MII_RXD<＝″0000″；

when″01001″＝>MII_RXD<＝″0001″；

when″10100″＝>MII_RXD<＝″0010″；

when″10101″＝>MII_RXD<＝″0011″；

when″01010″＝>MII_RXD<＝″0100″；

when″01011″＝>MII_RXD<＝″0101″；

when″01110″＝>MII_RXD<＝″0110″；

when″01111″＝>MII_RXD<＝″0111″；

when″10010″＝>MII_RXD<＝″1000″；

when″10011″＝>MII_RXD<＝″1001″；

when″10110″＝>MII_RXD<＝″1010″；

when″10111″＝>MII_RXD<＝″1011″；

when″11010″＝>MII_RXD<＝″1100″；

when″11011″＝>MII_RXD<＝″1101″；

when″11100″＝>MII_RXD<＝″1110″；

when″11101″＝>MII_RXD<＝″1111″；

end?case；

end?if；

end?process；

end?Body；

As for the realization of transponder, then, just constituted the passage of a direction as long as clock extraction circuit or clock are inserted transmitting terminal or the receiving terminal that circuit is connected to another side PHY chip.Whole transponder then is formed by stacking by two such passages, and whole transponder inserts circuit by two PHY chips, a clock signal extraction circuit and a clock signal and constitutes.More particularly, be exactly:

● the receiving terminal output of PHY chip A is connected to the input of clock signal extraction circuit;

● the output of clock signal extraction circuit is connected to the transmitting terminal input of PHY chip B, has just constituted the passage of a direction.

● the receiving terminal output of PHY chip B is connected to the input that clock signal is inserted circuit;

● the output that clock signal is inserted circuit is connected to the transmitting terminal input of PHY chip B, has just constituted reverse passage.

As a kind of concrete enforcement, some details of above-mentioned each circuit are not unique, and can change to some extent or optimize, but the difference of details does not influence essence of the present invention.

Claims (6)

1. the method for a loading clock signal on ethernet link is characterized in that:

(1.1) by 802.3 standard definitions be select in the illegal 5B code character and predetermined one of them as clock signal code character CLK;

When (1.2) needing loading clock signal, transmit leg inserts preset clock signal code character CLK in the 5B code character stream that is sent;

(1.3) recipient then check each the 5B code character in the 5B code character that the receives stream, when detecting preset clock signal code character CLK, just from code character flows, take out this clock signal code character CLK and export clock pulse.

2. according to the described method of on ethernet link, carrying clock sync signal of claim 1, it is characterized in that:

(2.1), the clock signal of transmit leg carries circuit, on the basis of original MAC and PHY chip or circuit, increases clock signal and inserts circuit and two parts of 4B/5B transducer, is used to realize the main operating process of transmit leg:

(2.1.1), for passing through the MII interface, paying the 4B hyte that the PHY layer sends by MAC, convert the 5B code character to by the 4B/5B transducer earlier;

If (2.1.2) do not insert the request of clock signal, just this 5B code character is handed to the PHY chip that is in the PCSBP pattern and supply to send; And get back to previous step;

If (2.1.3) request of inserting clock signal is arranged, but current 5B code character is one of back in must two 5B code characters of running fire, just wouldn't show interest in the request of this insertion clock signal;

(2.1.4) otherwise, just:

A) elder generation cuts off the tranmitting data register pulse TX_CLK on the MII interface, MAC is suspended to the PHY layer pay the 4B hyte;

B) will represent the 5B code character CLK of clock signal to consign to the PHY chip confession transmission that is in the PCSBP pattern, and remove the request of inserting clock signal;

C) the tranmitting data register pulse TX_CLK on the recovery MII interface makes MAC continue to pay the 4B hyte to the PHY layer;

(2.1.5), get back to the first step;

(2.2), the recipient on the basis of original MAC and PHY chip or circuit, two parts of the clock signal extraction circuit of increase and 5B/4B transducer are used to realize recipient's main operating process:

(2.2.1), monitor each code character receive, compared with the preset clock signal code character;

If (2.2.2) find that the new 5B code character that arrives is the preset clock signal code character, with regard to the receive clock pulse RX_CLK on the temporarily disconnected MII interface, make MAC postpone reading in the 4B hyte from PHY, and the pulse of output corresponding clock;

(2.2.3) otherwise just things are as usual.

3. according to the described method of on ethernet link, carrying clock sync signal of claim 1, it is characterized in that: idle running interim with " SSD1, SSD2, CLK, ESD1, ESD2 " 5B code character sequence as preset clock signal, TX_CLK clock pulse when need inserting clock signal on the transmit leg temporarily disconnected MII interface waits to send this 5B code character sequence and give recovery later on again.

4. according to claim 1 or 2 or 3 described methods of carrying clock sync signal on ethernet link, it is characterized in that: the predetermined clock signal that inserts 5B code character stream can be single 5B code character code character CLK, also can be the combination of CLK and several predetermined 5B code characters.

5. according to claim 1 on ethernet link the method for loading clock signal make up the method for ethernet repeater, it is characterized in that:

5.1) two ethernet physical layer PHY chip A and B that support the PCSBP patterns of use;

5.2) output of the receiving terminal of A is connected to the input of described clock signal extraction circuit;

5.3) the 5B code character of described clock signal extraction circuit is exported the transmitting terminal input that is connected to B, just constituted a unidirectional passage;

5.4) output of the receiving terminal of B is connected to the circuit of described clock signal method for loading;

5.5) the 5B code character of described clock signal lift-launch circuit is exported the transmitting terminal input that is connected to A, just constituted a reverse passage;

5.6) lump together by described positive and negative two passages and to constitute an ethernet repeater that can carry, extract, filter clock signal.

6. according to the method for the described structure ethernet repeater of claim 5, it is characterized in that: the clock signal that extracts with in addition frequency stabilization of phase-locked loop, is carried clock signal at transmit leg from this phase-locked loop.

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