CN101119136A

CN101119136A - Method and device for obtaining essential parameter of circuit

Info

Publication number: CN101119136A
Application number: CNA2006101038637A
Authority: CN
Inventors: 晋兆国; 李胜
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2006-08-04
Filing date: 2006-08-04
Publication date: 2008-02-06
Anticipated expiration: 2026-08-04
Also published as: CN101119136B

Abstract

The invention discloses a method and a device for acquiring basic parameter of a circuitry. The method contains the steps as follows: a digital signal processor DSP controls a signal generator SG to generate test signals of a frequency 1 and a frequency 2; sampling unit respectively samples the sampling voltages under the frequency 1 and the frequency 2, and then provides the sampling voltages to the DSP; the DSP obtains the vector ratios under the sampling voltages of the first frequency and the second frequency, thus the DSP obtains a Z parameter and then obtains the basic parameter of a circuitry. The method and the device provided by the invention can obtain the basic parameter of a circuitry, so as to realize the frequency responding measurement of the circuitry.

Description

Method and device for acquiring basic parameters of line

Technical Field

The present invention relates to the field of line evaluation, and in particular, to a method and an apparatus for obtaining basic line parameters.

Background

In the field of telecommunication Services, operators provide broadband telecommunication Services and narrowband telecommunication Services to users simultaneously through cables, such as Plain Old Telephone Service (POTS) adding Asymmetric Digital Subscriber Line (ADSL) over POTS), integrated Services Digital Network (ISDN) adding ADSL (ADSL over ISDN), and Plain Telephone adding Very High Speed Digital Subscriber line (VDSL (Very High Speed DSL) over POTS), which are Very popular both in China and abroad. Hereinafter, the DSL, VDSL, and the like are collectively referred to as an x Digital Subscriber line (xDSL).

Fig. 1 shows a schematic diagram of a service implementation principle for simultaneously providing a broadband telecommunication service and a narrowband telecommunication service in the prior art: the xDSL signal and the POTS/ISDN signal coexist in an outside line of a user, at the side of a local end, a Separator (SPL) in broadband access equipment (DSLAM) firstly distinguishes broadband service from narrow-band service, then sends broadband service data to a broadband service board, such as an xDSL service board, for processing, and sends narrow-band service data to a narrow-band service board, such as a POTS/ISDN service board, for processing; at the user end, the SPL located in the user end device sends the separated broadband service data to a Remote subscriber Unit (RTU) for processing, and sends the narrowband service data to the phone for processing.

In the operation and maintenance process of the above services, if a user declares a fault, it is often necessary to measure a subscriber line parameter, which may be a line voltage parameter, a line resistance parameter, a line capacitance parameter, a line frequency response, a line background noise, a line-to-ground balance, and the like. From these parameters, the quality of the line and the fault conditions, such as mixed line, broken line and short circuit, can be determined. The type of fault is used to automatically determine what kind of job needs to be dispatched to repair the fault, and the broadband line testing module shown in fig. 1 realizes the parameter testing functions.

The frequency response test of the line is an important function in the broadband test module, the frequency response is an important parameter in the broadband line test, and the broadband service rate which can be opened by the line can be accurately estimated according to the frequency response of the broadband service frequency band of the line and the background noise of the expanded service frequency band of the line. Single-ended line frequency response testing is also a difficulty in broadband line testing. Currently, most of the line frequency response tests are implemented by using the principle based on Time Domain Reflection (TDR).

Fig. 2 shows a schematic diagram of TDR implementation principle in the prior art: transmitting a main frequency voltage V to the cable at the local side _s A typical value of 300 kilohertz (KHz) of the primary frequency of the pulse, which is transmitted from the source end of the cable to the termination end of the cable, will be totally reflected back if the termination end of the cable is open or short circuited, and the reflected pulse is returned back to the source end of the cable. If the main frequency voltage of the pulse reflected back to the source is V _f Then the insertion loss of the cable to the main frequency voltage is obtained

Wherein, the first and the second end of the pipe are connected with each other,

the energy unit watts (W) is converted to DB, multiplied by 0.5, due to the signal being attenuated by twice the length of the cable.

Although the insertion loss is calculated by adopting a TDR mode, the test method has a black box effect, can reflect the insertion loss of the cable more objectively, and has higher test precision under the conditions that the cable is not very long, for example, the length of the cable is less than 3000 meters, and the terminal of the cable is open-circuited or short-circuited; however, there are many disadvantages to calculating the insertion loss using the TDR method. Because the tested pulse needs to go through twice the length of the cable to return to the data collector at the local side, when the cable is longer, the amplitude of the reflected pulse of the tested pulse is smaller, so that the test becomes very difficult. For example, the length of the tested cable is 4000 meters, the diameter of the cable is 0.4 millimeter, the main frequency component is a pulse of 300KHz attenuated by 14DB per kilometer, the pulse is attenuated by 56DB from the cable source end to the cable terminal, the pulse is transmitted to the cable source end after being totally reflected by the cable terminal, and is attenuated by 56DB again, and the total attenuation is 112DB; reflected pulses of very small amplitude are difficult to test accurately, given the presence of noise in the test environment. In addition, when the cable termination is in the matching state, the pulses transmitted from the cable source to the cable termination are all absorbed by the matching load, and basically no reflected pulses return to the cable source, so that it is not feasible to calculate the insertion loss by using the TDR method.

Disclosure of Invention

In view of this, an object of the present invention is to provide a method for obtaining basic parameters of a line, which can obtain the basic parameters of the line to implement a frequency response test of the line.

Another objective of the present invention is to provide an apparatus for obtaining basic parameters of a line, which is capable of obtaining the basic parameters of the line to implement a frequency response test of the line.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a method of obtaining line base parameters, the method comprising:

the DSP controls the signal generator SG to generate test signals of a first frequency and a second frequency, and the sampling unit samples sampling voltages under the first frequency and the second frequency respectively and provides the sampled sampling voltages for the DSP;

the DSP obtains a vector ratio of the sampling voltage under the first frequency and a vector ratio of the sampling voltage under the second frequency, and obtains a Z parameter according to the vector ratios;

and the DSP acquires the basic circuit parameters according to the Z parameters.

The method further comprises the following steps:

the circuit is disconnected, the DSP controls the SG to generate test signals of a first frequency and a second frequency, the sampling unit respectively samples calibration sampling voltages under the first frequency and the second frequency, and the sampled calibration sampling voltages are provided for the DSP;

the DSP obtains a vector ratio of the calibration sampling voltage under a first frequency and a vector ratio of the calibration sampling voltage under a second frequency of the access line;

the DSP obtaining the Z parameter according to the obtained vector ratio comprises: and acquiring the Z parameter according to the vector ratio of the calibration sampling voltage under the first frequency and the vector ratio of the calibration sampling voltage under the second frequency, and the vector ratio of the sampling voltage under the first frequency and the vector ratio of the sampling voltage under the second frequency.

The vector ratio obtained by the DSP is obtained by calculation through a Fast Fourier Transform (FFT) algorithm.

The basic parameters of the acquired line are as follows: the inductance of the line, the resistance of the line and the capacitance of the line.

The method further comprises the following steps:

and after the obtained Z parameter is used for correcting the calculated basic parameter to obtain the parameter of the line, obtaining the frequency response of the line according to the corrected parameter of the line.

The method further comprises the following steps: and comparing the acquired frequency response of the line with a frequency response standard to obtain the aging condition of the line.

A device for obtaining basic circuit parameters comprises a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a logic unit, a Signal Generator (SG) and a sampling unit, wherein the CPU is connected with the DSP, the DSP is connected with the logic unit, the signal generator is connected with the logic unit, the sampling unit is respectively connected with the logic unit, a signal emitter and the DSP,

the CPU is used for informing the DSP to carry out line test;

the DSP is used for informing the logic unit to send a test signal and sample according to the test notice of the CPU, and acquiring the basic parameters of the tested circuit according to the data provided by the sampling unit;

the logic unit is used for controlling the SG to generate a test signal and then controlling the sampling unit to sample; the SG is used for generating a test signal according to the control of the logic unit and sending the test signal to the sampling unit;

the sampling unit is used for receiving the test signal from the SG, sampling according to the control of the logic unit and then providing the sampled data for the DSP.

And the DSP is further used for acquiring the frequency response of the tested line according to the acquired basic parameters of the tested line.

The device also comprises an output display unit connected with the CPU, wherein the CPU is used for receiving the data provided by the DSP and providing the data to the output display unit; the output display unit is used for displaying data from the CPU.

The sampling unit comprises a linear filter LF, an analog/digital converter AD, a random access memory RAM, a relay, a sampling relay switch, a current sampling resistor and a grounding resistor,

where LF is used for linear filtering and AD is used for conversion between analog and digital quantities.

The RAM is a Static Random Access Memory (SRAM).

According to the scheme, the device for acquiring the basic parameters of the line is arranged, the device is adopted to measure the line to be measured, and the basic parameters of the line are calculated, so that the frequency response of the line is obtained. The device and the system provided by the invention are not influenced by the length of the line when the basic parameters are obtained, are accurate and stable, and solve the problems that the attenuation test of the long line is inaccurate by adopting a TDR method and the attenuation test is inaccurate when the terminal is matched in the prior art.

Drawings

Fig. 1 is a schematic diagram illustrating a service implementation principle of simultaneously providing a broadband telecommunication service and a narrowband telecommunication service in the prior art;

FIG. 2 is a schematic diagram of TDR implementation in the prior art;

FIG. 3A is a schematic diagram of a basic parametric model of a measured line;

FIG. 3B shows a two-port network model schematic of a baseline parametric model of the line under test;

FIG. 4 is a schematic diagram of an apparatus for obtaining basic line parameters according to the present invention;

FIG. 5 is a flow chart illustrating the basic line parameter acquisition according to the present invention;

fig. 6 shows a transmission line parametric model diagram of the inventive line.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the accompanying drawings.

For a tested line such as a communication cable, the low frequency circuit model of the cable can be equivalent to the model shown in fig. 3A from the local side, and the basic parameters of the circuit model of the tested line include R ₁ 、R ₂ 、 C ₁ 、C ₂ 、G ₁ 、G ₂ And Z, wherein R ₁ Is A line resistance, R ₂ Is a B line resistance, R ₁ And R ₂ In ohms; c ₁ Is the capacitance of A line to ground, C ₂ Is the capacitance of B line to ground, C ₁ And C ₂ Unit of (d) is farad; g ₁ For A line to ground conductance, G ₂ For B line to ground conductance, G ₁ And G ₂ Unit of (a) is siemens; z is the termination impedance in ohms, and these parameters may be referred to as primary parameters; then deducing the frequency response of the circuit according to the circuit model of the tested circuit, wherein the frequency response can also be called as a secondary parameter; and finally, correcting and mapping the basic parameters of the circuit model according to the deduced frequency response of the circuit to obtain the frequency response of the tested circuit.

Considering a two-port network model of the basic parameter model of the tested line at one of the ports of the tested line, as shown in fig. 3B, the two-port network model can be obtained according to the definition of Z matrix parameters:

thus, the values of the elements of the Z matrix are obtained as follows:

according to the circuit model of fig. 3A, when the frequency is w, the values of the elements of the Z matrix of the two-port network are:

as can be seen in FIG. 3A, due to Z ₁₂ ≡Z ₂₁ Therefore, among the four element values of the Z matrix, only three of them can be used to establish an equation. Without loss of generality, select Z ₁₁ 、Z ₂₁ And Z ₂₂ To establish an equation. Thus at frequencies w ₁ And w ₂ Then, the following 6 equations can be obtained:

first of all, it is necessary to obtain Z ₁₁ 、Z ₂₁ 、Z ₂₂ 、Z ₁₁ ′、Z ₂₁ ' and Z ₂₂ These six parameters can then be followed by Z ₁₁ 、Z ₂₁ 、Z ₂₂ 、Z ₁₁ ′、Z ₂₁ ' and Z ₂₂ ', obtaining a basic line parameter R ₁ 、R ₂ 、C ₁ 、C ₂ 、G ₁ 、G ₂ And Z. To obtain Z ₁₁ 、Z ₂₁ 、Z ₂₂ 、Z ₁₁ ′、Z ₂₁ ' and Z ₂₂ ', and according to Z ₁₁ 、Z ₂₁ 、Z ₂₂ 、Z ₁₁ ′、Z ₂₁ ′ And Z ₂₂ ' obtaining line fundamental parameter R ₁ 、R ₂ 、C ₁ 、C ₂ 、G ₁ 、G ₂ And Z, the present invention provides a device for acquiring basic parameters of a line, which comprises a Central Processing Unit (CPU), a number, as shown in FIG. 4The device comprises a signal processor (DSP), a logic unit, a Signal Generator (SG) and a sampling unit, wherein a CPU is connected with the DSP, the DSP is connected with the logic unit, the signal generator is connected with the logic unit, and the sampling unit is respectively connected with the logic unit, a signal transmitter and the DSP. After the device is normally loaded, the CPU is used for informing the DSP to carry out line test; the DSP is used for informing the logic unit to send a test signal and sample according to the test notice of the CPU, and acquiring the basic parameters of the tested circuit according to the data provided by the sampling unit; the logic unit is used for controlling the SG to generate a test signal and then controlling the sampling unit to sample; the SG is used for generating a test signal according to the control of the logic unit and sending the test signal to the sampling unit; the sampling unit is used for receiving the test signal from the SG, sampling according to the control of the logic unit and then providing the sampled data for the DSP. The test signal may be a sine wave, a square wave, a modulated wave, etc. The DSP is further used for acquiring the frequency response of the tested line according to the acquired basic parameters of the tested line. The device can further comprise an output display unit connected with the CPU, and the CPU is further used for receiving the data provided by the DSP and providing the data to the output display unit; the output display unit is used for displaying data from the CPU.

In the invention, the sampling unit comprises a Linear Filter (LF), an analog-to-digital converter (AD), a Random Access Memory (RAM), a relay, a sampling relay switch, a current sampling resistor and a grounding resistor, wherein the LF is used for performing linear filtering, and the AD is used for converting between analog quantity and digital quantity. The RAM may be a Static Random Access Memory (SRAM).

In a specific implementation, in order to sample two test signals generated by the SG, the sampling unit includes two LFs, two ADs, two RAMs, six relays, two sampling relay switches, one current sampling resistor and two ground resistors.

The following describes a specific implementation process of the apparatus for acquiring basic parameters of a line. According to FIG. 4, Z can be seen ₁₁ 、Z ₁₂ 、Z ₂₁ And Z ₂₂ Are respectively as

Therefore, only four vectors are needed to be calculated to further obtain the basic parameters of the tested line, and the four vectors are I ₂ When =0

And

I ₁ when =0

Andi.e. I ₂ V at =0 _a1 And V ₂₁ ， I ₁ V when =0 _a2 And V ₁₂ 。

Since the line resistance is much smaller than the capacitive reactance, the solution is very difficult; each vector comprises two components of amplitude and phase, and practice shows that

Andthe amplitude or phase errors of the four vectors cannot meet the requirement on precision within one thousandth, the voltage error within one thousandth is difficult to avoid in time domain noise, and the amplitude and phase errors can be caused in the design of a Printed Circuit Board (PCB), so that accurate amplitude and phase errors can be obtained only by adopting a special algorithm and a special implementation process

Andtherefore, two key methods are adopted to ensure the practicability of hardware, the amplitudes and phases of four vectors are obtained by Fast Fourier Transform (FFT) on sampling data, the influence caused by time domain noise is avoided by the frequency domain processing mode, very high precision can be achieved, and the practical requirement can be completely met; the inherent amplitude attenuation and phase delay of the channel are corrected.

Simultaneous acquisition of V by AD sampling _a And V ₁ Or V _a And V ₂ Or V ₁ And V ₂ The FFT is performed on the discrete sequence to obtain a frequency domain sequence thereof, and then the position of the excitation signal is found in the frequency domain sequence, the ratio of the amplitudes corresponding to the two sequences is the amplitude of the required vector, and the phase difference corresponding to the two sequences is the phase of the required vector.

Fig. 5 shows a flow chart of obtaining basic parameters of a line in the present invention, and corresponding to fig. 4, an implementation process of obtaining the basic parameters of the line includes the following steps:

open line calibration phase

Step 501: CPU controlled relay switch K ₁ 、K ₂ Closed, and a relay switch K ₆ 、K ₇ Switch K of AD sampling relay is disconnected and controlled ₄ Contact point a, K ₅ And contacting the point b.

Step 502: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₁ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, the AD is started to sample,obtaining N point sampling data V _{a_cor_w1} And V _{1_cor_w1} And the AD sends the sampled data to the SRAM for storage.

Step 503: DSP detects AD and accomplishes N some sampled data V _{a_cor_w1} And V _{1_cor_w1} After sampling, the SRAM stored N point sampling data V _{a_cor_w1} And V _{1_cor_w1} Get to the cache inside the DSP for data processing, i.e. the DSP processes V _{a_cor_w1} And V _{1_cor_w1} FFT is respectively carried out to obtain two new N point sequences V _{aw_cor_w1} And V _{1w_cor_w1} . Through V _{aw_cor_w1} And V _{1w_cor_w1} Determining the frequency as w ₁ Vector ratio of test signals

Wherein

V _{aw_cor_w1} (k) Is a V _{aw_cor_w1} The kth element in the sequence, V _{1w_cor_w1} (k) Is a V _{1w_cor_w1} The kth element in the sequence.

Step 504: CPU controlled relay switch K ₁ 、K ₂ 、K ₃ Closed, and a relay switch K ₆ 、 K ₇ Switch K of AD sampling relay is disconnected and controlled ₄ Point b of contact, K ₅ And contacting the point b.

Step 505: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₁ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{1_cor_w1} And V _{2_cor_w1} And the AD sends the sampled data to the SRAM for storage.

Step 506: DSP detects AD and accomplishes N some sampled data V _{1_cor_w1} And V _{2_cor_w1} After sampling, the SRAM stored N-point sampling data V _{1_cor_w1} And V _{2_cor_w1} Get to the cache inside the DSP for data processing, i.e. the DSP processes V _{1_cor_w1} And V _{2_cor_w1} FFT is respectively carried out to obtain two new N point sequences V _{1w_cor_w1} And V _{2w_cor_w1} . Through V _{1w_cor_w1} And V _{2w_cor_w1} Determining the frequency as w ₁ Of the test signalVector ratio

Wherein

V _{1w_cor_w1} (k) Is a V _{1w_cor_w1} The kth element in the sequence, V _{2w_cor_w1} (k) Is a V _{2w_cor_w1} The kth element in the sequence.

Step 507: CPU control relay switch K ₈ 、K ₉ Closing, discharging the circuit, and after the discharging is finished, controlling a relay switch K by the CPU ₈ 、K ₉ And (5) disconnecting.

Step 508: CPU controlled relay switch K ₁ 、K ₃ Closed, and a relay switch K ₆ 、K ₇ Switch K of AD sampling relay is disconnected and controlled ₄ Contact point a, K ₅ And contacting the point a.

Step 509: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₁ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{a_cor_w1} And V _{2_cor_w1} And the AD sends the sampled data to the SRAM for storage.

Step 510: DSP detects AD and accomplishes N some sampled data V _{a_cor_w1} And V _{2_cor_w1} After sampling, the SRAM stored N point sampling data V _{a_cor_w1} And V _{a_cor_w1} Get to the cache inside the DSP for data processing, i.e. the DSP processes V _{a_cor_w1} And V _{2_cor_w1} FFT is respectively carried out to obtain two new N point sequences V _{aw_cor_w1} And V _{2w_cor_w1} . Through V _{aw_cor_w1} And V _{2w_cor_w1} Determining the frequency as w ₁ Vector ratio of test signals

Wherein

V _{aw_cor_w1} (k) Is a V _{aw_cor_w1} The kth element in the sequence, V _{2w_cor_w1} (k) Is a V _{2w_cor_w1} The kth element in the sequence.

Step 511: CPU controlled relay switch K ₁ 、K ₂ Closed, and a relay switch K ₆ 、K ₇ Switch K of AD sampling relay is disconnected and controlled ₄ Contact point a, K ₅ And contacting the point b.

Step 512: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₂ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{a_cor_w2} And V _{1_cor_w2} And the AD sends the sampled data to the SRAM for storage.

Step 513: DSP detects AD and accomplishes N some sampled data V _{a_cor_w2} And V _{1_cor_w2} After sampling, the SRAM stored N point sampling data V _{a_cor_w2} And V _{1_cor_w2} Get to the cache inside the DSP for data processing, i.e. the DSP processes V _{a_cor_w2} And V _{1_cor_w2} FFT is respectively carried out to obtain two new N point sequences V _{aw_cor_w2} And V _{1w_cor_w2} . Through V _{aw_cor_w2} And V _{lw_cor_w2} Determining the frequency as w ₂ Vector ratio of test signals

Wherein

V _{aw_cor_w2} (k) Is a V _{aw_cor_w2} The kth element in the sequence, V _{1w_cor_w2} (k) Is a V _{1w_cor_w2} The kth element in the sequence.

Step 514: CPU controlled relay switch K ₁ 、K ₂ 、K ₃ Closed, and a relay switch K ₆ 、 K ₇ Switch K of AD sampling relay is disconnected and controlled ₄ Point b of contact, K ₅ And contacting the point b.

Step 515: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₂ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{1_cor_w2} And V _{2_cor_w2} And the AD sends the sampled data to the SRAM for storage.

Step 516: DSP detects AD and accomplishes N some sampled data V _{1_cor_w2} And V _{2_cor_w2} After sampling, the SRAM stored N point sampling data V _{1_cor_w2} And V _{2_cor_w2} Get to the cache inside the DSP for data processing, i.e. the DSP processes V _{1_cor_w2} And V _{2cor_w2} FFT is respectively carried out to obtain two new N point sequences V _{1w_cor_w2} And V _{2w_cor_w2} . Through V _{1w_cor_w2} And V _{2w_cor_w2} Determining the frequency as w ₂ Vector ratio of test signals of

Wherein

V _{1w_cor_w2} (k) Is a V _{1w_cor_w2} The kth element in the sequence, V _{2w_cor_w2} (k) Is a V _{2w_cor_w2} The kth element in the sequence.

517: CPU control relay switch K ₈ 、K ₉ Closing and laying the lineAfter the electricity is discharged, the CPU controls the relay switch K ₈ 、K ₉ And (5) disconnecting.

Step 518: CPU controlled relay switch K ₁ 、K ₃ Closed, and a relay switch K ₆ 、K ₇ Switch K of AD sampling relay is disconnected and controlled ₄ Contact point a, K ₅ And contacting the point a.

Step 519: CPU sends test command to DSP, DSP receives test command and informs logicThe editing unit sends test signals and sampling basic data, and the logic unit controls SG sending frequency to be w ₂ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{a_cor_w2} And V _{2_cor_w2} And the AD sends the sampled data to the SRAM for storage.

Step 520: DSP detects AD and accomplishes N some sampled data V _{a_cor_w2} And V _{2_cor_w2} After sampling, the SRAM stored N-point sampling data V _{a_cor_w2} And V _{2_cor_w2} Get to the cache inside the DSP for data processing, i.e. the DSP processes V _{a_cor_w2} And V _{2_cor_w2} FFT is respectively carried out to obtain two new N point sequences V _{aw_cor_w2} And V _{2w_cor_w2} . Through V _{aw_cor_w2} And V _{2w_cor_w2} Determining the frequency as w ₂ Vector ratio of test signals

Wherein

V _{aw_cor_w2} (k) Is a V _{aw_cor_w2} The kth element in the sequence, V _{2w_cor_w2} (k) Is a V _{2w_cor_w2} The kth element in the sequence.

Step 521: CPU control relay switch K ₁ 、K ₃ Open, and relay switch K ₂ 、K ₆ 、 K ₇ Closing and controlling AD sampling relay switch K ₄ Point a of contact、K ₅ And contacting the point b.

Step 522: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sample basic data, logic unit controls SG sending frequency as w ₁ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{a_w1} And V _{1_w1} And the AD sends the sampled data to the SRAM for storage.

Step 523: DSP detects AD and accomplishes N some sampled data V _{a_w1} And V _{1_w1} After sampling, the SRAM stored N point sampling data V _{a_w1} And V _{1_w1} Fetching into cache inside DSP for data processing, i.e. DSP for V _{a_w1} And V _{1_w1} FFT is respectively carried out to obtain two new N point sequences V _{aw_w1} And V _{1w_w1} . Through V _{aw_w1} And V _{1w_w1} Determining the frequency as w ₁ Vector ratio of test signals

Wherein

V _{aw_w1} (k) Is a V _{aw_w1} The kth element in the sequence, V _{1w_w1} (k) Is a V _{1w_w1} The kth element in the sequence.

Step 524: CPU controlled relay switch K ₁ 、K ₃ Open, and relay switch K ₂ 、K ₆ 、 K ₇ Closing and controlling AD sampling relay switch K ₄ Point b of contact, K ₅ And contacting the point b.

Step 525: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sample basic data, logic unit controls SG sending frequency as w ₁ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s Number of samplesIs N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{1_w1} And V _{2_w1} And the AD sends the sampled data to the SRAM for storage.

Step 526: n-point sampling data V after the DSP detects AD _{1_w1} And V _{2_w1} After sampling, the SRAM stored N point sampling data V _{1_w1} And V _{2_w1} Fetching into cache inside DSP for data processing, i.e. DSP for V _{1_w1} And V _{2_w1} FFT is respectively carried out to obtain two new N point sequences V _{1_w1} And V _{2w_w1} . Through V _{1w_w1} And V _{2w_w1} Determining the frequency as w ₁ Vector ratio of test signals

Wherein

V _{1w_w1} (k) Is a V _{1w_w1} The kth element in the sequence, V _{2w_w1} (k) Is a V _{2w_w1} The kth element in the sequence.

Access line test phase

Step 527: CPU controlled relay switch K ₈ 、K ₉ Closing, discharging the circuit, and after the discharging is finished, controlling a relay switch K by the CPU ₈ 、K ₉ And (5) disconnecting.

Step 528: CPU controlled relay switch K ₁ 、K ₂ Open, and relay switch K ₃ 、K ₆ 、 K ₇ Closing and controlling AD sampling relay switch K ₄ Contact point a, K ₅ And contacting the point a.

Step 529: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₁ The logic unit sends sampling basic data to the AD, and the sampling basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{a_w1} And V _{2_w1} AD will sampleAnd sending the data to the SRAM for storage.

Step 530: DSP detects AD and accomplishes N some sampled data V _{a_w1} And V _{2_w1} After sampling, the SRAM stored N point sampling data V _{a_w1} And V _{2_w1} Fetching into cache inside DSP for countingAccording to processes, i.e. DSP pairs V _{a_w1} And V _{2_w1} FFT is respectively carried out to obtain two new N point sequences V _{aw_w1} And V _{2w_w1} . Through V _{aw_w1} And V _{2w_w1} Determining the frequency as w ₁ Vector ratio of test signalsWherein

V _{aw_w1} (k) Is a V _{aw_w1} The kth element in the sequence, V _{2w_w1} (k) Is a V _{2w_w1} The kth element in the sequence.

Step 531: CPU controlled relay switch K ₁ 、K ₃ Open, and relay switch K ₂ 、K ₆ 、 K ₇ Closing and controlling AD sampling relay switch K ₄ Contact point a, K ₅ And contacting the point b.

Step 532: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₂ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{a_w2} And V _{1_w2} And the AD sends the sampled data to the SRAM for storage.

Step 533: DSP detects AD and accomplishes N some sampled data V _{a_w2} And V _{1_w2} After sampling, the SRAM stored N point sampling data V _{a_w2} And V _{1_w2} Fetching into cache inside DSP for data processing, i.e. DSP for V _{a_w2} And V _{1_w2} FFT is respectively carried out to obtain two new N point sequencesColumn V _{a_w2} And V _{1w_w2} . Through V _{aw_w2} And V _{1w_w2} Determining the frequency as w ₂ Vector ratio of test signalsWherein

V _{aw_w2} (k) Is a V _{aw_w2} The kth element in the sequence, V _{1w_w2} (k) Is a V _{1w_w2} The kth element in the sequence.

Step 534: CPU controlled relay switch K ₁ 、K ₃ Open, and a relay switch K ₂ 、K ₆ 、 K ₇ Closing and controlling AD sampling relay switch K ₄ Point b of contact, K ₅ And contacting the point b.

Step 535: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sample basic data, logic unit controls SG sending frequency as w ₂ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{1_w2} And V _{2_w2} And the AD sends the sampled data to the SRAM for storage.

Step 536: DSP detects AD and accomplishes N some sampled data V _{1_w2} And V _{2_w2} After sampling, the SRAM stored N point sampling data V _{1_w2} And V _{2_w2} Fetching into cache inside DSP for data processing, i.e. DSP for V _{1_w2} And V _{2_w2} FFT is respectively carried out to obtain two new N point sequences V _{1w_w2} And V _{2w_w2} . Through V _{1w_w2} And V _{2w_w2} Determining the frequency as w ₂ Vector ratio of test signals of

Wherein

V _{1w_w2} (k) Is a V _{1w_w2} Kth in sequenceElement of V _{2w_w2} (k) Is a V _{2w_w2} The kth element in the sequence.

Step 537: CPU controlled relay switch K ₈ 、K ₉ Closing, discharging the circuit, and after the discharging is finished, controlling a relay switch K by the CPU ₈ 、K ₉ And (5) disconnecting.

Step 538: CPU controlled relay switch K ₁ 、K ₂ Open, and relay switch K ₃ 、K ₆ 、 K ₇ Closing and controlling AD sampling relay switch K ₄ Contact point a, K ₅ And contacting the point a.

Step 539: CPU sends test command to DSP, DSP receives the test command and informs logic unit to send test signal and sampling basic data, and logic unit controls SG sending frequency to be w ₂ The logic unit sends sampling basic data to the AD, and the basic data can be sampling frequency w _s And the number of sampling points is N. After the state is stable, starting AD for sampling to obtain N-point sampling data V _{a_w2} And V _{2_w2} And the AD sends the sampled data to the SRAM for storage.

Step 540: DSP detects AD and accomplishes N some sampled data V _{a_w2} And V _{2_w2} After sampling, the SRAM stored N point sampling data V _{a_w2} And V _2w2 Fetching into cache inside DSP for data processing, i.e. DSP for V _{a_w2} And V _{2_w2} FFT is respectively carried out to obtain two new N point sequences V _{aw_w2} And V _{2w_w2} . Through V _{aw_w2} And V _{2w_w2} Determining the frequency as w ₂ Vector ratio of test signals

Wherein

V _{aw_w2} (k) Is a V _{aw_w2} The kth element in the sequence, V _{2w_w2} (k) Is a V _{2w_w2} The kth element in the sequence.

Step 541: the DSP obtains V according to step 503 _{a1_cor_w1} Step (ii) of523 acquired V _{a1_w1} ， Obtaining w ₁ Lower Z ₁₁ Parameters, i.e.V obtained according to step 506 _{21_cor_w1} V obtained in step 526 _{21_w1} Obtaining w ₁ Lower Z ₂₁ Parameters, i.e.

V obtained according to step 510 _{a2_cor_w1} V obtained in step 530 _{a2_w1} Obtaining w ₁ Lower Z ₂₂ Parameters, i.e.

According to V obtained in step 513 _{a1_cor_22} V obtained in step 533 _{a1_w2} Obtaining w ₂ Lower Z ₁₁ ' parameters, i.e.

V obtained according to step 516 _{21_cor_w2} V obtained in step 536 _{21_w2} Obtaining w ₂ Lower Z ₂₁ ' parameters, i.e.

V obtained according to step 520 _{a2_cor_w2} V obtained in step 540 _{a2_w2} Obtaining w ₂ Lower Z ₂₂ ' parameters, i.e.

The steps 501 to 520 described above are calibration stages for disconnecting the tested line, and the steps 521 to 540 are test stages for accessing the tested line, and the ratio of the vector ratio obtained in the test stage to the vector ratio in the calibration stage is used to obtain w ₁ Or w ₂ The following Z parameter is to eliminate the difference between the two AD channels to eliminate the error to the maximum.

Step 542: acquiring a basic parameter R of the measured line according to the Z parameter acquired in the step 541 ₁ 、 R ₂ 、C ₁ 、C ₂ 、G ₁ 、G ₂ And Z, the specific process is as follows:

substituting Eq1-3 in the aforementioned system of equations into Eq1-1 and Eq1-2 yields:

(G ₁ +jw ₁ C ₁ )Z ₁₁ ＝R ₁ (G ₁ +jw ₁ C ₁ )+1-(G ₂ +jw ₁ C ₂ )Z ₂₁ …………Eq1-7

(G ₂ +jw ₁ C ₂ )Z ₂₂ ＝R ₂ (G ₂ +jw ₁ C ₂ )+1-(G ₁ +jw ₁ C ₁ )Z ₂₁ ………Eq1-8

substituting Eq1-6 in the aforementioned system of equations into Eq1-4 and Eq1-5 yields:

(G ₁ +jw ₂ C ₁ )Z ₁₁ ′＝R ₁ (G ₁ +jw ₂ C ₁ )+1-(G ₂ +jw ₂ C ₂ )Z ₂₁ ′…………Eq1-9

(G ₂ +jw ₂ C ₂ )Z ₂₂ ′＝R ₂ (G ₂ +jw ₂ C ₂ )+1-(G ₁ +jw ₂ C ₁ )Z ₂₁ ′………Eq1-10

each Z parameter is represented in real and imaginary form, respectively: z ₁₁ ＝Z ₁₁ +jZ _11i 、 Z ₂₂ ＝Z _22r +jZ _22i 、Z ₂₁ ＝Z _21r +jZ _21i 、Z ₁₁ ′＝Z _11r ′+jZ _11i ′、Z ₂₂ ′＝Z _22r ′+jZ _22i ' and Z ₂₁ ′＝Z _21r ′+jZ _21i ' then, respectively substituting each Z parameter represented by the imaginary part and the real part into equations Eq1-7 to Eq1-10, and separating the real part from the imaginary part to obtain a new equation set as follows:

as can be seen from the above equation set, the eight equations include R ₁ 、R ₂ 、C ₁ 、C ₂ 、G ₁ And G ₂ These six variables, according to the structural symmetry of the above eight equations, can be easily seen as linear equations only if the following conditions are satisfied: the number of the equations selected from Eq1-11 to Eq1-14 and Eq1-15 to Eq1-18 must be equal, namely three equations are selected from the four equations Eq1-11, eq1-12, eq1-13 and Eq1-14, and three equations are selected from the four equations Eq1-15, eq1-16, eq1-17 and Eq 1-18; the equations selected from Eq1-11, eq1-12, eq1-13, eq1-14 and Eq1-15, eq1-16, eq1-17, eq1-18 must satisfy structural symmetry, so that there are only four cases of selection to satisfy these two requirements, respectively the following selection modes:

1、Eq1-11、Eq1-12、Eq1-13、Eq1-15、Eq1-16、Eq1-17

2、Eq1-11、Eq1-12、Eq1-14、Eq1-15、Eq1-16、Eq1-18

3、Eq1-11、Eq1-13、Eq1-14、Eq1-15、Eq1-17、Eq1-18

4、Eq1-12、Eq1-13、Eq1-14、Eq1-16、Eq1-17、Eq1-18

according to the characteristics of the line under test, of which the capacitance C is ₁ And C ₂ The impedance value of each element of the Z matrix is a main component which does not change along with the frequency and is a main component of the impedance value of each element of the Z matrix in low frequency, and the influence of the known quantity and the variable precision is small; and the resistance R ₁ And R ₂ At low frequencies, it is a very small component of the line impedance, greatly influenced by the known quantity and variable precision, so that stable C can be obtained first ₁ And C ₂ Then, an equation set which is relatively less influenced by the known quantity and the variable precision is searched to obtain R ₁ And R ₂ . To simplify the subsequent description of the equations, definitions are providedThe following constants: m is ₁ ＝Z _11r -Z _11r ′、m ₂ ＝Z _12r -Z _12r ′、m ₃ ＝Z _22r -Z _22r ′、n ₁ ＝w ₁ Z _11i -w ₂ Z _11i ′、 n ₂ ＝w ₂ Z _11i -w ₁ Z _11i ′、n ₃ ＝w ₁ Z _12i -w ₂ Z _12i ′、n ₄ ＝w ₂ Z _12i -w ₁ Z _12i ′、n ₅ ＝w ₁ Z _22i -w ₂ Z _22i ' and n ₆ ＝w ₂ Z _22i -w ₁ Z _22i ′。

To simplify to obtain a linear equation according to (Eq 1-11) - (Eq 1-15), w ₂ ×(Eq1-12)-w ₁ ×(Eq1-16)、w ₂ ×(Eq1-14)-w ₁ X (Eq 1-18) and simplified to obtain: m is ₂ G ₂ -n ₁ C ₁ -n ₃ C ₂ ＝-m ₁ G ₁ 、n ₆ G ₂ +m ₂ w ₁ w ₂ C ₁ +m ₃ w ₁ w ₂ C ₂ ＝-n ₄ G ₁ And n ₄ G ₂ +m ₁ w ₁ w ₂ C ₁ +m ₂ w ₁ w ₂ C ₂ ＝-n ₂ G ₁ . Note that matrices MAR1, MR1G2, MR1C1, and MR1C2 are:

recording the determinant of each matrix as follows: the ratio relationship among MAR1, MR1G2, MR1C1 and MR1C2 is

And

this gives: g ₂ ＝p ₂ G ₁ 、C ₁ ＝p ₁ G ₁ And C ₂ ＝p ₃ G ₁ R can be obtained by substituting the above equality relationship into the equation Eq1-12 or Eq1-16 ₁ To substitute the equation Eq1-12 is an example:

accordingly according to w ₂ ×(Eq1-12)-w ₁ ×(Eq1-16)、(Eq1-13)-(Eq1-17)、 w ₂ ×(Eq1-14)-w ₁ X (Eq 1-18) and simplified to obtain: n is ₄ G ₂ +m ₁ w ₁ w ₂ C ₁ +m ₂ w ₁ w ₂ C ₂ ＝-n ₂ G ₁ 、 n ₆ G ₂ +m ₂ w ₁ w ₂ C ₁ +m ₃ w ₁ w ₂ C ₂ ＝-n ₄ G ₁ And m ₃ G ₂ -n ₃ C ₁ -n ₅ C ₂ ＝-m ₂ G ₁ . Let matrices MAR2, MR2G2, MR2C1, and MR2C2 be:

recording the determinant of each matrix as follows: the ratio relationship between MAR2, MR1G2, MR2C1 and MR2C2 is

And

this makes it possible to obtain: g ₂ ＝q ₂ G ₁ 、C ₁ ＝q ₁ G ₁ And C ₂ ＝q ₃ G ₁ R can be obtained by substituting the above equation into Eq1-12 or Eq1-16 ₁ Take the substitution equation Eq1-12 as an example:

the obtained R _1temp And R _2temp Substituting the equations Eq1-11, eq1-12, eq1-13, eq1-14 or Eq1-15, eq1-16, eq1-17, eq1-18 into the equation so as to obtain the equation containing four variables C ₁ 、C ₂ 、G ₁ And G ₂ To obtain C from the four linear equations ₁ 、C ₂ 、G ₁ And G ₂ The specific value of (a). Take the first four equations as an example:

the following equation set C ₁ 、C ₂ 、G ₁ And G ₂ And (6) solving.

Note that matrices M, MC, MC2, MG1 and MG2 are:

and

the determinant of each matrix is respectively recorded as: i M, MG1, MG2, MC1 and MC2, such that C ₁ 、C ₂ 、G ₁ And G ₂ Can be respectively expressed as:

in the above equation set, the equations Eq1-23 and Eq1-2 are based on4 is stable and not affected by the known quantity and the variable precision. As mentioned before, due to R ₁ And R ₂ At low frequencies, it is a very small component of the Z parameter impedance and is therefore greatly affected by the known quantity and variable accuracy, the C which will now be stable ₁ And C ₂ As a known quantity, into equations Eq1-11 to Eq1-18, so that there are four variables in the eight equations, for a total of

And (4) combining the solutions. After extensive simulation and calculation, e.g. based on the obtained line fundamental parameter R ₁ 、R ₂ 、C ₁ 、C ₂ 、G ₁ And G ₂ Calculating each Z parameter, and then calculating R according to the obtained Z parameters ₁ 、R ₂ 、C ₁ 、C ₂ 、G ₁ And G ₂ Finally, it is found that only one combination can obtain stable and accurate R ₁ And R ₂ The combination is: eq1-12, eq1-14, eq1-16, eq1-18. Thus, will be known as C ₁ And C ₂ Substituting into four parties Eq1-12, eq1-14, eq1-16 and Eq1-18In the process:

the notation matrices MP, MR1 and MR2 are respectively:

and

the determinant of each matrix is respectively recorded as: i MP, MR1 and MR2, such that R ₁ And R ₂ Can be expressed as:

in summary, R ₁ 、R ₂ 、C ₁ 、C ₂ 、G ₁ And G ₂ Eight line basic parameters are represented by six equations Eq1-23 to Eq1-28, respectively, and R to be obtained ₁ 、R ₂ 、C ₁ 、C ₂ 、G ₁ And G ₂ Substituting into the equation, the remaining variable Z can be represented as:

step 543: r and L are corrected.

The above steps obtain the basic parameters of the line model, and usually, because the line is long, the circuit model of the line cannot reflect the real situation of signal transmission when the ADSL high-frequency band transmits signals, so the basic parameters obtained in the above steps need to be mapped to the transmission line model of the line through correction, as shown in fig. 6.

According to the transmission line equation, there are:

U _(x) ＝A ₁ e ^-γx +A ₂ e ^γx

the relationship between each parameter and the basic line parameter is as follows:

since G is very small, it can be ignored. From this, the frequency response of the line attenuation can be determined as:

|S ₂₁ |＝e ^-αf

wherein

Wherein the relation between R and C and the obtained R1, R2, C1 and C2 is as follows:

r and C are only resistance and capacitance values under low frequency, because the line attenuation is a function of frequency, the line attenuation corresponding to different frequencies is different, and in order to obtain the line attenuation under other frequencies, according to the above formula, the invention needs to obtain the resistance R under other frequencies first _(f) Capacitor C _(f) And an inductance L _(f) 。

For the line of the twisted pair, the capacitance does not change with the frequency, but the resistance and the inductance change with the frequency, so the capacitance under other frequencies does not need to be calculated, namely the capacitance under all the frequencies is the same, and the capacitance can be replaced by the obtained low-frequency capacitance C; i.e. C _(f) ＝C

The invention only needs to calculate the resistance R under other frequencies _(f) And an inductance L _(f) 。

Calculation of the resistance at other frequencies f:

where R is the resistance at low frequencies and α is a certain constant. It can be seen that the resistance at different frequencies is different; with this formula, the resistances at other frequencies are all calculated.

Calculation of the inductances at other frequencies f:

wherein L is _a ，L _a ，f _p And b is a determined value: la: inductance per kilometer line in direct current; lo: the inductance limit value of each kilometer of the line when the frequency is infinite; fp: a critical frequency; b: and the inductance is a characteristic quantity of the frequency variation trend. It can be seen that the inductance at different frequencies is different; by means of this formula it is possible to,the inductances at other frequencies are all calculated.

And step 544, acquiring the frequency response of the line transmission attenuation.

Obtain the resistance R under different frequencies _(f) Capacitor C _(f) And an inductance L _(f) Then, substituting into the formula for calculating attenuation derived, the attenuation at other frequencies can be calculated:

|S ₂₁ |＝e ^-αf

wherein

When the line attenuation is obtained, the line attenuation is compared with a known standard, and a fault such as the aging condition of the line can be judged.

The system and the device provided by the invention can be accurate and stable without being influenced by the line length when the line parameters are obtained, and solve the defects that the TDR method adopted by the prior art is inaccurate in attenuation test of a long line and in attenuation test when a terminal is matched.

In short, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A method for obtaining basic parameters of a line, the method comprising:

2. The method of claim 1, further comprising:

3. The method of claim 1 or 2, wherein the ratio of vectors obtained by the DSP is obtained by a fast fourier transform, FFT, algorithm calculation.

4. The method according to claim 1 or 2, wherein the basic parameters of the acquired line are: the inductance of the line, the resistance of the line and the capacitance of the line.

5. A method according to claim 1 or 2, characterized in that the method further comprises:

6. The method of claim 3, further comprising: and comparing the acquired frequency response of the line with a frequency response standard to obtain the aging condition of the line.

7. A device for obtaining the basic parameters of line is characterized by that it includes CPU, DSP, logic unit, signal generator SG and sampling unit, in which the CPU is connected with DSP, the DSP is connected with logic unit, the signal generator is connected with logic unit, the sampling unit is respectively connected with logic unit, signal emitter and DSP,

the CPU is used for informing the DSP to carry out line test;

the sampling unit is used for receiving the test signal from the SG, sampling according to the control of the logic unit, and then providing the sampled data for the DSP.

8. The apparatus of claim 7, wherein the DSP is further configured to obtain a frequency response of the line under test based on the obtained basic parameters of the line under test.

9. The apparatus of claim 7, further comprising an output display unit coupled to the CPU, the CPU being configured to receive data provided by the DSP and to provide the data to the output display unit; the output display unit is used for displaying data from the CPU.

10. The apparatus of claim 7, wherein the sampling unit includes a linear filter LF, an analog/digital converter AD, a random access memory RAM, a relay, a sampling relay switch, a current sampling resistor, and a ground resistor,

11. The apparatus of claim 10, wherein the RAM is a Static Random Access Memory (SRAM).