CN101114259A - Program code memory bank in processor piece based on FLASH structure and method for realizing execution in code piece - Google Patents
Program code memory bank in processor piece based on FLASH structure and method for realizing execution in code piece Download PDFInfo
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Abstract
A processor on-chip program code memory that is based on a FLASH framework and a method that realizes the execution of the on-chip code belongs to the chip technical field, which is characterized in that the FLASH is in the form of NAND, and the memory comprises an address mapping unit which is logically arranged between the CPU and the NAND FLASH for the conversion between an indexed address of the NAND FLASH and a linear address. The invention leads the program code to be stored in the NAND FLASH to realize the on-chip execution (XIP) by the address mapping unit, and solves the disadvantages of the prior NOR FLASH such as high cost, large area and small capacity. By taking the NAND FLASH as the memory of the processor, the invention breaks the limitations for capacity, and the small volume is convenient for the packaging and integration with a high speed of erasure and more erasing times.
Description
Technical field
The invention belongs to System on Chip/SoC (SOC) technical field, be specifically related to the method for carrying out based in the processor piece internal program code storage body of FLASH framework and the code sheet.
Background technology
Flash memory (Flash Memory) abbreviates FLASH as, is a class nonvolatile memory NVM (Non-Volatile Memory), and its feature is still can the retention tab internal information after power supply is closed.According to the difference of Technical Architecture, flash memory mainly is divided into two kinds of NOR framework (Nor Flash) and NAND frameworks (Nand Flash) in the world at present.
The maximum characteristics of Nor Flash are to have independently data bus and address bus, can read at random fast, the permission system directly reads the code execution from Flash be to carry out (XIP in the chip, eXecuteIn Place), application program can directly be moved in the flash flash memory like this, needn't read code among the RAM of system again.With Nor FLASH difference, its data message of Nand Flash, same bus of address information time-sharing multiplex, so its speed that reads byte at random is slower than Nor Flash.Because NorFlash has independently data bus and address bus, be convenient to direct data and address bus interface with processor, the program/data back of all processor inside all adopts NorFlash in the world at present.
Along with the development in technology and market, the memory bank of processor inside also there has been higher requirement.On the one hand, because the raising of system complexity, program code amount and required data quantity stored are increasing, and this just requires bigger FLASH space to deposit code and data; On the other hand, because cost and integrated level aspect require the size of memory bank more and more littler.So Nor Flash is obvious day by day as the weak point of code storage body:
(1) Nor Flash memory capacity is little, Nor Flash adopts is independently address bus and data bus framework, the characteristics of this linear address mode are, must increase the width of address bus when increasing memory capacity, yet the highway width of CPU and the requirement of cost do not allow Nor type FLASH unrestrictedly to increase the width of its address bus, and the Nor Flash of memory capacity maximum only is 16MB at present.
(2) Nor Flash unit size is big, the cost height of unit capacity.Because framework and technical matters, the cost of same size Nor flash almost is the twice of Nand Flash device.
(3) wipe and write slow, and durability is poor, and NOR is that the piece with 64～128KB carries out, and carrying out the time that a write/erase operates is 5s, and compares Nand Flash, is 1 to 10 piece erase cycle inferior position.
Summary of the invention
In order to address the above problem, the present invention's purpose is NAND FLASH is integrated into the internal storage of processor inside as processor, shortcoming such as solved existing scheme NOR FLASH cost height, area is big, capacity is little, a kind of processor piece internal program code storage body based on the FLASH framework is provided, and makes the program code that is stored in NAND FLASH realize carrying out in the sheet method of (XIP).
The present invention realizes that above-mentioned purpose adopts following scheme:
A kind of processor piece internal program code storage body based on the FLASH framework, it is characterized in that described FLASH is the NAND type, described memory bank comprises an address mapping unit, it gets conversion between the linear address that refers to the unit in order to the index type address of NAND FLASH and processor in logic between CPU and NAND FLASH.
Described address mapping unit comprises:
The control signal unit is in order to the generation required control signal of NAND FLASH with to transmission NAND FLASH control signal;
The data parsing unit in order in the WRITE cycle and the READ cycle of processor, is split as various bit wide data 8 bit data or 8 bit data is combined as various bit wide data, and be transferred to NAND FLASH or processor under the indication of control signal;
Address resolution unit resolves to the required index address that comprises page address and page or leaf bias internal address of NAND FLASH in order to the linear address that processor is transmitted, and respectively page address and page or leaf bias internal address are delivered to NAND FLASH under the control signal indication.
The control signal unit, connect NAND FLASH by control bus, the data parsing unit is connected NAND FLASH with address resolution unit by the address date multiplex bus, and data parsing unit and address resolution unit be articulating by data bus and address bus and processor respectively.
Control signal of the present invention unit is made up of logical circuit of clock and sequential logical circuit, and logical circuit of clock is in order to produce the clock reference ModulClk of address mapping unit under the control of total line traffic control write signal WE, read signal RE; Sequential logical circuit is in order to produce control signal.
Data parsing of the present invention unit comprises by data shift latching logic circuit and bus driving circuits to be formed, data shift latching logic circuit is in order to latch the data on the data bus, be shifted, divide into groups, and under the cooperation of bus driving circuits, deliver to NAND FLASH; Bus driving circuits is connected with data shift latching logic circuit by driving interface, and data shift latching logic circuit latched data is delivered to external bus.Data shift latching logic circuit is responsible for the data on the data bus are latched, are shifted, divide into groups, and delivers to NAND FLASH under the cooperation of bus driving circuits.The data of for example sending here on the bus 0 * 1234, at first being shifted the latching logic circuit latchs, the latching logic that is shifted then circuit is delivered to upper byte 0 * 12 driving interface and by bus driving circuits data 0 * 12 is delivered to external bus, the latching logic that then is shifted circuit is delivered to driving interface with the low byte 0 * 34 of latched data 0 * 1234 and is sent by bus driving circuits, and so far a data transfer procedure just is through with.Certainly, finishing of above-mentioned action all is to finish under the control timing that sequential logical circuit produces.
Address resolution unit of the present invention comprises address displacement latching logic circuit, page address buffer memory, offset address buffer memory and the bus driving circuits separately of double width;
Address displacement latching logic circuit is 32 an address latch logic with shift circuit, in order to the data of latch address bus, and is page address and offset address with data parsing;
Page address and offset address that page address buffer memory and offset address buffer memory are parsed by address latch logic with shift circuit in order to storage;
Bus driving circuits is connected with the offset address buffer memory with the page address buffer memory by driving interface, in order to address page address and offset address are outputed to external bus.
The address of double width displacement latching logic circuit is one 32 an address latch logic with shift circuit, and its effect is the data of latch address bus, and is data parsing page address and offset address.The page address width is 21 to the maximum, can addressing 2048K page or leaf.The offset address width is 11, is used for carrying out addressing in the page or leaf.The page address and the offset address that are parsed by address latch logic with shift circuit are respectively stored in page address buffer memory and the offset address buffer memory.Address mapping unit is according to the access to content NANDFLASH of page address buffer memory.The effect of bus driving circuits is identical with the effect of the bus driving circuits of data analysis unit.
For improving the efficient carried out in the program code sheet and the efficient of reading of data, all right link order high-speed cache ICACHE of address mapping unit of the present invention and data cache DCACHE, address resolution unit comprises the Cache control logic circuit, the Cache control logic circuit connects page address buffer memory and offset address buffer memory, in order to judge according to the content of page address buffer memory whether the Cache page or leaf hits; If hit, address mapping unit is directly according to the address information that is stored in offset address buffer memory addressing from Cache; Otherwise according to the access to content NAND FLASH of page address buffer memory and upgrade the Cache page or leaf.
Because in the time of NAND FLASH reading of data, address information and data message all transmit by same 8 buses of time-sharing multiplex, so the speed of reading of data is slower than traditional NORFLASH, ICACHE and DCACHE have been increased in order to address this problem the present invention.The size of ICACHE and DCACHE is identical with NAND FLASH page or leaf size, and content that can disposable storage one page is if instruction of reading or data in CACHE, are then directly fetched data from CACHE, otherwise the target data page or leaf is read in corresponding CACHE.
NAND FLASH with 2K bytes data page is an example,
If do not adopt the CACHE framework, be: time overhead=(order and address Time Created+CPU time for reading) * byte number according to formula.Herein, " order and address Time Created " is according to 7 cycle meters of common configuration." CPU time for reading " is according to 1 cycle meter of common configuration.
Do not adopt the CACHE framework, the expense that CPU reads one page is 16384 cycle for (7+1) * 2048
And adopt the CACHE framework, calculate according to formula: time overhead=CACHE surge time+CPU time for reading=order and address the Time Created+burst byte time for reading * byte number+CPU time for reading * byte number.Herein, " order and address Time Created " is according to 7 cycle meters of common configuration." burst byte time for reading " according to 1 cycle meter of common configuration, " CPU time for reading " is according to 1 cycle meter of common configuration.
Expense when adopting the CACHE framework is: 7+2048 * 1+2048 * 1 4103 cycle.Efficient improves nearly four times.This index has been that 4096 cycle (calculate according to formula: CPU time for reading * byte number of time overhead=NOR FLASH by the CPU access speed of NOR FLASH near the CPU access speed 2 * 2048 of NOR FLASH; " the CPU time for reading of NOR FLASH " is according to 2 cycle meters of common configuration.)。This shows that the introducing of ICACHE and DCACHE has greatly improved the access speed of NAND FLASH, has overcome the slow shortcoming of NAND FLASH access speed.
Another purpose of the present invention is to provide with NAND FLASH as the method for carrying out in the processor piece stored body code sheet, it is characterized in that comprising step:
With program code storage in NAND FLASH flash memory;
Described memory bank articulates by address mapping unit and described processor;
The processor system processor sends linear address;
Address mapping unit produces the required control signal of NAND FLASH, and to transmission NANDFLASH control signal;
Address mapping unit resolves to the required index address that comprises page address and page or leaf bias internal address of NAND FLASH at the linear address that processor is transmitted, and respectively page address and page or leaf bias internal address is delivered to NAND FLASH under the control signal indication.
Address mapping unit was split as various bit wide data a plurality of 8 data and is transferred to NAND FLASH under the indication of control signal in the WRITE cycle of processor; In the READ cycle of processor, a plurality of 8 bit data are combined as various bit wide data, and under the indication of control signal, are transferred to processor;
If address mapping unit is connected with instruction cache ICACHE and data cache DCACHE also comprises step:
Calculate " page address " and " page or leaf bias internal amount " and be stored in page address buffer memory and offset address buffer memory.
Judge whether the Cache page or leaf hits;
If hit, address mapping unit is directly according to the information addressing from Cache that is stored in the offset address buffer memory;
If miss, the information in the page address buffer memory of being stored in is according to visit NANDFLASH and upgrade the Cache page or leaf, then according to the information addressing from the Cache that has upgraded that is stored in the offset address buffer memory.
The present invention has following beneficial effect with NOR FLASH as the processor memory bank with respect to existing:
(1) NAND FLASH has broken through the restriction of capacity as the memory bank of processor, and the capacity of NAND FLASH has reached 2GB at present.
(2) volume is little, is convenient to encapsulation and integrated.
(3) erasing speed is fast, and the erasing speed of NAND FLASH is at Millisecond, and NORFLASH then needs a few tens of milliseconds.
(4) often erasable, the erasable number of times of NAND FLASH reaches 1,000,000 times, and the erasable number of times of NORFLASH only tens0000 times.
(5) the present invention has greatly improved the reading speed of code and data by increasing ICACHE and DCACHE.
Description of drawings
Fig. 1 is prior art CPU and NOR FLASH connection diagram;
Fig. 2 is an address mapping unit logic diagram of the present invention;
Fig. 3 is an address mapping unit configuration diagram of the present invention;
Fig. 4 is the logic timing figure of address mapping unit coherent signal of the present invention;
Fig. 5 is for using the application examples configuration diagram of the inventive method;
Fig. 6 is an instruction fetch process flow diagram embodiment illustrated in fig. 5.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
See the cabling that is connected that Figure 1 shows that CPU and NOR FLASH, processor internal processes/data all are stored in NOR FLASH in the prior art, and Nor Flash has independently data bus and address bus, directly links to each other with the data and address bus interface of processor.
For realizing NAND FLASH as carrying out in processor piece stored body and the code sheet, the present invention is by address mapping unit, with the conversion of linear address and NAND FLASH index type address.Utilize address mapping unit, the program code that is stored in NAND FLASH can realize carrying out in the sheet (XIP).What NAND FLASH adopted is the index type address of the page number+page or leaf bias internal amount.This address structure is got the linear address difference that adopts when referring to CPU, if do not change, refers to and execution command just CPU can not get from NAND FLASH.Address mapping unit of the present invention between CPU and NAND FLASH, is got the linear address that refers to the unit to the index type address of NAND FLASH with CPU and is done with conversion in logic.
Address mapping unit of the present invention comprises that address mapping unit 1 comprises: control signal unit 11, data parsing unit 12 and address resolution unit 13.
Principle of work to various piece is illustrated below.
(1) control information unit
The effect of control information unit 11 is to produce the needed various control signals of Nand Flash, as signals such as CLE, ALE, RB, and is transferred to Nand Flash in due course.
(2) data analysis unit
In the WRITE cycle of CPU, data analysis unit 12 is split as a plurality of 8 data with the data of various bit wides, and is transferred to Nand Flash under the indication of control signal; In the READ cycle of CPU, data analysis unit 12 receives a plurality of 8 data from Nand Flash, and the requirement according to cpu instruction is combined as the data of various bit wides and sends CPU to then.
The data of for example sending here on the bus 0 * 1234, at first being shifted latching logic circuit 121 latchs, the latching logic that is shifted then circuit 121 is delivered to upper byte 0 * 12 driving interface and by bus driving circuits 122 data 0 * 12 is delivered to external bus, the latching logic that then is shifted circuit 121 is delivered to driving interface with the low byte 0 * 34 of latched data 0 * 1234 and is sent by bus driving circuits, and so far a data transfer procedure just is through with.Certainly finishing of all these actions all is to finish under the control timing that sequential logical circuit produces, and sees Fig. 3 for details.
(3) adress analysis unit
The linear address that address resolution unit 13 transmits CPU resolves to the needed index address of Nand Flash (page address and page or leaf bias internal address), respectively page address and page or leaf bias internal address is delivered to Nand Flash then under the indication of control signal.
Below be example with the ZSP400 kernel, the embodiment that CPU articulates with NAND FLASH is described.Its functional block diagram such as Fig. 5 show.Instruction cache ICACHE and data cache DCACHE have been increased between address mapping unit and the ZSP400 CPU.
It is that the program's memory space of 0 * 85ac is an example that present embodiment obtains the address with CPU (ZSP400), in order to the get finger process of explanation CPU to NAND FLASH.Wherein " address mapping unit " sees before and states content, and the instruction fetch process flow diagram is seen shown in Figure 6, the step of passing through as follows:
(1), CPU sends and gets instruction, and address 0 * 85ac is delivered to address bus.
(2), address mapping unit obtains the address information (0 * 85ac) on the bus.
(3), (0 * 85ac) calculates " page address PageN " and " page or leaf bias internal amount DstN " and is stored in page address buffer memory and offset address buffer memory address resolution unit parse addresses information.
(4), the CACHE steering logic resolves page address PageN, judges whether to hit ICACHE.If hit buffer memory then directly carry out the 6th step, otherwise carry out the 5th step.
(5), refresh ICACHE according to PageN.
(6), according to the page or leaf bias internal amount DstN code that from ICACHE, gets instruction.
Claims (8)
1. processor piece internal program code storage body based on the FLASH framework, it is characterized in that described FLASH is the NAND type, described memory bank comprises an address mapping unit, it gets conversion between the linear address that refers to the unit in order to the index type address of NAND FLASH and processor in logic between CPU and NAND FLASH.
2. according to claim 1 based on the processor piece internal program code storage body of FLASH framework, it is characterized in that address mapping unit comprises:
The control signal unit is in order to the generation required control signal of NAND FLASH with to transmission NANDFLASH control signal;
The data parsing unit in order in the WRITE cycle and the READ cycle of processor, is split as various bit wide data 8 bit data or 8 bit data is combined as various bit wide data, and be transferred to NAND FLASH or processor under the indication of control signal;
Address resolution unit resolves to the required index address that comprises page address and page or leaf bias internal address of NAND FLASH in order to the linear address that processor is transmitted, and respectively page address and page or leaf bias internal address are delivered to NAND FLASH under the control signal indication.
The control signal unit, connect NAND FLASH by control bus, the data parsing unit is connected NAND FLASH with address resolution unit by the address date multiplex bus, and data parsing unit and address resolution unit be articulating by data bus and address bus and processor respectively.
As described in the claim 2 based on the processor piece internal program code storage body of FLASH framework, it is characterized in that described control signal unit is made up of logical circuit of clock and sequential logical circuit, logical circuit of clock is in order to produce the clock reference ModulClk of address mapping unit under the control of total line traffic control write signal WE, read signal RE; Sequential logical circuit is in order to produce control signal.
As described in the claim 2 based on the processor piece internal program code storage body of FLASH framework, it is characterized in that described data parsing unit comprises by data shift latching logic circuit and bus driving circuits forms, data shift latching logic circuit is in order to latch the data on the data bus, be shifted, divide into groups, and under the cooperation of bus driving circuits, deliver to NAND FLASH; Bus driving circuits is connected with data shift latching logic circuit by driving interface, and data shift latching logic circuit latched data is delivered to external bus.
As described in the claim 2 based on the processor piece internal program code storage body of FLASH framework, it is characterized in that described address resolution unit comprises address displacement latching logic circuit, page address buffer memory, offset address buffer memory and the bus driving circuits separately of double width;
Address displacement latching logic circuit is 32 an address latch logic with shift circuit, in order to the data of latch address bus, and is page address and offset address with data parsing;
Page address and offset address that page address buffer memory and offset address buffer memory are parsed by address latch logic with shift circuit in order to storage;
Bus driving circuits is connected with the offset address buffer memory with the page address buffer memory by driving interface, in order to address page address and offset address are outputed to external bus.
As described in the claim 5 based on the processor piece internal program code storage body of FLASH framework, it is characterized in that described address mapping unit also link order high-speed cache ICACHE and data cache DCACHE, described address resolution unit comprises the Cache control logic circuit, the Cache control logic circuit connects page address buffer memory and offset address buffer memory, in order to judge according to the content of page address buffer memory whether the Cache page or leaf hits; If hit, address mapping unit is directly according to the address information that is stored in offset address buffer memory addressing from Cache; Otherwise according to the access to content NAND FLASH of page address buffer memory and upgrade the Cache page or leaf.
7. the method as carrying out in the processor piece internal program code storage body code sheet based on the FLASH framework as described in one of claim 1～6 is characterized in that comprising step:
With program code storage in NAND FLASH flash memory;
Described memory bank articulates by address mapping unit and described processor;
The processor system processor sends linear address;
Address mapping unit produces the required control signal of NAND FLASH, and to transmission NAND FLASH control signal;
Address mapping unit resolves to the required index address that comprises page address and page or leaf bias internal address of NAND FLASH at the linear address that processor is transmitted, and respectively page address and page or leaf bias internal address is delivered to NAND FLASH under the control signal indication;
Address mapping unit was split as various bit wide data a plurality of 8 data and is transferred to NAND FLASH under the indication of control signal in the WRITE cycle of processor; In the READ cycle of processor, a plurality of 8 bit data are combined as various bit wide data, and under the indication of control signal, are transferred to processor.
8. the method as carrying out in the processor piece internal program code storage body code sheet based on the FLASH framework as described in the claim 7 is characterized in that also comprising step:
Calculate " page address " and " page or leaf bias internal amount " and be stored in page address buffer memory and offset address buffer memory.
Judge whether the Cache page or leaf hits;
If hit, address mapping unit is directly according to the information addressing from Cache that is stored in the offset address buffer memory;
If miss, the information in the page address buffer memory of being stored in is according to visit NANDFLASH and upgrade the Cache page or leaf, then according to the information addressing from the Cache that has upgraded that is stored in the offset address buffer memory.
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