CN101110260B - Selective precharging circuit for memory device with charging compensating structure - Google Patents
Selective precharging circuit for memory device with charging compensating structure Download PDFInfo
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- CN101110260B CN101110260B CN200710035330A CN200710035330A CN101110260B CN 101110260 B CN101110260 B CN 101110260B CN 200710035330 A CN200710035330 A CN 200710035330A CN 200710035330 A CN200710035330 A CN 200710035330A CN 101110260 B CN101110260 B CN 101110260B
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- charging
- pipe
- bit line
- phase inverter
- tube
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Abstract
The invention discloses a storage device selective pre-charging circuit with a charging compensation structure. The selective pre-charging unit is composed of a pre-charging tube Mp1 and two or more than two bit line selection tube Mpi; the charging compensation unit is composed of a charging compensation tube Mp2 and a second phase inverter inv2; the source end of the pre-charging tube is connected to a power source and its leakage end is connected to an internal circuit; the pre-charging tube Mp1 is controlled by a pre-charging signal Fpre; one end of each bit line selection tube is connected to the bit line in a storage array and its another end is connected to the leakage end of the pre-charging tube Mp1 and the charging compensation tube Mp2, the second phase inverter inv2 of the charging compensation unit as well as the input end of a first phase inverter inv2 in an output drive unit; the source end of the charging compensation tube Mp2 is connected to the power source and its leakage end is connected to the internal circuit; the mp2 tube is controlled by the output end of the second phase inverter inv2; the input end of the second phase inverter inv2 is connected to the leakage end of the pre-charging tube Mp1 and the charging compensation tube Mp2. Therefore, the invention, with simple structure, is able to shorten the time consumed in the bit line charging stage and enhance the reading speed of the storage device.
Description
Technical field
The present invention is mainly concerned with the design field of low power consumption memories, refers in particular to a kind of selective precharging circuit for memory with charging compensating structure.
Background technology
Along with the density of integrated circuit and frequency of operation according to the described such sustainable growth of Moore's Law, the focus that being designed to of low-power dissipation system paid close attention to for devisers.Particularly among the SoC (system integrated chip), because storer has occupied the very most of of chip power-consumption, so the designing technique of low power consumption memories is significant to the integrated circuit development at microprocessor.And, the performance of speed, area and three aspects of power consumption of storer is all had high requirements along with a large amount of uses of in-line memory in the high-performance processor.And because the mutual restriction relation between these three parameters, the storer Low-power Technology tends to cause the expense of speed and area.Therefore, exchange the design difficulty that low power capabilities is the storer Low-power Technology for lower expense.
For memory chip, the source of power consumption can be divided into three aspects: memory cell array, code translator and peripheral circuit.Wherein the power consumption of memory cell array is the main source of power consumption of memory.To the storer of the capable m row of n, its structure as shown in Figure 1, power consumption can be with following formula approximate representation:
P＝V
DDI
DD
＝(mi
act+m(n-1)i
hld)+((n+m)C
DEV
intf)+(C
PTV
intf)
I wherein
ActBe the watt current of equal value of selected unit, it be one read or write operation in flow through the total electrical charge of storage unit and the ratio of read-write cycle, i
H1dBe that the dead zone unit data are kept electric current, V
IntBe internal power source voltage, C
DEBe the output load of equal value of each code translator, C
PTBe the total load of peripheral circuit, f is a frequency of operation.
Chip now is embedded in the formula storer, and in order to realize the purpose of high-speed low-power-consumption, mostly memory cell array is to adopt dynamic precharge structure.Therefore, the power consumption of memory cell array mainly is the power consumption that discharges and recharges to memory cell array neutrality line electric capacity.The estimation equation of its power consumption is as follows;
P
array＝m×i
act×V
DD＝m×C
eff×V
DD 2×f
Wherein, m needs the number of bit that discharged and recharged, C in read operation
EffBe the effective capacitance of equal value of each bit line, V
DD 2Be supply voltage, f is a frequency of operation.By formula as can be seen,, want to reduce the work power consumption of storage array, be merely able to realize by reducing the number of bit m that participates in charge and discharge process for the storer of having determined manufacturing process, capacity and performance requirement.
The selective precharge structure as shown in Figure 2, circuit 10 is memory cell arrays among the figure, circuit 20 is selectivity bit-line pre-charge unit, circuit 30 is output driving circuits.In selectivity bit-line pre-charge unit, PMOS manages M
P1Be traditional preliminary filling fulgurite, M
P1The source end connecting power supply, drain terminal is connecting internal circuit, M
P1Be subjected to precharging signal F
PreF is worked as in control
PrePreliminary filling fulgurite conducting during for low level begins F is worked as in the circuit charging
PreThe preliminary filling fulgurite turn-offs during for high level, cuts off the path from the power supply to the internal circuit.NMOS manages M
N1To M
N16Be that bit line is selected pipe, bit line selects the quantity of pipe to organize the difference of form according to memory array and difference can be two and arrive a plurality of.One end of each bit line selection pipe connects the bit line in the storage array, and the other end connects preliminary filling fulgurite M
P1Drain terminal and the phase inverter input end in the output driving circuit.Bit line is selected the decode results signal s of pipe by column decoder
1To s
16Control.When storer enters pre-charging stage, F
PreBe low level, column decoder carries out work decoding simultaneously, respective signal s after column decoder is finished decoding
1To s
16In a meeting by low transition to high level, this moment, respective bit line selected pipe to be opened bit line that connects and preliminary filling fulgurite M
P1Be communicated with preliminary filling fulgurite M
P1Begin this bit line is charged.When storer is finished the laggard data phase of studying in of pre-charge process, F
PreSaltus step is that high level is with preliminary filling fulgurite M
P1Turn-off, simultaneously, the bit line that is opened in pre-charging stage selects to guarantee and holds conducting state, discharges according to the content pairs of bit line of cell stores in the storage array or discharge operation not.Bit line is a low level if bit line is discharged, so the phase inverter input end in the output driving circuit is low level, thereby at " 1 " signal of output terminal output high level; Remain the high level state of pre-charging stage if bit line does not discharge, so the phase inverter input end in the output driving circuit is high level, thereby at " 0 " of output terminal output low level signal.The work schedule of circuit as shown in Figure 3.
In the circuit structure of Fig. 2, select 1 bit line selected cell the bit line number that participates in discharging and recharging can be reduced to 1/16 of ordinary construction by 16, have only original about 1/16 thereby the work power consumption of memory cell array reduced to.As seen the selective precharge structure has very significantly optimised power consumption effect.But as can be seen, this structure can bring the expense (t that is bordering on a times for the data read time in order to guarantee correctly precharge of bit line from working timing figure
2≈ t
1), this obviously is unacceptable for high-speed memory.
Summary of the invention
The problem to be solved in the present invention just is: at the technical matters of prior art existence, the invention provides a kind of simple in structure, can shorten the time overhead of bit line charging stage greatly, thereby improved the selective precharging circuit for memory of the band charging compensating structure of memory data reading speed.
For solving the problems of the technologies described above, the solution that the present invention proposes is: a kind of selective precharging circuit for memory with charging compensating structure, it is characterized in that: it comprises selective precharge unit, charge compensate unit and output driver element, and described selective precharge unit comprises precharge pipe M
P1Select pipe M with two or more bit lines
Ni, the charge compensate unit comprises charge compensate pipe M
P2With the second phase inverter inv
2, charge compensate pipe M
P1The source end connecting power supply, drain terminal is connecting internal circuit, charge compensate pipe M
P1Be subjected to precharging signal F
PrePipe M is selected in control, each bit line
NiAn end connect bit line in the storage array, the other end is connected in preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal and the second phase inverter inv of charge compensate unit
2, output driver element the first phase inverter inv
1Input end, charge compensate pipe M
P2The source end connecting power supply, drain terminal is connecting internal circuit, M
P2Pipe is subjected to the second phase inverter inv
2Output terminal control, the second phase inverter inv
2Input end and preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal connect.
A described charge compensate unit and an equivalent capacitor C
dLink to each other.
Compared with prior art, advantage of the present invention just is:
1, because the present invention has adopted the charging compensating structure circuit, compares, can shorten the time overhead t of bit line charging stage greatly with common selective precharge structure
2Thereby, improved the data reading speed of storer.
2, select the charging process of management and control system bit line by bit line, the bit line capacitance that does not participate in data read does not does not discharge and recharge operation, thus the power wastage when having avoided reading of data.
3, introduce the charge compensate circuit, not only guaranteed precharge correctness but also shortened the time overhead of charging stage.
Description of drawings
Fig. 1 is memory construction block diagram and power consumption source synoptic diagram;
Fig. 2 is existing selective precharge structural circuit synoptic diagram;
Fig. 3 is the work schedule synoptic diagram of existing selective precharge circuit;
Fig. 4 is a structural framing synoptic diagram of the present invention;
Fig. 5 is a physical circuit synoptic diagram of the present invention;
Fig. 6 is a workflow synoptic diagram of the present invention
Fig. 7 is the work schedule synoptic diagram of circuit of the present invention.
Embodiment
Below with reference to the drawings and specific embodiments the present invention is described in further details.
As shown in Figure 4 and Figure 5, the selective precharging circuit for memory of band charging compensating structure of the present invention is to have set up a charge compensate unit on traditional selective precharge architecture basics in addition, it comprises selective precharge unit, charge compensate unit and output driver element, and described selective precharge unit comprises precharge pipe M
P1Select pipe M with two or more bit lines
Ni, the charge compensate unit comprises charge compensate pipe M
P2With the second phase inverter inv
2, preliminary filling fulgurite M
P1The source end connecting power supply, drain terminal is connecting internal circuit, preliminary filling fulgurite M
P1Be subjected to precharging signal F
PrePipe M is selected in control, each bit line
NiAn end connect bit line in the storage array, the other end is connected in preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal and the second phase inverter inv of charge compensate unit
2, output driver element the first phase inverter inv
1Input end, charge compensate pipe M
P2The source end connecting power supply, drain terminal is connecting internal circuit, M
P2Pipe is subjected to the second phase inverter inv
2Output terminal control, the second phase inverter inv
2Input end and preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal connect.
As shown in Figure 5, be the present invention at one 16 application example that selects in 1 the bit line choice structure, wherein circuit 10 is memory cell arrays, w
1To w
64Be the storage array word line, capacitor C
BL1To C
BL16The equivalent capacity of representing every storage array bit line.Circuit 20 is selective precharge circuits of the band charging compensating structure that proposes of the present invention.Wherein NMOS manages M
N1To M
N16Adopt traditional bit line to select pipe, according to the respective bit line of gating as a result of column decoder, capacitor C
dBe the circuit equivalent electric capacity of this structure.Circuit 30 is circuit of output driver element.
In circuit, PMOS manages M
P1Be traditional preliminary filling fulgurite, M
P1The source end connecting power supply, drain terminal is connecting internal circuit, M
P1Be subjected to precharging signal F
PreControl is when being F
PrePreliminary filling fulgurite conducting during for low level begins to the circuit charging, when being F
PreThe preliminary filling fulgurite turn-offs during for high level, cuts off the path from the power supply to the internal circuit.NMOS manages M
N1To M
N16Be that bit line is selected pipe, bit line selects the quantity of pipe to organize the difference of form according to memory array and difference can be two and arrive a plurality of.One end of each bit line selection pipe connects the bit line in the storage array, and the other end connects preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal and the phase inverter inv of charge compensate circuit
2With the phase inverter inv in the output driving circuit
1Input end.Bit line is selected the decode results signal s of pipe by column decoder
1To s
16Control.Charge compensate pipe M
P2And driving phase inverter inv
2Be the innovative structure that the present invention proposes, M
P2Connected mode and M
P1Roughly the same, the source end is connecting power supply, and drain terminal is connecting internal circuit, but M
P2Pipe is subjected to phase inverter inv
2Output terminal control, phase inverter inv
2Input end and preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal connect.Therefore, in the memory precharge stage, phase inverter inv
2Input end be charged to high level, the low level of its output can be with charge compensate pipe M
P2Open, and then make at preliminary filling fulgurite M
P1Be turned off back charge compensate pipe M
P2Still can charge to internal circuit.
Shown in operating process Fig. 6 of the present invention, in the circuit sequential relationship of each signal as shown in Figure 7, s wherein
nAnd w
mBe respectively word line and the bit line select signal of choosing after the decoding of column decoder and line decoder, C
BLnIt is the equivalent capacity of selected bit line.As shown in Figure 6, the operating process of this circuit can be divided into three phases:
1. preliminary filling fulgurite (M
P1) open stage (t in the sequential chart
1): when precharge operation begins, precharging signal (F
Pre) under jump to low level and make preliminary filling fulgurite (M
P1) open circuit equivalent electric capacity (C
d) carry out precharge.This moment, the line decoder and the column decoder of storer carried out decoded operation to the address, the word line (w in the storage array
m) and bit line select signal (s
n) all remain low level.Because (s
n) be low level, so bit line selects pipe to close, bit line did not have by precharge in this stage.
2. the bit-line pre-charge stage (t in the sequential chart
2): column decoder is prior to line decoder t
2Time bears results.At this moment, according to the column decoder result, respective bit line is selected signal (s
i) jump in the generation, jump it on along corresponding bit line being selected to manage (M
Ni) open, pre-charge circuit is connected with the bit line of being chosen.Simultaneously, precharging signal (F
Pre) remain low, preliminary filling fulgurite (M
P1) continuation conducting and and charge compensate pipe (M
P2) pairs of bit line equivalent capacity charging together.The bit line of being chosen by bit line select signal does not then carry out charging operations.
3. preliminary filling fulgurite (M
P1) dwell period (t in the sequential chart
3): line decoder is finished decoded operation, respective word (w
i) go up and jump the gating storage unit.Simultaneously, precharging signal (F
Pre) on jump to high level with preliminary filling fulgurite (M
P1) close.At this moment, if cell stores is " 1 " signal, then the NMOS pipe of storage unit is communicated with bit line with ground wire, beginning pairs of bit line equivalent capacity (C
BLj) discharge.Because the NMOS of storage unit pipe driving force is greater than charge compensate pipe (M
P2), so bit line will be discharged into low level, output drives phase inverter (inv
1) output " 1 " signal; If cell stores is " 0 " signal, then bit line and ground wire do not have connecting path, by charge compensate pipe (M
P2) continue pairs of bit line and be charged to supply voltage, output drives phase inverter (inv
1) maintenance output " 0 " signal.
Claims (1)
1. selective precharging circuit for memory with charging compensating structure is characterized in that: it comprises selective precharge unit, charge compensate unit and output driver element, and described selective precharge unit comprises precharge pipe M
P1Select pipe M with two or more bit lines
Ni, the charge compensate unit comprises charge compensate pipe M
P2With the second phase inverter inv
2, charge compensate pipe M
P1The source end connecting power supply, drain terminal is connecting internal circuit, charge compensate pipe M
P1Be subjected to precharging signal F
PrePipe M is selected in control, each bit line
NiAn end connect bit line in the storage array, the other end is connected in preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal and the second phase inverter inv of charge compensate unit
2, output driver element the first phase inverter inv
1Input end, charge compensate pipe M
P2The source end connecting power supply, drain terminal is connecting internal circuit, M
P2Pipe is subjected to the second phase inverter inv
2Output terminal control, the second phase inverter inv
2Input end and preliminary filling fulgurite M
P1With charge compensate pipe M
P2Drain terminal connect a described charge compensate unit and an equivalent capacitor C
dLink to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710035330A CN101110260B (en) | 2007-07-10 | 2007-07-10 | Selective precharging circuit for memory device with charging compensating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710035330A CN101110260B (en) | 2007-07-10 | 2007-07-10 | Selective precharging circuit for memory device with charging compensating structure |
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| Publication Number | Publication Date |
|---|---|
| CN101110260A CN101110260A (en) | 2008-01-23 |
| CN101110260B true CN101110260B (en) | 2010-05-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710035330A Expired - Fee Related CN101110260B (en) | 2007-07-10 | 2007-07-10 | Selective precharging circuit for memory device with charging compensating structure |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104978999A (en) * | 2014-04-03 | 2015-10-14 | 晶宏半导体股份有限公司 | Bit line multiplexer with precharge |
| CN115148243B (en) * | 2021-03-31 | 2024-05-14 | 长鑫存储技术有限公司 | Memory circuit, memory precharge control method and apparatus |
| EP4386753A1 (en) * | 2021-10-26 | 2024-06-19 | Huawei Technologies Co., Ltd. | Single-port memory |
| CN115236534B (en) * | 2022-07-29 | 2023-11-14 | 苏州浪潮智能科技有限公司 | Device and method for detecting voltage of RTC battery of server |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069828A (en) * | 1993-09-10 | 2000-05-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device having voltage booster circuit |
| CN1266266A (en) * | 1999-03-09 | 2000-09-13 | 因芬尼昂技术北美公司 | Capacitance coupled driving circuit |
-
2007
- 2007-07-10 CN CN200710035330A patent/CN101110260B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069828A (en) * | 1993-09-10 | 2000-05-30 | Kabushiki Kaisha Toshiba | Semiconductor memory device having voltage booster circuit |
| CN1266266A (en) * | 1999-03-09 | 2000-09-13 | 因芬尼昂技术北美公司 | Capacitance coupled driving circuit |
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| Publication number | Publication date |
|---|---|
| CN101110260A (en) | 2008-01-23 |
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Granted publication date: 20100519 Termination date: 20120710 |