CN101110179A - Plane display device structure - Google Patents
Plane display device structure Download PDFInfo
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- CN101110179A CN101110179A CNA2006101057290A CN200610105729A CN101110179A CN 101110179 A CN101110179 A CN 101110179A CN A2006101057290 A CNA2006101057290 A CN A2006101057290A CN 200610105729 A CN200610105729 A CN 200610105729A CN 101110179 A CN101110179 A CN 101110179A
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Abstract
A plane display structure is provided, which comprises a basal plate, a pixel array, a first level displacement memory unit and a second level displacement memory unit. The basal plate comprises a signal lead; the pixel array is positioned on the basal plate; the first level displacement memory unit is positioned at a first side of the pixel array and is coupled to the signal lead, so as to output a first scanning signal to the pixel array according to the triggering of a first initiation signal; the second level displacement memory unit is positioned at a second side of the pixel array is coupled to the signal lead to receive a second initiation signal via the signal lead.
Description
Technical field
The relevant a kind of plane display device structure of the present invention, and particularly relevant a kind of plane display device structure that shift register (shiftregister) circuit is placed on two side drives of panel odd even.
Background technology
Traditional monolateral driven sweep circuit is any side in the left and right sides that shift-register circuit is arranged at pel array (pixel matrix), yet when the design high resolving power, so monolateral type of drive will improve panel margo frontalis width.Along with the consumer requires under the compact demand of product, the design of bilateral driven sweep circuit is just given birth to thereupon.
Figure 1A and Figure 1B are a kind of gate driver circuit calcspars that United States Patent (USP) is disclosed for No. 20040217935.Shown in Figure 1A, shift register SRC_O
1, SRC_O
2Be arranged at a side of pel array (not being shown among the figure) in the odd level shift register, and odd level sweep signals such as sweep signal GL1, GL3 are provided respectively, to drive the odd column pixel.Shown in Figure 1B, shift register SRC_E
1, SRC_E
2Be arranged at the opposite side of pel array in the even level shift register, and sweep signal GL is provided respectively
2, GL
4Deng the even level sweep signal, to drive the even column pixel.
Shift register SRC_O
1Be to come output scanning signal GL according to start signal ST_O and clock signal CK_O that control circuit (not being shown among the figure) is provided
1, and shift register SRC_E
1Be that another start signal ST_E and the clock signal CK_E that provides according to control circuit comes output scanning signal GL
2Moreover, shift register SRC_O
2And SRC_E
2Then utilize shift register SRC_O respectively
1And SRC_E
1The drive signal S1 of output and S2 and come output scanning signal GL according to clock signal CKB_O and CKB_E respectively as start signal
3And GL
4Because shift register SRC_O
1And SRC_E
1Must use the different start signal ST_O and the ST_E of control circuit output respectively, produce sweep signal GL
1And GL
2, and whole shift register used four clock signal CK_O, CK_E, CKB_O and CKB_E altogether, all can improve the power attenuation of whole driving circuit.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of plane display device structure exactly.Directly the start signal of use first order shift register or output signal perhaps only use three clock signals to drive the shift register of odd even level as the start signal of second level shift register, effectively reduce the power attenuation of flat-panel screens.
According to purpose of the present invention, a kind of plane display device structure is proposed, comprise substrate, pel array, first order shift register and second level shift register.Substrate comprises a signal lead.Pel array is arranged on the substrate.First order shift register is arranged at first side of pel array, and is coupled to signal lead, and in order to the triggering according to first start signal, output first order sweep signal is to this pel array.Second level shift register is arranged at second side of pel array, and is coupled to signal lead, in order to receive one second start signal via signal lead.
According to purpose of the present invention, another kind of plane display device structure is proposed, comprise pel array, first order shift register and second level shift register.First order shift register is arranged at first side of pel array, in order to export first order sweep signal to pel array according to first clock signal and second clock signal.Second level shift register is arranged at second side of pel array, in order to export second level sweep signal to pel array according to second clock signal and the 3rd clock signal.In first sequential in the stage, first clock signal has the first accurate position, and second clock signal and the 3rd clock signal have the second accurate position; In stage, first clock signal and the 3rd clock signal have the second accurate position in second sequential, and second clock signal has the first accurate position; In stage, first clock signal and second clock signal have the second accurate position in the 3rd sequential, and the 3rd clock signal has the first accurate position.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, two preferred embodiments cited below particularly, and conjunction with figs. is elaborated as follows:
Description of drawings
Figure 1A and Figure 1B are the United States Patent (USP) case number 20040217935 a kind of gate driver circuit calcspars that disclosed.
Fig. 2 is a kind of plane display device structure calcspar according to first embodiment of the invention.
Fig. 3 is the analog clocking signal figure of Fig. 2 midplane display.
Fig. 4 is another trace configurations figure that receives first sweep signal according to second level shift register in the plane display structure of first embodiment of the invention.
Fig. 5 is the trace configurations figure that receives the start signal of first order shift register according to second level shift register in the plane display structure of first embodiment of the invention.
Fig. 6 is a kind of plane display device structure calcspar according to second embodiment of the invention.
Fig. 7 is a shift-register circuit structural drawing among Fig. 6.
Fig. 8 is the analog clocking signal figure of Fig. 6 midplane display.
Embodiment
First embodiment
Please refer to Fig. 2, it is a kind of plane display device structure calcspar according to first embodiment of the invention.Flat-panel screens 200 for example is a kind of amorphous silicon film transistor LCD (a-Si TFT LCD), and its structure comprises substrate 210, pel array 220, multi-stage shift register and data driver 230.Pel array 220 is arranged on the substrate 210.Multi-stage shift register, for example be to be arranged on the substrate 210, it comprises odd level shift registers such as first order shift register SR1, third level shift register SR3, and even level shift registers such as second level shift register SR2, fourth stage shift register SR4.Odd level shift register SR1, SR3 are the left sides that is arranged at pel array 220, and even level shift register SR2, SR4 are the right sides that is arranged at pel array 220.All shift registers are to use identical operations voltage VDD and VSS.
First order shift register SR1 receives third level sweep signal S3, and after the triggering via start signal STV, export first order sweep signal S1 according to the first clock signal CK1 and the 3rd clock signal CK3, via the first row pixel P1 of sweep trace L1 activation pel array 220, to receive data-driven
230 data-signal.Second level shift register SR2 is coupled to sweep trace L1, in order to receive first order sweep signal S1 with as required start signal.Second level shift register SR2 receives fourth stage sweep signal S4, and triggering via first order sweep signal S1 (start signal), export second level sweep signal S2 according to the second clock signal CK2 and the 4th clock signal CK4, with the secondary series pixel P2 of activation pel array 220, receive the data-signal of data driver 230.Next, odd level shift register SR3 ... reception next stage odd level sweep signal S5 ... and via previous stage odd level sweep signal S1 ... the triggering of (start signal), according to the first clock signal CK1 and the 3rd clock signal CK3, output odd level sweep signal S3 ... to pel array 220; Even level shift register SR4 ... reception next stage even level sweep signal S6 ... and via previous stage even level sweep signal S2 ... the triggering of (start signal), and according to the second clock signal CK2 and the 4th clock signal CK4, output even level sweep signal S4 ... to pel array 220.
Please refer to Fig. 3, it is the analog clocking signal figure of Fig. 2 midplane display 200.As shown in Figure 3, in sequential stage T1, start signal STV exports high levle, for example is 10V.First order shift register SR1 is that high levle is exported the have high levle first order sweep signal S1 of (10V) to pel array 220 according to the first clock signal CK1 in sequential stage T2 after start signal STV triggers.Then, second level shift register SR2 is that high levle is exported the have high levle second level sweep signal S2 of (10V) to pel array 220 according to the second clock signal CK2 in sequential stage T3 after first order sweep signal S1 triggers.By that analogy, in ensuing sequential, shift register SR3, SR4 ... just export in regular turn high levle (10V) sweep signal S3, S4 ... to pel array 220, reach in the purpose of panel odd even two side drives.
As mentioned above, second level shift register SR2 directly receives first order sweep signal S1 as start signal via sweep trace L1 in the flat-panel screens of present embodiment, not only can reach normal running in two side drives of panel odd even, and, therefore can effectively reduce the power attenuation and the cost of driving circuit owing to do not need additionally to provide another start signal by control circuit.
Though it is that example explains to receive sweep signal S1 as start signal that the present invention couples sweep trace L1 with second level shift register SR2, yet as shown in Figure 4, plane display device structure of the present invention also can be coupled to the sweep signal output terminal VOUT of first order shift register SR1 and the start signal input end IN of second level shift register SR2 with exterior domain signalization cabling 400 by pel array 220 on substrate 210.Second level shift register SR2 receives first order sweep signal S1 as start signal via signal lead 400.The sweep signal S1 that this design more can reduce first order shift register SR1 output is sent to the second level, right side shift register SR2 as signal delay that its start signal produced via pel array 220 left sides.
Perhaps as shown in Figure 5, plane display device structure of the present invention also can be coupled to the start signal input end IN of first order shift register SR1 and the start signal input end IN of second level shift register SR2 with exterior domain signalization cabling 500 by pel array 220 on substrate 210.Second level shift register SR2 directly utilizes start signal STV as required start signal.So long as the signal lead that couples first order shift register and second level shift register is set on substrate, make second level shift register receive first order shift register coherent signal as required start signal through signal lead thus, the start signal that needn't additionally use control circuit and provided, and reach purpose in two side drives of panel odd even, neither disengaging technical scope of the present invention.
Second embodiment
Please refer to Fig. 6, it is a kind of plane display device structure calcspar according to second embodiment of the invention.Flat-panel screens 600 for example is a kind of amorphous silicon film transistor LCD, and its structure comprises substrate 610, pel array 620, multi-stage shift register and data driver 630.Pel array 620 is arranged on the substrate 610.Multi-stage shift register, for example be to be arranged on the substrate 610, it comprises odd level shift registers such as first order shift register SR1, third level shift register SR3, and even level shift registers such as second level shift register SR2, fourth stage shift register SR4.Odd level shift register SR1, SR3 ... be the left side that is arranged at pel array 620, and even level shift register SR2, SR4 ... it is the right side that is arranged at pel array 620.
First order shift register SR1 receives third level sweep signal S3, and after the triggering via the first start signal STV1, export first order sweep signal S1 according to the first clock signal CK1 and the second clock signal CK2, the first row pixel P1 of activation pel array 620 is to receive the data-signal of data driver 630.Second level shift register SR2 receives fourth stage sweep signal S4, and after the triggering via the second start signal STV2, export second level sweep signal S2 according to the second clock signal CK2 and the 3rd clock signal CK3, the secondary series pixel P2 of activation pel array 620 is to receive the data-signal of data driver 630.Wherein the first start signal STV1 for example is by control circuit (not being shown among the figure) two the different start signals that provide with the second start signal STV2.
In addition, third level shift register SR3 receives level V sweep signal S5, and triggering via first order sweep signal S 1, according to the 3rd clock signal CK3 and the first clock signal CK1, output third level sweep signal S3, the 3rd row pixel P3 of activation pel array 620 is to receive the data-signal of data driver 630.Next, per three shift registers are one-period, be that shift register SR (i), SR (i+1) and SR (i+2) (i 〉=4) receive two-stage sweep signal S (i+2), S (i+3) and S (i+4) down respectively, and after the triggering via preceding two-stage sweep signal S (i-2), S (i-1) and S (i) (start signal), according to clock signal CK1 and CK2, CK2 and CK3 and CK3 and CK1, output scanning signal S (i), S (i+1) and S (i+2) are to pel array 620.
Please be simultaneously with reference to Fig. 7 and Fig. 8, it is respectively the gate driving analog clocking signal figure of shift-register circuit structural drawing and flat-panel screens 600 among Fig. 6.As shown in Figure 7, above-mentioned shift register SR (i) comprises 11 N-type metal oxide semiconductors (N-type Metal Oxide Semiconductor, NMOS) transistor M1～M11.The grid of input signal Si n input transistors M1 couples the source electrode of transistor M11, and as the start signal of shift register SR (i).In addition, the grid of transistor M2 and M4 receives two-stage sweep signal S (i+2) down.Clock signal C1 (=CK1, CK2 or CK3) couples the drain electrode of transistor M3, and the grid of clock signal C2 (=CK2, CK3 or CK1) oxide-semiconductor control transistors M6, M10 and M11.
As shown in Figure 8, the first clock signal CK1 comprises a plurality of high levle sequential Th and low level sequential T1, and high levle sequential Th and low level T1 alternately produce, and low level sequential T1 is the twice of high levle sequential.The sequential of the second clock signal CK2 is the sequential that the first clock signal CK1 postpones a high levle sequential Th, and the sequential of the 3rd clock signal CK3 is the sequential that the second clock signal CK2 postpones a high levle sequential Th.
In initial sequential stage T0, for the first order (i=1) shift register SR1, the input signal Si n i.e. first start signal STV1 is an output high levle (for example being 10V), and sweep signal S3 and clock signal C1 (=CK1) with C2 (=CK2) all export low level.Therefore, transistor M1, M3, M7 and M8 are conducting state among the shift register SR1, make that the voltage of node P1 is high levle, and transistor M4, M9 and M10 be not on-state, sweep signal S1 will (=CK1) low level be pulled to and be low level by clock signal C1 this moment.
At this moment, for the second level (i=2) shift register, input signal Si n promptly the second start signal STV2 be the output low level (for example be-10V), and clock signal C1 (=CK2) with C2 (=CK3) be low level.Therefore, transistor M1～M11 is all not on-state among the shift register SR2, makes sweep signal S2 also be low level.In like manner, to follow-up shift register SR3 ..., since its input signal Si n be preceding two-stage sweep signal S1 ... be all low level, and clock signal C1 and C2 are all low level.So shift register SR3 ... the sweep signal S3 of output ... be all low level.
Then, in the first sequential stage T1, for first order shift register SR1, input signal Si n (=STV1) be the output low level, clock signal C1 (=CK1) change high levle into, and clock signal C2 (=CK2) still be low level, at this moment, the voltage of node P1 is because of Bootstrap (bootstrap) effect is pulled to than high levle, makes the transistor M3 conducting of shift register SR1, and causes sweep signal S1 to be output as perfect clock signal C1 (=CK1) high levle.
For second level shift register SR2, input signal Si n (=STV2) be the output high levle, and clock signal C1 (=CK2) with C2 (=CK3) be all low level.The operational circumstances of first order shift register SR1 among the similar last sequential stage T0, the node P1 voltage of second level shift register SR2 is high levle, and sweep signal S2 is output as low level.
And for third level shift register SR3, start signal Sin is that sweep signal S1 also exports high levle, and clock signal C1 (=CK3) be low level, and clock signal C2 (=CK1) be high levle, therefore the transistor M10 conducting of shift register SR3, and the sweep signal S3 of output low level.By that analogy as can be known, sweep signal S4 ... be all low level.
Then, in the second sequential stage T2, for first order shift register SR1, input signal Si n (=STV1) be low level, clock signal C1 (=CK1) be low level, and clock signal C2 (=CK2) be high levle.The transistor M10 conducting of shift register SR1 makes sweep signal S1 be output as low level at this moment.
For second level shift register SR2, input signal Si n (=STV2) be the output low level, clock signal C1 (=CK2) be high levle, and clock signal C2 (=CK3) be low level.The operational circumstances of first order shift register SR1 among the similar last sequential stage T1, the voltage of node P1 still is high levle among the shift register SR2, make the transistor M3 conducting of shift register SR2, and sweep signal S2 is output as clock signal C1 (=CK2) high levle.
And for third level shift register SR3, start signal Sin is the output low level for sweep signal S1, and clock signal C1 (=CK3) with C2 (=CK1) be all low level.At this moment, the transistor M3 conducting of shift register SR3 makes sweep signal S3 be output as clock signal C1 (=CK3) low level.By that analogy as can be known, sweep signal S4 ... be all low level.
Then, in the 3rd sequential stage T3, for first order shift register SR1, input signal Si n (=STV1) be low level, clock signal C1 (=CK1) with C2 (=CK2) be all low level.Because the 3rd sweep signal S3 output high levle, make the transistor M2 conducting of shift register SR1, the voltage of node P1 is low level, and causes transistor M3 to close, so sweep signal S1 is a low level.
For second level shift register SR2, input signal Si n (=STV2) be the output low level, clock signal C1 (=CK2) be low level, and clock signal C2 (=CK3) be high levle.The operational circumstances of first order shift register SR1 among the similar last sequential stage T2, the transistor M10 conducting of shift register SR2 makes sweep signal S2 export low level.
And for third level shift register SR3, start signal Sin is the output low level for sweep signal S1, and clock signal C1 (=CK3) be high levle, and clock signal C2 (=CK1) be low level.The operational circumstances of second level shift register SR2 among the similar last sequential stage T2, the voltage of node P1 still is high levle among the shift register SR3, make the transistor M3 conducting of shift register SR2, and sweep signal S2 is output as clock signal C1 (=CK3) high levle.By that analogy as can be known, sweep signal S4 ... be all low level.Therefore, shift-register circuit only needs three clock signal CK1～CK3 can reach purpose in two side drives of panel odd even in the plane display device structure of present embodiment.
Though the present invention receives different start signal STV1 respectively with first order shift register SR1 and second level shift register SR2 and STV2 is that example explains, right plane display device structure of the present invention also can be as shown in Figure 2, and second level shift register SR1 couples sweep trace L1 to receive sweep signal S1 as start signal.Perhaps as shown in Figure 4, second level shift register SR2 is coupled to the sweep signal output terminal VOUT of first order shift register SR1 via pel array 220 on the substrate 210 with the set signal lead 400 of exterior domain, and receives first order sweep signal S1 as start signal via signal lead 400.Perhaps as shown in Figure 5, second level shift register SR2 also can be coupled to the start signal input end IN of first order shift register SR1 with the set signal lead 500 of exterior domain via pel array 220 on the substrate 210, and directly utilizes start signal STV as required start signal.So long as use three clock signal CK1～CK3, reach purpose, neither disengaging technical scope of the present invention in two side drives of panel odd even.
The advantage of above-mentioned two plane display device structures that embodiment discloses of the present invention is that second level shift register directly uses the sweep signal of the start signal of first order shift register or output as required start signal, perhaps odd even level shift-register circuit only need be utilized three clock signals, just can reach purpose in two side drives of panel odd even, all can effectively reduce the power attenuation and the cost of driving circuit, improve the market competitiveness of flat-panel screens.
In sum, though the present invention with two preferred embodiments announcement as above, yet it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various change that is equal to and retouching.Therefore, protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.
Claims (17)
1. plane display device structure comprises:
One substrate comprises a signal lead;
One pel array is arranged on this substrate;
One first order shift register is arranged at one first side of this pel array, and is coupled to this signal lead, in order to the triggering according to one first start signal, exports a first order sweep signal to this pel array; And
One second level shift register is arranged at one second side of this pel array, and is coupled to this signal lead, in order to receive one second start signal via this signal lead.
2. plane display device structure as claimed in claim 1, it is characterized in that this second start signal is this first start signal, this signal lead is coupled to an initial signal input part of this first order shift register, and this signal lead is to be disposed to be positioned at this pel array zone in addition on this substrate.
3. plane display device structure as claimed in claim 1, it is characterized in that this second start signal is this first order sweep signal, this signal lead is the one scan signal output part that is coupled to this first order shift register, and this signal lead is the one scan line that couples this pel array.
4. plane display device structure as claimed in claim 1, it is characterized in that this second start signal is this first order sweep signal, this signal lead is the one scan signal output part that is coupled to this first order shift register, and this signal lead is to be disposed to be positioned at this pel array zone in addition on this substrate.
5. plane display device structure as claimed in claim 1, it is characterized in that also comprising a third level shift register and a fourth stage shift register, wherein this first order sweep signal is the initial signal as this third level shift register, and a second level sweep signal of this second level shift register output is the initial signal as this fourth stage shift register.
6. plane display device structure as claimed in claim 1 is characterized in that this first order shift register and this second level shift register are to be arranged on this substrate.
7. plane display device structure as claimed in claim 1 is characterized in that it is an amorphous silicon film transistor liquid crystal display device structure.
8. plane display device structure comprises:
One pel array;
One first order shift register is arranged at one first side of this pel array, in order to export a first order sweep signal to this pel array according to one first clock signal and one second clock signal; And
One second level shift register is arranged at one second side of this pel array, in order to export a second level sweep signal to this pel array according to this second clock signal and one the 3rd clock signal;
Wherein, in one first sequential in the stage, this first clock signal has one first accurate position, and this second clock signal and the 3rd clock signal have one second accurate position; In stage, this first clock signal and the 3rd clock signal have this second accurate position in one second sequential, and this second clock signal has this first accurate position; In stage, this first clock signal and this second clock signal have this second accurate position in one the 3rd sequential, and the 3rd clock signal has this first accurate position.
9. plane display device structure as claimed in claim 8, it is characterized in that this first order shift register is to export this first order sweep signal to this pel array via the one scan line, and this second level shift register is to receive this first order sweep signal as an initial signal via this sweep trace.
10. plane display device structure as claimed in claim 8, it is characterized in that also comprising a substrate, in order to dispose this pel array, wherein this substrate comprises a signal lead, be arranged at this pel array with exterior domain, and couple this first order shift register and this second level shift register, and this first order shift register exports this first order sweep signal via this signal lead, with an initial signal as this second level shift register.
11. plane display device structure as claimed in claim 8, it is characterized in that also comprising a substrate, in order to dispose this pel array, wherein this substrate comprises a signal lead, be arranged at this pel array with exterior domain, and couple this first order shift register and this second level shift register, and an initial signal of this first order shift register is via this signal lead output, with the initial signal as this second level shift register.
12. plane display device structure as claimed in claim 8 is characterized in that also comprising a substrate, in order to dispose this pel array, wherein this first order shift register and this second level shift register are to be arranged on this substrate.
13. plane display device structure as claimed in claim 8, it is characterized in that also comprising a third level shift register and a fourth stage shift register, wherein this first order sweep signal is the initial signal as this third level shift register, and this second level sweep signal is the initial signal as this fourth stage shift register.
14. plane display device structure as claimed in claim 13, it is characterized in that this third level shift register is to export a third level sweep signal to this pel array according to the 3rd clock signal and this first clock signal, and this fourth stage shift register is to export a fourth stage sweep signal to this pel array according to this first clock signal and this second clock signal.
15. plane display device structure as claimed in claim 8 it is characterized in that this first accurate position is a high levle, and this second accurate position is a low level.
16. plane display device structure as claimed in claim 8, it is characterized in that this first clock signal comprises a plurality of first accurate bit timing with this first accurate position, this second clock signal is that this first clock signal postpones this first accurate bit timing, and the 3rd clock signal is this first accurate bit timing of this second o'clock clock pulse signal delay.
17. plane display device structure as claimed in claim 8 is characterized in that it is an amorphous silicon film transistor liquid crystal display device structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101057290A CN101110179A (en) | 2006-07-18 | 2006-07-18 | Plane display device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101057290A CN101110179A (en) | 2006-07-18 | 2006-07-18 | Plane display device structure |
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| Publication Number | Publication Date |
|---|---|
| CN101110179A true CN101110179A (en) | 2008-01-23 |
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ID=39042238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101057290A Pending CN101110179A (en) | 2006-07-18 | 2006-07-18 | Plane display device structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035216A (en) * | 2011-10-06 | 2013-04-10 | 株式会社日本显示器东 | Display device |
| CN107833550A (en) * | 2017-10-27 | 2018-03-23 | 友达光电（苏州）有限公司 | Display device and its clock pulse generator |
| CN108717843A (en) * | 2018-02-26 | 2018-10-30 | 友达光电股份有限公司 | Display device and gate driver thereof |
| CN109345994A (en) * | 2018-08-23 | 2019-02-15 | 友达光电股份有限公司 | Display device and driving method thereof |
| CN110828475A (en) * | 2018-08-13 | 2020-02-21 | 乐金显示有限公司 | Thin film transistor substrate and display device |
| CN113808654A (en) * | 2021-02-04 | 2021-12-17 | 友达光电股份有限公司 | Shift register |
-
2006
- 2006-07-18 CN CNA2006101057290A patent/CN101110179A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035216A (en) * | 2011-10-06 | 2013-04-10 | 株式会社日本显示器东 | Display device |
| US8982114B2 (en) | 2011-10-06 | 2015-03-17 | Japan Display Inc. | Display device |
| CN103035216B (en) * | 2011-10-06 | 2015-09-30 | 株式会社日本显示器 | Display device |
| US9299308B2 (en) | 2011-10-06 | 2016-03-29 | Japan Display Inc. | Display device |
| CN107833550A (en) * | 2017-10-27 | 2018-03-23 | 友达光电（苏州）有限公司 | Display device and its clock pulse generator |
| CN108717843A (en) * | 2018-02-26 | 2018-10-30 | 友达光电股份有限公司 | Display device and gate driver thereof |
| CN108717843B (en) * | 2018-02-26 | 2020-04-14 | 友达光电股份有限公司 | Display device and gate driver thereof |
| CN110828475A (en) * | 2018-08-13 | 2020-02-21 | 乐金显示有限公司 | Thin film transistor substrate and display device |
| CN110828475B (en) * | 2018-08-13 | 2024-03-29 | 乐金显示有限公司 | Thin film transistor substrate and display device |
| CN109345994A (en) * | 2018-08-23 | 2019-02-15 | 友达光电股份有限公司 | Display device and driving method thereof |
| CN113808654A (en) * | 2021-02-04 | 2021-12-17 | 友达光电股份有限公司 | Shift register |
| CN113808654B (en) * | 2021-02-04 | 2023-07-04 | 友达光电股份有限公司 | Shift register |
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