CN101107599B - 高速缓冲存储器控制方法和高速缓冲存储器控制装置 - Google Patents
高速缓冲存储器控制方法和高速缓冲存储器控制装置 Download PDFInfo
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- CN101107599B CN101107599B CN200680002425XA CN200680002425A CN101107599B CN 101107599 B CN101107599 B CN 101107599B CN 200680002425X A CN200680002425X A CN 200680002425XA CN 200680002425 A CN200680002425 A CN 200680002425A CN 101107599 B CN101107599 B CN 101107599B
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- 238000000034 method Methods 0.000 title claims description 26
- 230000005055 memory storage Effects 0.000 claims description 9
- 239000003595 mist Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000001404 mediated effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/608—Details relating to cache mapping
- G06F2212/6082—Way prediction in set-associative cache
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP081544/2005 | 2005-03-22 | ||
JP2005081544 | 2005-03-22 | ||
PCT/JP2006/305676 WO2006101113A1 (ja) | 2005-03-22 | 2006-03-22 | キャッシュメモリ制御方法およびキャッシュメモリ制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101107599A CN101107599A (zh) | 2008-01-16 |
CN101107599B true CN101107599B (zh) | 2011-09-21 |
Family
ID=37023773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200680002425XA Active CN101107599B (zh) | 2005-03-22 | 2006-03-22 | 高速缓冲存储器控制方法和高速缓冲存储器控制装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7636812B2 (zh) |
EP (1) | EP1862906A4 (zh) |
JP (1) | JP4080527B2 (zh) |
CN (1) | CN101107599B (zh) |
WO (1) | WO2006101113A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4635063B2 (ja) * | 2008-03-11 | 2011-02-16 | 株式会社東芝 | キャッシュメモリ制御回路及びプロセッサ |
US8589629B2 (en) * | 2009-03-27 | 2013-11-19 | Advanced Micro Devices, Inc. | Method for way allocation and way locking in a cache |
US8244982B2 (en) * | 2009-08-21 | 2012-08-14 | Empire Technology Development Llc | Allocating processor cores with cache memory associativity |
JP6012263B2 (ja) * | 2011-06-09 | 2016-10-25 | 株式会社半導体エネルギー研究所 | 半導体記憶装置 |
US9753858B2 (en) | 2011-11-30 | 2017-09-05 | Advanced Micro Devices, Inc. | DRAM cache with tags and data jointly stored in physical rows |
US8984368B2 (en) | 2012-10-11 | 2015-03-17 | Advanced Micro Devices, Inc. | High reliability memory controller |
US9400544B2 (en) | 2013-04-02 | 2016-07-26 | Apple Inc. | Advanced fine-grained cache power management |
US8984227B2 (en) * | 2013-04-02 | 2015-03-17 | Apple Inc. | Advanced coarse-grained cache power management |
US9396122B2 (en) | 2013-04-19 | 2016-07-19 | Apple Inc. | Cache allocation scheme optimized for browsing applications |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5845309A (en) * | 1995-03-27 | 1998-12-01 | Kabushiki Kaisha Toshiba | Cache memory system with reduced tag memory power consumption |
US6038647A (en) * | 1995-12-06 | 2000-03-14 | Fujitsu Limited | Cache memory device and method for providing concurrent independent multiple accesses to different subsets within the device |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5875464A (en) * | 1991-12-10 | 1999-02-23 | International Business Machines Corporation | Computer system with private and shared partitions in cache |
JPH0950401A (ja) * | 1995-08-09 | 1997-02-18 | Toshiba Corp | キャッシュメモリ及びそれを備えた情報処理装置 |
US6351788B1 (en) | 1996-10-30 | 2002-02-26 | Hitachi, Ltd. | Data processor and data processing system |
JPH11139216A (ja) | 1997-11-12 | 1999-05-25 | Primo Hanbai Kk | 車載用機器のホルダー装置 |
GB9727485D0 (en) * | 1997-12-30 | 1998-02-25 | Sgs Thomson Microelectronics | Processing a data stream |
JP2000099399A (ja) | 1998-09-19 | 2000-04-07 | Apriori Micro Systems:Kk | ウェイ予測型キャッシュメモリとそのアクセス方法 |
KR100351504B1 (ko) * | 2000-06-05 | 2002-09-05 | 삼성전자 주식회사 | 캐쉬 메모리, 그의 전력 소비 절감 방법 그리고 캐쉬메모리를 구비하는 데이터 처리 시스템 |
JP2002342163A (ja) * | 2001-05-15 | 2002-11-29 | Fujitsu Ltd | マルチスレッドプロセッサ用キャッシュ制御方式 |
US6823426B2 (en) * | 2001-12-20 | 2004-11-23 | Intel Corporation | System and method of data replacement in cache ways |
US7055004B2 (en) * | 2003-09-04 | 2006-05-30 | International Business Machines Corporation | Pseudo-LRU for a locking cache |
US7516275B2 (en) * | 2006-04-25 | 2009-04-07 | International Business Machines Corporation | Pseudo-LRU virtual counter for a locking cache |
-
2006
- 2006-03-22 WO PCT/JP2006/305676 patent/WO2006101113A1/ja active Application Filing
- 2006-03-22 CN CN200680002425XA patent/CN101107599B/zh active Active
- 2006-03-22 JP JP2007509291A patent/JP4080527B2/ja active Active
- 2006-03-22 EP EP06729643A patent/EP1862906A4/en not_active Withdrawn
- 2006-03-22 US US11/720,751 patent/US7636812B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5845309A (en) * | 1995-03-27 | 1998-12-01 | Kabushiki Kaisha Toshiba | Cache memory system with reduced tag memory power consumption |
US6038647A (en) * | 1995-12-06 | 2000-03-14 | Fujitsu Limited | Cache memory device and method for providing concurrent independent multiple accesses to different subsets within the device |
Also Published As
Publication number | Publication date |
---|---|
JPWO2006101113A1 (ja) | 2008-09-04 |
US20090235028A1 (en) | 2009-09-17 |
EP1862906A4 (en) | 2009-01-07 |
WO2006101113A1 (ja) | 2006-09-28 |
CN101107599A (zh) | 2008-01-16 |
EP1862906A1 (en) | 2007-12-05 |
US7636812B2 (en) | 2009-12-22 |
JP4080527B2 (ja) | 2008-04-23 |
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Effective date of registration: 20151106 Address after: Kanagawa Patentee after: SOCIONEXT Inc. Address before: Osaka Japan Patentee before: Matsushita Electric Industrial Co.,Ltd. |
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Effective date of registration: 20210224 Address after: 2179, 2nd floor, building D, 33, 99 Kechuang 14th Street, economic and Technological Development Zone, Daxing District, Beijing (centralized office area) Patentee after: Beijing yisiwei Computing Technology Co.,Ltd. Address before: Kanagawa Prefecture, Japan Patentee before: SOCIONEXT Inc. |
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Address after: No. 2179, 2nd Floor, Building D, Building 33, No. 99, Kechuang 14th Street, Economic and Technological Development Zone, Daxing District, Beijing 100176 (centralized office area) Patentee after: Beijing ESWIN Computing Technology Co.,Ltd. Address before: No. 2179, 2nd Floor, Building D, Building 33, No. 99, Kechuang 14th Street, Economic and Technological Development Zone, Daxing District, Beijing 100176 (centralized office area) Patentee before: Beijing yisiwei Computing Technology Co.,Ltd. |