CN101051892A - Enciphering device and method for CPU special data - Google Patents
Enciphering device and method for CPU special data Download PDFInfo
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Abstract
Being setup in chip containing CPU, the encryption device includes following parts: being setup between CPU system and external data transmission, an encryption unit is in use for decrypting/encrypting partial data based on physical address for reading/writing data by CPU system; being connected to CPU system and the said encryption unit, a external storage controller is in use for sending data to be decrypted / encrypted to the encryption unit, as well as sending not encrypted data or data not needed to encrypted to CPU directly. Using symmetrical grouped data encryption technique to implement encrypting partial data for data dedicated to CPU, the disclosed encryption device and method is a relative independent unit in hardware so as to influence on hardware of original system slightly. Features are: easy of realization, security, and high effect. The invention is applicable to hardware system of any computer.
Description
Technical field
The present invention proposes the device and method in a kind of hardware system that how data ciphering method is applied to contain CPU; in particular a kind of how grouped data encryption method (Block cipherencryption) is applied to the protection of the outer CPU exclusive data of sheet and the device and method of use; under the prerequisite that guarantees system safety, make the performance of system and operating efficiency be unlikely to fall too lowly.Simultaneously because apparatus of the present invention and method are the address choice encryptions, its address choice part be in fact again one can self-defining encryption method, so the present invention is again a kind of double encryption approach.
Background technology
Along with the continuous development of computer technology, to use more and more widely, function is also more and more; it is more and more huger that corresponding software programs also becomes; can't be placed in the sheet together with CPU at all, and can only be stored in the outside of chip, this just has higher requirement for the protection of technology such as software.If do not take some safeguard measures, that works laboriously to spend the software of huge fund exploitation, may will be plagiarized by others in the twinkling of an eye and go.Though in the law aspect to protection of Intellectual Property Rights in continuous reinforcement, protect at technological layer, the technical threshold of improve plagiarizing remains essential.
In order to improve data security, data ciphering method becomes and becomes increasingly complex, and for example, wire transmission data service interface specification (DOCSIS) utilizes the integrality of information transmission to encrypt, and once once is being considered to perfect.But 2002, the TCNISO tissue was just finished with a very simple method and has been cracked, and sees the 83rd page of Hacking the Cable Modem ISBN 1-59327-101-8 for details.
Present data encryption technology is divided into two big class, rivest, shamir, adelman and symmetric encipherment algorithms.In the rivest, shamir, adelman, what use was commonplace now is RSA public key encryption method, and the advantage of this cryptographic algorithm is to use convenient, flexible, transmission side's public key encryption file, the recipient obtains the data that need with private key deciphering, not only convenient but also safety.But this cryptographic algorithm is compared with symmetric encipherment algorithm, under the situation that cracks difficulty on an equal basis, the key and the complicated more loaded down with trivial details computations that need several double-lengths, if, will reduce the running speed and the performance of system greatly so this cryptographic algorithm is applied in the cpu system runs software program.
Comparatively speaking, very ripe through the 3DES development so far based on the Advanced Encryption Standard (AES) of symmetrical grouped data encryption technology from DES, be acknowledged as best data ciphering method at present.This AES encryption method is used 128-256 position key, and each encrypting and decrypting all needs the calculating of tens rounds, theoretically, can't crack (utilizing prior art means and not oversize time) now, and this has just improved the fail safe of software program greatly.But simultaneously, expend tens machine clocks carries out encryption and decryption to CPU more at every turn, also make the speed of whole system operation reduce (still having superiority) greatly but compare asymmet-ric encryption method, can certainly reduce the machine clock number of some encryption and decryption, but like that just must increase transistorized quantity in the chip, can make the cost of chip roll up.
Existing other symmetrical grouped data encryption method also has Lucifer, LOKI, IDEA, GOST, CAST, RC5, Blowfish, Madryga, FEAL, REDOC, Khufu, MMB, SAFER, 3-WAY, Crab etc., and their modification and combination cascade etc., the situation that the same DES of these cryptographic algorithm, 3DES and AES run into is the same, when having improved the deciphering data difficulty, also reduced the performance and the operational efficiency of system more or less.
From top description to prior art as can be seen, in the operation and protection of cpu system, symmetrical grouped data encryption technology has advantage clearly, but simultaneously because it greatly reduces the performance and the efficient of system, still existing needs improved place.At this situation; the present invention improves symmetrical grouped data encryption technology in line with adding excellent principle on excellent, is applied in the encryption and protection of CPU exclusive data; under the prerequisite that guarantees system safety, make systematic function and operating efficiency be unlikely to reduce too much as much as possible for this reason.
Summary of the invention
The object of the present invention is to provide a kind of encryption device and method of CPU exclusive data, symmetrical grouped data encryption technology is applied in the encryption of CPU exclusive data, and the mode that adopts part to encrypt, guarantee the fail safe of software program and efficient and the speed that CPU works.
Technical scheme of the present invention comprises:
A kind of encryption device of CPU exclusive data, it is arranged in the chip that contains CPU, wherein, comprising: a ciphering unit that is provided with between cpu system and external data transmission is used for the read/write data of described cpu system is carried out separating/encrypting of partial data according to physical address; And an outer memory controller connects described cpu system and described ciphering unit simultaneously, be used for separating/enciphered data is through described ciphering unit with waiting, and with clear data or do not need enciphered data directly to transmit with described cpu system.
Described device, wherein, described ciphering unit also comprises a register, is used for configuration and need separates/the enciphered data physical address; One decoder is used for the physical address that the numerical value and the cpu system of register are sent lumped together and deciphers, and judges whether the data of this address correspondence need to separate/encrypt; The grouped data encryption equipment of one band bypass after being used for when carrying out transfer of data with described cpu system corresponding data being separated/encrypting according to the configuration of described register, transmits with described outer memory controller again; One key is stored in the encryption of separating that is used for described grouped data encryption equipment in the chip that contains CPU.
Described device, wherein, described cryptographic algorithm is symmetrical grouped data encryption method.
Described device, wherein, described symmetrical grouped data encryption method comprises DES, 3DES, AES, Lucifer, LOKI, IDEA, GOST, CAST, RC5, Blowfish, Madryga, FEAL, REDOC, Khufu, MMB, SAFER, 3-WAY, Crab and their modification, combination and cascade.
A kind of encryption method of CPU exclusive data, it may further comprise the steps:
A, to the outer read/write data of cpu system and sheet,, separate/encryption according to its physical address by a ciphering unit according to predetermined configurations selection portion divided data, outside described cpu system and one, transmit between the memory controller;
B, to need not separate/data of encryption described cpu system and described outside directly transmission between the memory controller;
C, described outer memory controller together and between outside the sheet transmit all encryptions and clear data.
Described method, wherein, described ciphering unit adopts symmetrical grouped data cryptographic algorithm.
Described method, wherein, described predetermined configurations for separating/physical address of enciphered data, and be stored in the register; Simultaneously in described ciphering unit, also be provided with a decoder, be used for the physical address that the numerical value and the cpu system of described register are sent lumped together and decipher, that the data of judging this address correspondence need encryption and decryption or do not need.
The encryption device of a kind of CPU exclusive data provided by the present invention and method, owing to adopt symmetrical grouped data encryption technology to realize the part of CPU exclusive data is encrypted, for any one CPU (described cpu system may contain a plurality of CPU), for any one process all is transparent, so can not influence the execution of any software program; Simultaneously; encryption method of the present invention can be a relatively independent unit on hardware; hardware influence for original system is little; be easy to realize, but, all be one wall for the outer any parts of sheet; whole system has been played protective effect; therefore the inventive method has safety, efficiently with the characteristics that are easy to realize, can be applicable in any computer hardware system.
Description of drawings
Fig. 1 is the structured flowchart of hardware system of the present invention, and ciphering unit of the present invention residing position in the whole system structure;
Fig. 2 is the structured flowchart of ciphering unit of the present invention shown in Fig. 1;
Fig. 3 is the instance graph that the present invention uses the AES grouping encryption method;
Fig. 4 is the physical address space encrypted partition figure of example of the present invention shown in Figure 3;
Fig. 5 is that example of the present invention shown in Figure 3 is used for selecting between encrypted area and the register definitions table of concrete encryption address.
The specific implementation method
Below in conjunction with accompanying drawing, will be described in more detail each preferred embodiment of the present invention.
It is generally acknowledged, data ciphering method is complicated more then crack difficult more, just relatively safe more, but encryption method is complicated more simultaneously, then system effectiveness is low more, and therefore from the surface, the raising of cryptographic means and the raising of system effectiveness are a pair of paradox, badly take into account simultaneously, this is not in fact not entirely entirely so.For general data, for example picture or word or file etc. even have only small part to be known by others, are also divulged a secret, because the fragment of this data all has independently meaning.But for the CPU exclusive data, it is with the general data difference, very strong logicality and integrality requirement are arranged, that is to say, its fragment does not have independently meaning, though a part of data learnt by others, also meaningless, because can't know integral body by inference, so that whole procedure remains is safe from some bitty parts.
Apparatus of the present invention method is applied to symmetrical grouped data encryption technology in the encryption of CPU exclusive data, guaranteed the fail safe of software program, the said symmetrical grouped data cryptographic algorithm of the present invention, all symmetrical grouped data cryptographic algorithm that comprise existing and later appearance, and their modification and combination, cascade etc., as long as the disposed of in its entirety means of its encrypting and decrypting meet the feature of symmetrical grouped data cryptographic algorithm, all should belong to the scope that the present invention is contained.The CPU exclusive data refers to that cpu system in the feed uses and the data that can not be used by miscellaneous equipment, if contain a plurality of CPU in the cpu system, the CPU exclusive data can be used by a CPU or a plurality of CPU shared.
The feature of described symmetrical grouped data cryptographic algorithm comprises: (1) encrypting and decrypting uses identical key; (2) encrypted grouping expressly the ciphertext after (initial data) and the encryption have identical data width (figure place); (3) all it doesn't matter for the other parts only relevant with encrypted grouping clear data, key and cryptographic algorithm and expressly ciphertext of the ciphertext behind the block encryption.
Apparatus of the present invention and method and the characteristics that have integrality require strong according to CPU exclusive data logicality, change and be encrypted as part encryption selectively in full, both guaranteed that whole data can't be cracked, simultaneously because just part is encrypted, the unencryption part can directly pass in and out the cpu system kernel, compare with encrypting in full, improved the speed of service of software program, the performance of whole system and operating efficiency are significantly improved.
Ciphering unit of the present invention comprises four parts: key, register, decoder and grouped data encryption equipment, as shown in Figure 2, key is exactly the calculating parameter that the grouped data cryptographic algorithm is used, just the password of encrypting and decrypting.For symmetric encryption method, the used password of encryption and decryption is identical, so only need a key.If use various symmetrical grouped data cryptographic algorithm to make up cascade etc., this key is the combination of each single algorithm secret key in fact, so can still think a key.
Described register is the interface that Hardware Design person provides for the user of system; system user (software program designer) can pass through this interface; in whole physical address space, mark off between concrete encrypted area; selection is encrypted the data of which address; just, select a suitable encipherment protection scheme according to the needs of software program.
Described decoder then is the physical address that the numerical value in the register and cpu system are sent to be lumped together decipher, and judges that the data of this address correspondence need encryption and decryption or unwanted.The grouped data encryption equipment is the module that contains the grouped data enciphering and deciphering algorithm of bypath system, it decides according to the judged result of decoder and carries out what concrete data manipulation, if being this address, the result that decoder is judged is encryption and decryption address not, then it is responsible for the direct bypass of data is gone over, give cpu system or outer memory controller, if judged result is to need encryption and decryption, then use key and grouped data enciphering and deciphering algorithm to the advanced row of data encryption and decryption earlier, and then send, give cpu system or outer memory controller.
Described register and decoder are core of the present invention places, they finish the selection to data encryption and decryption address jointly, so register is appreciated that into the first road password of system encryption, decoder is equivalent to cooperate an encryption and decryption " algorithm " of this first road password, and real key is the second road password, the grouped data encryption equipment is the second road enciphering and deciphering algorithm, so the present invention is again a double encryption approach, and this is another advantage of selective encryption.
CPU exclusive data in apparatus of the present invention and the method only refers to the variable used in the software program that uses for CPU and the program and other intermediate data etc., and this part data is only used for CPU, can not be by the outer miscellaneous equipment use of sheet.
Part of the present invention is encrypted, comprise and can be as required the data of 0% to 100% address correspondence in the encrypted partition being encrypted, can select key component is encrypted in full, can unimportant part or system's common sparing (the common data of using of cpu system and sheet external equipment) not encrypted or the like yet, because the logicality of CPU exclusive data is very strong, the mode that part is encrypted has increased the difficulty of definite encryption section, what can't distinguish from angle-of-attack, and what is clear data for enciphered data at all, therefore can not effectively attack.
Of the present invention interior CPU number is not defined as 1, and be still effective for multi-CPU system the inventive method.Be the structured flowchart of hardware system of the present invention as shown in Figure 1, and ciphering unit of the present invention residing position in the whole system structure.Wherein cpu system can be a single cpu, or multi-CPU system, can also comprise functional units such as MMU and Cache, what it was outwards exported is physical address, data are initial data, i.e. unencrypted data, and what its was accepted also is initial data, promptly separate overstocked data, clear data and data decryption all be initial data.
Ciphering unit of the present invention is between cpu system and the outer memory controller, have bypath system, its effect is that the data of coming from cpu system are selected to encrypt, and will select data encrypted to give outer memory controller then, and not need the direct bypass of enciphered data to go over; Give cpu system behind the data decryption of the encryption that will come from outer memory controller simultaneously, the direct bypass of the data of really not encrypting is gone over.Outer memory controller is responsible for the outer memory of sheet is read and write.
It may be noted that, because ciphering unit of the present invention comprises controlled data bypass circuit, so behind ciphering unit, some is encrypted so-called " initial data ", some may really not encrypted, and just bypass is gone over, but for the hardware cell after the ciphering unit, comprise the various hardware devices that sheet is outer, which they have no way of distinguishing is the data of really encrypting, which is the data of really not encrypting, so can only think it all is enciphered data.And the data that (outer memory controller) comes from the ciphering unit back, ciphering unit can distinguish which be the data of really encrypting which be initial data, it can give cpu system with the direct bypass of data of originally not encrypting, just the data of really encrypting being decrypted, is initial data so cpu system obtains forever.
As Fig. 2 is the structured flowchart of ciphering unit of the present invention, and it comprises four parts: key, register, decoder and grouped data encryption equipment.
Described key is the calculating parameter that the grouped data cryptographic algorithm is used, because the grouped data cryptographic algorithm is symmetric encipherment algorithm, so what use when data encryption and deciphering is same key.Because key uses the difference of figure place, also different when the concrete operation with a kind of cryptographic algorithm, AES cryptographic algorithm for example, when key was 128, calculating the wheel number was 10 times, when key is 196, calculating the wheel number is 12 times, and when key was 256, calculating the wheel number was 14 times.Key is the most critical part of data ciphering and deciphering, so must guarantee being perfectly safe of key itself, key is kept in the sheet, must guarantee all can't obtain with existing any technical method.
Described register and decoder are functions peculiar unit in apparatus of the present invention and the method, and the numerical value of register can be provided with as required voluntarily by software program.Register is the interface that Hardware Design person provides for software program, and the software program designer can pass through this interface, and whole physical address space is specifically divided, and selects which address date is carried out encryption and decryption.Decoder then is the reference address that the numerical value in the register and cpu system are sent to be lumped together decipher, and the data of judging this address correspondence need encryption and decryption or unwanted, and tells the grouped data encryption equipment this decode results.
The register of apparatus of the present invention and method and decoder are finished the selection of data encrypting and deciphering address jointly, it can be to the full encryption and decryption of data in certain interval in the physical address (for example FFFFF000-FFFFFFFF interval), also can be to the data in certain interval (for example 40000000-4FFFFFFF interval) encryption and decryption not entirely, also can (for example minimum 8 bit address A7-A0 be x11xxxxx to being in certain address section (for example 10000000-3FFFFFFF) and having certain address feature, wherein " x " can also can be " 1 " for " 0 ") data carry out encryption and decryption, thereby realize data encrypting and deciphering to the address correspondence of 0-100%.
The inventive method is when carrying out the part encryption, the address feature not necessarily " linear " that needs the data of encryption and decryption, promptly, can be the part position of address or certain self-defined computing (coding and decoding) that the data in whole position and the register are participated in together, so the numerical value in the register is actually the first road password of system encryption, and real key is the second road password, therefore, make the assailant have no way of grasping encryption and decryption data and exist in which part, this has increased the difficulty that system software program is decrypted again.
It may be noted that; apparatus of the present invention and method are protection cpu system exclusive data; mainly software program proposes; if some data is that outer other system of cpu system and sheet is shared in the external memory storage; that must be opened this part physical address space; promptly can not encrypt, otherwise external system can't not handled these shared datas because of there being key etc. this partial data.
The grouped data encryption equipment of apparatus of the present invention and method is the place that data are carried out concrete encryption and decryption, and it determines concrete processing procedure according to the result that decoder is sent.If it is the address that data do not need encryption and decryption that decoder is determined this address, the grouped data encryption equipment will be left intact corresponding data (read data that write data that cpu system is sent or outer memory controller transmission come) so, and directly bypass is sent.If it is the address that data need encryption and decryption that decoder is determined this address, the grouped data encryption equipment will be encrypted corresponding data (write data that cpu system is sent) or deciphering (read data that outer memory controller transmission comes) so, and then send.
The write operation process of cpu system of the present invention comprises:
As shown in Figure 1, when the cpu system in apparatus of the present invention and the method need be write outside the sheet with certain data (initial data), it will export a physical address and an initial data, and physical address is exactly the particular location that these data will be deposited outside sheet.This physical address is fed to ciphering unit and outer memory controller.
As shown in Figure 2, the physical address that cpu system of the present invention sends is delivered to the decoder of ciphering unit, decoder is put data in the register and this address together and is deciphered, and determines whether the data of this address correspondence need to encrypt, and result notification grouped data encryption equipment.
If the decode results of decoder is need not encrypt, the grouped data encryption equipment does not just deal with direct bypass to the write data of cpu system and gives outer memory controller so.If the decode results of decoder is to need to encrypt, the grouped data encryption equipment is encrypted the write data of cpu system with regard to using key and cryptographic algorithm so, and the enciphered data that obtains after encrypting is given outer memory controller again.Only after the grouped data encryption equipment had been finished the operation that needs (data bypass is sent or encrypted earlier and send), outer memory controller just can really start.
As Fig. 1, after described ciphering unit is finished the operation that needs, outer memory controller starts and the responsible enciphered data (can be initial data, can be the data of really encrypting also, but be referred to as enciphered data) that ciphering unit is sent here is written in the appropriate address of external memory storage.So far, cpu system is all finished the write operation of external memory.
The read operation process of cpu system of the present invention comprises:
As shown in Figure 1, need be outside sheet during certain address reading data of certain memory as CPU, cpu system sends the physical address of read command and desired data, and this address is fed to ciphering unit and outer memory controller.
Described outer memory controller is received read command and the physical address that cpu system is sent, and directly outside sheet the data that need is read, and is given ciphering unit the data of reading (no matter whether being that the data of really encrypting are referred to as enciphered data).
As shown in Figure 2, deliver to the physical address of ciphering unit and in fact given decoder, decoder is put the data in the register and this address together and is deciphered, and it is overstocked whether the data of determining this address correspondence are added, and gives the grouped data encryption equipment this judged result.Grouped data encryption equipment in the described ciphering unit is handled the read data that outer memory controller is sent here according to the judged result that decoder is sent here.
If the judged result of this decoder is: the data of this address correspondence are not added overstocked, cpu system is given in the direct bypass of read data that grouped data encryption equipment is just sent outer memory controller here, and the data that the notice cpu system needs are ready, so far, the cpu system operation of reading outer deposit data is finished.
If the judged result of decoder is: the data of this address correspondence add overstocked really, that grouped data encryption equipment is decrypted with regard to the read data of sending here with key and the external memory controller of data decryption algorithm, after deciphering is finished, give cpu system with the data (initial data) that deciphering obtains, and the data that the notice cpu system needs are ready, so far, the cpu system operation of reading outer deposit data is finished.
As can be seen from the above, cpu system of the present invention is when the external memory write data, so long as do not need ciphered data, just directly outer memory controller is given in bypass; When cpu system during to the external memory read data, as long as the data that outer memory controller is read are not added overstocked, just can give cpu system the direct bypass of these data, so just saved a large amount of encryption and decryption time (each several), made the operating efficiency of system increase significantly than the full text encryption method to tens machine clocks that do not wait.
Simultaneously, because where encrypted the assailant does not know, even if it can be known, but it does not know key again, so just can't decode, the partial data that the logicality of software program and the requirement of integrality make the assailant obtain is meaningless, and this has just guaranteed the fail safe of cpu system.Fail safe of the present invention and high efficiency come to this and embody.Moreover as can be seen, ciphering unit of the present invention has relative independentability from the structured flowchart of Fig. 1, can add up very easily in any hardware system, and the present invention that Here it is has the advantage that is easy to realize again.
Figure 3 shows that a concrete application example of apparatus of the present invention and method, but this example should not be construed as any limitation of the invention.Especially, the present invention not merely is applicable to the AES encryption method, and the present invention is applicable to all encryption methods that meet symmetrical block encryption algorithm feature, comprises their modification, combination and cascade etc.What similarly, relate in this example all can not produce any restriction to the present invention about the number of CPU and data bits etc.
Be the exemplary construction block diagram that a present invention uses AES grouped data encryption method as shown in Figure 3, wherein the part in the frame of broken lines is equivalent to the grouped data encryption equipment among Fig. 2.
The full name of AES is Advanced Encryption Standard, i.e. Advanced Encryption Standard.This project is proposed by American National Standard technical research institute, and is new federal information encryption standard (FIPS PUB 197) by U.S. government's approval, and this standard is the best grouped data encryption method of generally acknowledging at present.The designer of the Rijndael algorithm that AES adopts is that (Katholieke Universiteit Leuven, ESAT-COSIC), the name of algorithm is from combination alphabetical in two people's names for Joan Daemen (Proton World Int.l) and VincentRijmen.Rijndael is the block encryption algorithm of a symmetry, and block length and key length are all variable, can be appointed as 128 bits, 192 bits and 256 bits respectively separately.But the data packet length among the AES has only adopted 128 bits among the Rijndael, and do not use 192 and 256 bits, key length and Rijndael's is consistent, also is respectively 128 bits, 192 bits and 256 bits, and is called as AES-128, AES-192 and AES-256 respectively.
The application that below specifies apparatus of the present invention and method is as follows:
At first, The Hardware Design person is according to principle of the present invention, selecting AES is the cryptographic algorithm of CPU exclusive data, select key length and determine that according to this key length AES-128 or AES-192 or AES-256 are concrete cryptographic algorithm, again according to every specific requirement of this cryptographic algorithm, determine hardware block diagram---as accompanying drawing 3, it comprises one first multi-channel gating device (multi-channel gating device W), be used in described cpu system write data process, ciphered data is not directly sent outside sheet, and connect an AES encryption equipment, the needs ciphered data is encrypted the back by this AES encryption equipment outside sheet, send by this first multi-channel gating device; One second multi-channel gating device (multi-channel gating device R), be used at described cpu system reading data course, to there not being ciphered data directly to send to described cpu system, and connect an AES decipher, the needs decrypted data is sent to described cpu system by this second multi-channel gating device by this AES decipher deciphering back; And cryptographic algorithm is accomplished in " the AES encryption equipment " of accompanying drawing 3, decipherment algorithm is accomplished in " the AES decipher " of accompanying drawing 3, it should be noted that the hardware of above-mentioned AES encryption equipment and AES decipher is realized adopting same module.
Start concrete physical address and other requirement that back article one instruction is deposited according to cpu system again, The Hardware Design person divides whole physical space.The principle of dividing is to have a fixing full encryption address space at least, to comprise cpu system in this space and start back article one instruction, can also divide some full encryption spaces or part as required again and encrypt the space, the encryption space that some can be selected by register is preferably divided in the flexibility of and data encryption easy to use for software.
Illustrate here that why the start-up portion of program must be encrypted entirely.Because, the assailant always attempts to find earlier the start-up portion of program, go to guess along a thinking what remaining part can be then, if beginning one section has been decrypted, just might threaten whole procedure, so the full encryption of start-up portion to program can increase the decoding difficulty, this is extremely important also very necessary.As long as the start-up portion of program can't be decrypted, what that assailant faced is a tangled skein of jute that can not find head forever, and the fail safe of whole procedure just can be protected.
Provided distribution diagram between apparatus of the present invention and physical address space encrypted area of method as Fig. 4.Because article one that CPU carries out in this example instruction is placed among the FFFFFFF0, so the 64KB space of FFFF0000-FFFFFFFF correspondence is warded off between fixing full encrypted area.Simultaneously the space of FF000000-FFFEFFFF correspondence is warded off between the standing part encrypted area---between 1/16 encrypted area, 1/16 the density that adds is easy to realize, for example can make the address of all A (7:4)=" 0000 " all encrypt, also can make the address of A (7:4)=A (8:5) all encrypt etc.Give the user of system other all space openings again, select between encrypted area by register definitions table as shown in Figure 5 and to have the data of which address feature in the interval encrypted by software.
Being one as shown in Figure 5 is used between encrypted area and the register definitions table selected of encryption address.This definition list is an interface that provides for the user of system, and system user can select a suitable encipherment scheme according to the needs of software program, and principle of the present invention is really applied in the protection to software systems.
This definition list has defined four independently registers (these four registers can be regarded a big register as), system user can use them to select between four separate encrypted areas at most, can not be overlapping between these four encrypted areas, and all can not exceed W0 district in the accompanying drawing 4, promptly select encrypted area.
Hardware Design person finishes the hardware designs of decoder and register according to above these requirements, it is noted that register only writes, and its numerical value can not be read.
It should be noted that equally apparatus of the present invention and method can not be provided with register, promptly the address of concrete enciphered data is determined by hardware fully; though software uses can be not too convenient; and secret effect is a bit weaker, but still makes progress than prior art, therefore belongs to protection scope of the present invention.
So far, the design work of hardware of the present invention is finished, and its operation principle can be with reference to top explanation.The following describes apparatus of the present invention and method and how to use this system, both protected the program safety of oneself, can obtain a relatively satisfied operational efficiency again.
At first, system user sets the key (length is determined that by hardware concrete numerical value is determined by user oneself) of AES encryption and decryption according to the needs of hardware, this key is write also note properly management in the chip.Because the AES data ciphering method is the block encryption algorithm of symmetry, so same key is used in encryption and decryption, this key can be 128, or 192 and 256, the key figure place is determined in advance by hardware.
Key writes the method for chip, can be OTP (write-once memory cell), or alternate manner such as FLASH (concrete wiring method is determined by hardware), but must guarantee this key: (a) outage can continue to preserve and can not lose, (b) can not be known, even cpu system can not be read.
For the difficulty that the increase program is decrypted, in general, one section code of program start-up portion all need be encrypted, the program code seen of code breaker is well as if a tangled skein of jute that can not find head like this.In the full code of encrypting of this section, finish setting to register in the ciphering unit, this register is a write-only register, numerical value can not be read, and will disappear immediately after the outage.
Be the register definitions table that Hardware Design person provides as shown in Figure 5, write the encipherment scheme that personnel are fit to for procedure Selection for software program, with use safety, it is convenient that also taking into account efficient simultaneously is principle.
Be the data encryption address section distribution diagram of example hypothesis of the present invention as shown in Figure 4, article one instruction was placed on FFFFFFF0h after wherein cpu system started, so FFFF0000h-FFFFFFFFh is fixed as the full encryption address of data interval; Simultaneously FF000000h-FFFEFFFFh is fixed as ten sixth encrypted areas, that is to say in this interval, per 16 data grouping will have one encrypted; Other address section is software optional encryption interval, and software design personnel can be by to the encipherment scheme of selecting own needs that is provided with as four registers of R1-R4 of Fig. 4 definition.Apparatus of the present invention and method can also can be encrypted the part address data encryption of protection with all address dates as required, and its scope comprises from 0-100% and containing into entirely.
Supposing to have a software program code total length is 38385KB (the primary data table that comprises definition), and the exclusive data space of need distributing is 10000KB, with the outer miscellaneous equipment data shared space of sheet not at the row of consideration.
At first program is begun initialized part and be put into FFFF0000h-FFFFFFFFh between fixing full encrypted area, wherein article one instruction is placed on the FFFFFFF0h place, supposes that the code of a total 5KB has been placed between this fixing full encrypted area.
The 3000KB normal codes is arranged subsequently, need 1/16 to encrypt, this part can be placed on the fixed-encryption district of FF000000h-FFFEFFFFh, also can open between an encrypted area at optional encrypted area, suppose that here this part code has been placed in the FF000000h-FFFEFFFFh fixed-encryption district with a register.
The key code that 380KB is arranged subsequently needs to encrypt entirely, because the fixing full encrypted area space of FFFF0000h-FFFFFFFFh is limited, need select encrypted area (the W0 district of Fig. 4) to open an interval.According to register definitions table among Fig. 4, can make R1=" 0,010 0,000 0,011 0,000 0,111 0,000 00000001 ", the initial address of wherein encrypting the space is 20300000H, encrypt the space size and be 512KB (must greater than 380KB), adding density encrypts for " 0000 " is promptly complete, this register of R1 (0)=1 expression is activated, and encrypts the space and effectively opens.
All codes subsequently are unimportant code, can not encrypt, so can be placed on it the place of arbitrary not chosen encryption---between the free zone, suppose initial address 30000000H.As W0 district in the accompanying drawing 4, the not selected interval of four registers of R1-R4 all is between the free zone.
See the data space that program needs again, suppose that this 10000KB all need 2/16 adds density, can make R2=" 0,110 0,000 0,000 0,000 1,100 0,010 0,000 0001 " so, the initial address of wherein encrypting the space is 60000000H, encrypt the space size and be 16MB (must greater than 10000KB), add density and be " 0010 " promptly 2/16, this register of R2 (0)=1 expression is activated, and effectively open in the encryption space.
After above encipherment scheme and address assignment were determined, the source code (clear data) with software program was encrypted to the ciphertext code again.This step operation is to design a tool software (data converter), the cryptographic operation that analog chip will carry out, that is to say, the code that ciphertext code that obtains with this software and cpu system are write external memory by top encryption hardware should be identical, comprise where all encrypting, where do not encrypt, where partly encrypt etc.Could guarantee cpu system like this when the external memory program code read is carried out, well as if oneself write the same that the outside goes, what can guarantee just just that cpu system obtains forever is initial data.
At last the ciphertext code that obtains is write in the outer memory of sheet with corresponding electronic device (for example programmer etc.).
Use above-mentioned program encryption scheme, key code is encrypted entirely, one group of per 16 group encryption of normal codes, guaranteed the safety of software, attempt the plagiarist can only take some bitty codes and utterly useless, simultaneously since most of code and data space to add density all lower, make calling program when real the execution, most of codes and data can directly pass in and out CPU core (going over from the ciphering unit bypass), the speed of service of calling program is compared with whole encryptions be significantly increased.
Therefore, apparatus of the present invention and method are applicable to the security fence of CPU exclusive data, and it can't reduce much the speed of service of CPU, but fail safe improves greatly.
Should be understood that above-mentioned description at specific embodiments of the invention is comparatively concrete and detailed, can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (7)
1, a kind of encryption device of CPU exclusive data, it is arranged in the chip that contains CPU, it is characterized in that, comprising: a ciphering unit that is provided with between cpu system and external data transmission is used for the read/write data of described cpu system is carried out separating/encrypting of partial data according to physical address; And an outer memory controller connects described cpu system and described ciphering unit simultaneously, be used for separating/enciphered data is through described ciphering unit with waiting, and with clear data or do not need enciphered data directly to transmit with described cpu system.
2, device according to claim 1 is characterized in that, described ciphering unit also comprises a register, is used for configuration and need separates/the enciphered data physical address; One decoder is used for the physical address that the numerical value and the cpu system of register are sent lumped together and deciphers, and judges whether the data of this address correspondence need to separate/encrypt; The grouped data encryption equipment of one band bypass after being used for when carrying out transfer of data with described cpu system corresponding data being separated/encrypting according to the configuration of described register, transmits with described outer memory controller again; One key is stored in the encryption of separating that is used for described grouped data encryption equipment in the chip that contains CPU.
3. according to claim 1 or 2 described devices, it is characterized in that described cryptographic algorithm is symmetrical grouped data encryption method.
4, device according to claim 3, it is characterized in that described symmetrical grouped data encryption method comprises DES, 3DES, AES, Lucifer, LOKI, IDEA, GOST, CAST, RC5, Blowfish, Madryga, FEAL, REDOC, Khufu, MMB, SAFER, 3-WAY, Crab and their modification, combination and cascade.
5, a kind of encryption method of CPU exclusive data, it may further comprise the steps:
A, to the outer read/write data of cpu system and sheet,, separate/encryption according to its physical address by a ciphering unit according to predetermined configurations selection portion divided data, outside described cpu system and one, transmit between the memory controller;
B, to need not separate/data of encryption described cpu system and described outside directly transmission between the memory controller;
C, described outer memory controller together and between outside the sheet transmit all encryptions and clear data.
6, method according to claim 5 is characterized in that, described ciphering unit adopts symmetrical grouped data cryptographic algorithm.
7, method according to claim 5 is characterized in that, described predetermined configurations for separating/physical address of enciphered data, and be stored in the register; Simultaneously in described ciphering unit, also be provided with a decoder, be used for the physical address that the numerical value and the cpu system of described register are sent lumped together and decipher, that the data of judging this address correspondence need encryption and decryption or do not need.
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| CN200710073515A CN101051892B (en) | 2007-03-14 | 2007-03-14 | Enciphering device and method for CPU special data |
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| WO2000062475A1 (en) * | 1999-04-13 | 2000-10-19 | Sony Corporation | Information processing system, information processing method, and information processing device |
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