CN101051844A - Differential pulse code regulation coding method and its device of no built-in decoder - Google Patents

Abstract

Using deviation data generated by the encoder to carry out reduction, the method knows the reduction data decoded by the decoding device of difference impulse code modulation. Using share between adder and buffer, the invention reduces number of modules so as to reach purpose of reducing cost.

Description

The differential pulse code regulation coding method of no built-in decoder and device thereof

Technical field

The present invention relates to a kind of signal processing system, particularly relevant for a kind of differential pulse code regulation coding method and device thereof of no built-in decoder.

Background technology

Because the rapid technological improvement of Digital Signal Processing when handling the message data, usually can use the technology of compression to reduce stored figure place.The most normal compress technique of using is DPCM (DifferentialPulse Code Modulation, differential pulse code regulation) at present, and in simple terms, this kind method is not directly to store the PCM data, but only stores the difference of present sample and previous sample.Because message data variation amount is little, the otherness of the sample in front and back is also little usually, usually can be little a lot of than directly storing the PCM data so store the data volume of difference data.

Differential pulse code regulation is the compression of kind of distortion, represents difference data, the source of distortion that Here it is because only use limited position.In addition, if directly taking the present sample and the difference data of previous sample encodes, then can be asynchronous with the differential pulse code regulation code translator, and the result of the wrong transmission of meeting, therefore, in the differential pulse code regulation code device, can simulate the restoring data that the differential pulse code regulation code translator is deciphered out by a built-in decoder, the restoring data that present sample and this emulation differential pulse code regulation code translator are deciphered out subtracts each other again, the error information that draws remakes compression, thus, just only have, and do not have other distortion because the spacing distortion that produces is arranged.As shown in Figure 1, it is the calcspar of the sound signal processing system in the known technology.Sound signal processing system 10 comprises: a differential pulse code regulation code device 100 and a differential pulse code regulation code translator 200.Differential pulse code regulation code device 100 comprises further: a first adder 110, an encoder 120, one first decoder 130 and one first delay cell 140.And differential pulse code regulation code translator 200 comprises further: one second decoder 210, second adder 220 and one second delay cell 230.

When numerical data p (n) inputs to first adder 110 in the differential pulse code regulation code device 100, the delay prediction data pred (n-1) that first adder 110 can be imported numerical data p (n) and first delay cell 140 does the action of subtracting each other, and produces a difference data dif (n).Encoder 120 is according to difference data dif (n), and coding produces a coded data code (n).First decoder, 130 acquisition coded data code (n), decoding produces a prediction data pred (n).First delay cell 140 postpones to produce a delay prediction data pred (n-1) according to prediction data pred (n), and first adder 110 is again according to delay prediction data pred (n-1), and numerical data p (n).In addition, second decoder 210 in the differential pulse code regulation code translator 200 is with coded data code (n), separate and be encoded to difference data dif (n), second adder 220 is made comparisons difference data dif (n) with postponing restoring data ret (n-1), produce restoring data ret (n).

Yet, in differential pulse code regulation code device 100, in order to simulate the restoring data ret (n) that differential pulse code regulation code translator 200 is deciphered out, added one first decoder 130 in differential pulse code regulation code device 100, not only cause the problem of many delays, be that code length is big more, the amount of delay is just many more, but also has improved expending of production cost.

Summary of the invention

For addressing the above problem, the objective of the invention is to propose the differential pulse code regulation coding method and the device thereof of a no built-in decoder, reduce with the error information that encoder was produced and to learn the restoring data that the differential pulse code regulation code translator is deciphered out, and utilize sharing of adder and buffer, to reduce assembly, reach the purpose that reduces cost.

Differential pulse code regulation coding method and device thereof according to no built-in decoder of the present invention is characterized in that device comprises: first adder, encoder, fallout predictor and delay cell.

As numerical data p (n) when inputing to first adder, first adder is according to received numerical data p (n), after relatively, produce corresponding difference data dif (n), and input in the encoder, encoder can be according to received difference data dif (n), coding produces a coded data code (n) and error information err (n), and coded data code (n) exported to outside the differential pulse code regulation code device, doing follow-up processing further, and error information err (n) is sent to fallout predictor.When fallout predictor receives the error information err (n) that encoder is imported, and in conjunction with numerical data p (n), can be with error information err (n) and the addition of numerical data p (n) process, produce a prediction data pred (n), and be sent to delay cell, delay cell can be with received prediction data pred (n), postpone to produce delay prediction data pred (n-1), and delay prediction data pred (n-1) is sent to first adder, so that being provided, first adder produces the usefulness of above-mentioned difference data dif (n).

Description of drawings

Fig. 1 is the point-to-point setting schematic diagram of the known technology network equipment;

Fig. 2 is the calcspar of the differential pulse code regulation code device of content of the present invention;

Fig. 3 is the flow chart of the differential pulse code regulation coding method of content of the present invention;

Fig. 4 is the flow chart of the encoder encodes of content of the present invention.

Wherein, Reference numeral:

Known technology:

10 sound signal processing systems

100 differential pulse code regulation code devices, 110 first adders

120 encoders, 130 first decoders

140 first delay cells

200 differential pulse code regulation code translators, 210 second decoders

220 second adders, 230 second delay cells

The present invention:

300 differential pulse code regulation code devices, 310 first adders

320 encoders, 330 fallout predictors

340 delay cells

Embodiment

Fig. 2 is the calcspar of the differential pulse code regulation code device of content of the present invention.As shown in the figure, it is the calcspar of the differential pulse code regulation code device of content of the present invention.Differential pulse code regulation code device 300 comprises: a first adder 310, an encoder 320, a fallout predictor 330 and a delay cell 340.

First adder 310, the delay prediction data pred (n-1) that imports in order to numerical data p (n) that differential pulse code regulation code device 300 is received and delay cell are done the action of subtracting each other, and produce difference data dif (n).Wherein this numerical data p (n) is the pulse-code modulation data after process sampling and the quantification.

Encoder 320, it is linked to first adder 310, and difference data dif (n) coding in order to first adder 310 is imported produces coded data code (n) and error information err (n), so encoder 320 can a differential pulse code regulation encoder.Encoder 320 further comprises: at least one second adder (not shown), at least one multiplier (not shown) and a plurality of buffer (not shown).

Fallout predictor 330, it is linked to encoder 320 and delay cell 340, the numerical data p (n) that is imported in order to error information err (n) that encoder 320 is imported and differential pulse code regulation code device 300, be reduced into prediction data pred (n), because the action that fallout predictor 330 is done, for when difference data dif (n) greater than zero the time, numerical data p (n) and error information err (n) done the action of subtracting each other, or when difference data dif (n) be less than zero the time, numerical data p (n) and error information err (n) are done the action of addition, so fallout predictor 330 can be shared with the second adder in the encoder 320, to reduce the use of assembly.

Delay cell 340, it is linked between first adder 310 and the fallout predictor 330, in order to prediction data pred (n) is postponed to produce delay prediction data pred (n-1).

Fig. 3 is the flow chart of the differential pulse code regulation coding method of content of the present invention.As shown in the figure, may further comprise the steps:

Step S310, when numerical data p (n) inputed to first adder 310 in the differential pulse code regulation code device 300, numerical data p (n) was for through sampling and the pulse-code modulation data after quantizing.

Step S320, first adder 310 can be with received numerical data p (n), and the delay prediction data pred (n-1) that is imported by delay cell 340, and the action that work subtracts each other produces a difference data dif (n), and inputs in the encoder 320.

Step S330, encoder 320 can be according to received difference data dif (n), and coding produces a coded data code (n) and error information err (n).

Step S340, when fallout predictor 330 receives the error information err (n) that encoder 320 is imported, and in conjunction with numerical data p (n), can be with error information err (n) and numerical data p (n) through subtracting each other, produce a prediction data pred (n), and be sent to delay cell 340.

Step S350, delay cell 340 can postpone to produce delay prediction data pred (n-1) with received prediction data pred (n), produces the usefulness of above-mentioned difference data dif (n) so that first adder 310 to be provided.

Step S360, encoder 320 can export coded data code (n) outside the differential pulse code regulation code device 300 to, and to do follow-up processing further, for example decoding is reduced into restoring data etc.

In order more clearly to set forth content of the present invention, so receive the difference data dif (n) that is imported by first adder 310 at encoder 320, the process through coding generation one a coded data code (n) and an error information err (n) provides an embodiment again.

Fig. 4 is the flow chart of the encoder encodes of content of the present invention, as shown in the figure, has the bits of coded of 4bit in the present embodiment hypothesis encoder 320, and coded data is respectively B3, B2, B1 and B0, B3 is a sign bit, represents the positive negative value of difference data, and coded data B2 to B0 is a magnitude bits.

Step S410, the numerical data p (n) that outside first adder 310 receives by differential pulse code regulation code device 300, is imported, when reaching the delay prediction data pred (n-1) that is imported by delay cell 340, first adder 310 can be made numerical data p (n) and delay prediction data pred (n-1) action of subtracting each other, produce a difference data dif (n), and be sent to the action of encoding in the encoder 320.

Step S420, at first, encoder 320 can judge earlier that difference data dif (n) that first adder 310 imported whether less than zero, is one or zero with decision coded data B3.

Step S421 judges that when encoder 320 difference data dif (n) more than or equal to zero the time, equal zero coded data B3, and difference data remains unchanged, so that a judgment value d1 (n) to be provided.

Step S422 is when encoder 320 judges that difference data dif (n) less than zero the time, make coded data B3 equal one, and get the absolute value of difference data dif (n), so that a judgment value d1 (n) to be provided.

Step S430, whether then, encoder 320 will be judged the judgment value d1 (n) more than or equal to zero difference data dif (n), or judge the judgment value d1 (n) of minus difference data dif (n), greater than a minimum quantization unit value SS.

Step S431 when encoder 320 is judged judgment value d1 (n) smaller or equal to minimum quantization unit value SS, equals zero coded data B2, and judgment value d1 (n) remains unchanged, and so that a comparison value to be provided, is the first comparison value d2 (n).

Step S432 when encoder 320 is judged judgment value d1 (n) greater than minimum quantization unit value SS, makes coded data B2 equal one, and judgment value d1 (n) is deducted a minimum quantization unit value SS, so that one first comparison value d2 (n) to be provided.

Step S440, encoder 320 further judge the first comparison value d2 (n) greater than minimum quantization unit value SS, or judge the first comparison value d2 (n) smaller or equal to minimum quantization unit value SS, whether greater than a minimum quantization unit value SS divided by two value.

Step S441, judging the first comparison value d2 (n) when encoder 320 during divided by two value, coded data B1 is equalled zero, and the first comparison value d2 (n) remains unchanged smaller or equal to minimum quantization unit value SS, so that next comparison value to be provided, be one second comparison value d3 (n).

Step S442, when encoder 320 judges that the first comparison value d2 (n) is greater than minimum quantization unit value SS during divided by two value, make coded data B1 equal one, and the first comparison value d2 (n) is deducted a minimum quantization unit value SS divided by two value, so that one second comparison value d3 (n) to be provided.

Step S450, encoder 320 will be judged the second comparison value d3 (n) divided by two value greater than minimum quantization unit value SS, or judge the second comparison value d3 (n) divided by two value smaller or equal to minimum quantization unit value SS, whether greater than a minimum quantization unit value SS divided by four value.

Step S451, judging the second comparison value d3 (n) when encoder 320 during divided by four value, coded data B0 is equalled zero, and the second comparison value d3 (n) remains unchanged smaller or equal to minimum quantization unit value SS, so that next comparison value to be provided again, be one the 3rd comparison value d4 (n).

Step S452, when encoder 320 judges that the second comparison value d3 (n) is greater than minimum quantization unit value SS during divided by four value, make coded data B0 equal one, and the second comparison value d3 (n) is deducted a minimum quantization unit value SS divided by four value, so that one the 3rd comparison value d4 (n) to be provided, the 3rd comparison value d4 (n) is error information err (n).

Step S460, encoder 320 from step S421 to step S452, captured judgment value d1 (n), the first comparison value d2 (n), the second comparison value d3 (n), the 3rd comparison value d4 (n), minimum quantization unit value SS, minimum quantization unit value SS divided by two value and minimum quantization unit value SS divided by four value, according to digital coding B3 to B0, by at least one second adder and at least one multiplier in the encoder 320, come computing to produce a coded data code (n), as.

Wherein, encoder 320 computing judgment value d1 (n), the first comparison value d2 (n), the second comparison value d3 (n), the 3rd comparison value d4 (n), minimum quantization unit value SS, minimum quantization unit value SS during divided by four value, need meet following formula divided by two value and minimum quantization unit value SS:

$\mathrm{code}\left(n\right)-{(-1)}^{B_N}\&times;(B_{N-1}\&times;\mathrm{SS}+B_{N-2}\&times;\frac{\mathrm{<figure-callout\; id="2"\; label="SS"\; filenames="A20061006670600141.png"\; state="\{\{state\}\}">SS</figure-callout>}}{2}+K+{\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="A20061006670600111.png,A20061006670600121.png"\; state="\{\{state\}\}">B</figure-callout>}}_1\&times;\frac{\mathrm{SS}}{2^{N-2}}+{\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20061006670600141.png"\; state="\{\{state\}\}">B</figure-callout>}}_0\&times;\frac{\mathrm{SS}}{2^{N-1}})$

, N is the figure place of coded data.

Step S470, encoder 320 exports the 3rd comparison value d4 (n) to fallout predictor 330,, reduces and produces a prediction data pred (n) according to the received numerical data p (n) of fallout predictor 330 with further.

Step S471, in addition, encoder 320 exports coded data code (n) outside the differential pulse code regulation code device 300 to, and to make subsequent treatment further, for example decoding is reduced into recovering signal etc.

In encoder 320, difference data dif (n) is encoded, the data that produced in the process, as judgment value d1 (n), the first comparison value d2 (n), minimum quantization unit value SS etc., to be temporarily stored in encoder 320 in a plurality of buffers, required when providing encoder 320 to do the coding action.In addition, encoder 320 computing judgment value d1 (n), the first comparison value d2 (n), the second comparison value d3 (n), the 4th comparison value d4 (n) minimum quantization unit value SS

Advantage provided by the present invention is, by the error information that coding is produced, and the restoring data of the anti-sign indicating number end of deciphering.

Another advantage provided by the present invention is, need not add decoder again at coding side and simulate the restoring data that the differential pulse code regulation code translator is deciphered out, reduces the use of assembly.

An advantage more provided by the present invention is, by sharing of adder and buffer, reduces the use of assembly.

Another advantage provided by the present invention is, reduces the use of assembly, and what can reduce cost expends.

Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims (10)

1. a differential pulse code regulation code device is characterized in that, comprises:

One first adder in order to receiving a numerical data, and produces a difference data;

One encoder, it is linked to this first adder, this error information of importing in order to this first adder of encoding, and produce a coded data and an error information;

One fallout predictor, it is linked to this encoder, in order to according to this numerical data and this error information, produces a prediction data; And

One delay cell, it is linked to this fallout predictor and this first adder, in order to produce delay prediction data according to this prediction data;

Wherein, after this first adder utilization is done this numerical data and this delay prediction data to subtract each other, to produce this difference data.

2. differential pulse code regulation code device according to claim 1 is characterized in that, this encoder comprises at least one second adder, at least one multiplier and a plurality of buffer.

3. differential pulse code regulation code device according to claim 2 is characterized in that, this fallout predictor and this second adder are shared.

4. differential pulse code regulation coding method is characterized in that step comprises:

Import numerical data to a first adder;

This first adder subtracts each other this numerical data and delay prediction data, gives an encoder to produce a difference data;

This difference data of encoding produces a coded data and an error information, and wherein, this error information is sent to a fallout predictor further;

This fallout predictor is reduced into a prediction data according to this numerical data and this error information, and is sent to a delay cell; And

This delay cell postpones to produce delay prediction data according to this prediction data, does the action of subtracting each other so that this first adder to be provided, and produces this difference data.

5. differential pulse code regulation coding method according to claim 4 is characterized in that, this numerical data is pulse-code modulation data.

6. differential pulse code regulation coding method according to claim 4 is characterized in that, this fallout predictor is in order to subtracting each other this error information and this numerical data, producing this prediction data, and when this prediction data when zero, this predict data is got negative.

7. differential pulse code regulation coding method according to claim 4 is characterized in that, this encoder is this difference data coding, and the step that produces this error information and have this coded data of a sign bit and a plurality of magnitude bits further comprises:

Judge that this difference data that this first adder imports whether less than zero, is one or zero to determine this sign bit, and a judgment value is provided;

Judge that this judgment value is whether respectively greater than the value of each minimum quantization unit value divided by two power, to determine that a magnitude bits in those magnitude bits is one or zero, and a comparison value is provided, wherein two power value is decided by the quantity of this sign bit and those magnitude bits;

According to judging that this comparison value is whether greater than the value of this minimum quantization unit value divided by two power, one of to determine in those magnitude bits that a magnitude bits is one or zero, and provide next comparison value, when those magnitude bits all were judged to be one or zero, the comparison value that generates at last was this error information;

According to this sign bit and those magnitude bits, capture the value of this each this minimum quantization unit value, so that this coded data to be provided divided by two power; And

, determine whether this coded data is negative, and determine this fallout predictor should deduct or add this error information whether greater than zero according to this judgment value.

8. differential pulse code regulation coding method according to claim 7 is characterized in that, if this judgment value is greater than this minimum quantization unit value, then this judgment value is deducted the value of this minimum quantization unit value divided by two power, so that this comparison value to be provided; If this judgment value is smaller or equal to the value of this minimum quantization unit value divided by two power, then this judgment value remains unchanged, so that next comparison value to be provided.

9. differential pulse code regulation coding method according to claim 7 is characterized in that, judges whether this difference data that this first adder imports whether less than zero, needs to get its absolute value to determine this difference data, so that this judgment value to be provided.

10. differential pulse code regulation coding method according to claim 7 is characterized in that, captures the value of this each this minimum quantization unit value divided by two power, so that this coded data to be provided, need meet a coding formula, and this coding formula is as follows:

$\mathrm{code}\left(n\right)={(-1)}^{B_N}\&times;(B_{N-1}\&times;\mathrm{SS}+B_{N-2}\&times;\frac{\mathrm{SS}}{2}+K+B_1\&times;\frac{\mathrm{SS}}{2^{N-2}}+B_0\&times;\frac{\mathrm{SS}}{2^{N-1}})$

, wherein N is this sign bit and those magnitude bits additions total quantity afterwards.

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