CN101051827A - Scanning trigger circuit with lenghtening maintenance time margin - Google Patents
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Abstract
The scanning flipflop circuit includes at least sensor amplifier and latch. The latch possesses a generation circuit. Being in use for receiving first signal and second signal output from the sensor amplifier, the generation circuit generates the output signal. Receiving the output signal and the second signal, the storage circuit is in use for maintaining the output signal of the generation circuit when both of the first signal and the second signal do not run.
Description
Technical field
The present invention relates to a kind of trigger (Flip-Flop) circuit, particularly a kind of scan flip-flop circuit with lenghtening maintenance time margin (Hold Time Margin).
Background technology
Please refer to Fig. 1, it is depicted as known D type master-slave mode trigger (Master-Slave Flip-Flop) circuit diagram.This D type master-slave mode trigger comprise main latch (Master Latch) 10 with from latch (Slave Latch) 20.Main latch 10 comprises n transistor npn npn (Mn1, Mn2, Mn3), P transistor npn npn (Mp1, Mp2, Mp3), NAND gate (Not Gate) 12.Wherein, n transistor npn npn (Mn1) is connected to become transmission gate (Transmission Gate) 14 with P transistor npn npn (Mp1), the input of transmission gate 14 is the input (D) of D type master-slave mode trigger, and the frequency signal (CLK, CLKb) of frequency signal and complementary (Complement) is connected to the grid of n transistor npn npn (Mn1) and P transistor npn npn (Mp1) respectively.Moreover, P transistor npn npn (Mp3) source electrode is connected to voltage source (Vdd), P transistor npn npn (Mp3) drain electrode is connected to P transistor npn npn (Mp2) source electrode, P transistor npn npn (Mp2) drain electrode is connected to n transistor npn npn (Mn2) drain electrode, n transistor npn npn (Mn2) source electrode is connected to n transistor npn npn (Mn3) drain electrode, n transistor npn npn (Mn3) source electrode is connected to earth terminal (Gnd), and P transistor npn npn (Mp3) grid is connected to n transistor npn npn (Mn3) grid, and frequency signal and complementary frequency signal (CLK, CLKb) be connected to the grid of p transistor npn npn (Mp2) and n transistor npn npn (Mn2) respectively.And output NAND gate 12 inputs of transmission gate 14 are connected to P transistor npn npn (Mp2) drain electrode, and not gate 12 outputs are connected to P transistor npn npn (Mp3) grid and are the output of main latch 10.
Comprise n transistor npn npn (Mn4, Mn5, Mn6), P transistor npn npn (Mp4, Mp5, Mp6), NAND gate 22 from latch 20.Wherein, n transistor npn npn (Mn4) is connected to become transmission gate 24 with P transistor npn npn (Mp4), the input of transmission gate 24 is connected to the output of main latch 10, and the frequency signal (CLK, CLKb) of frequency signal and complementation is connected to the grid of p transistor npn npn (Mp4) and n transistor npn npn (Mn4) respectively.Moreover, p transistor npn npn (Mp6) source electrode is connected to voltage source (Vdd), P transistor npn npn (Mp6) drain electrode is connected to P transistor npn npn (Mp5) source electrode, P transistor npn npn (Mp5) drain electrode is connected to n transistor npn npn (Mn5) drain electrode, n transistor npn npn (Mn5) source electrode is connected to n transistor npn npn (Mn6) drain electrode, n transistor npn npn (Mn6) source electrode is connected to earth terminal (Gnd), and P transistor npn npn (Mp6) grid is connected to n transistor npn npn (Mn6) grid, and frequency signal and complementary frequency signal (CLK, CLKb) be connected to the grid of n transistor npn npn (Mn5) and p transistor npn npn (Mp5) respectively.And output NAND gate 22 inputs of transmission gate 24 are connected to P transistor npn npn (Mp5) drain electrode, and not gate 22 outputs are connected to P transistor npn npn (Mp6) grid and are the output (Q) of D type master-slave mode trigger.
By D type master-slave flip-flop shown in Figure 1 as can be known, main latch 10 moves and does not move from latch 20 when frequency signal is high level.Otherwise when frequency signal was low level, main latch 10 did not move and moves from latch 20.That is to say, when the input of D type master-slave mode trigger is that high level and frequency signal are when being high level, main latch 10 operation and output low levels, when frequency signal is converted to low level through 1/2 all after dates, because the p transistor npn npn (Mp2, Mp3) in the main latch 10 is opened, make main latch 10 outputs locks (Latch) in low level.Simultaneously, because from latch 20 operations, make from latch 20 output high level, when frequency signal is converted to high level through 1/2 all after dates once more, n transistor npn npn from latch 20 (Mn5, Mp6) is opened, make to be locked in high level the high level of D type master-slave mode trigger output just from latch 20 outputs.In like manner, when the input of D type master-slave mode trigger is low level, must be through after 1/2 frequency period, D type master-slave mode trigger is exportable low level.
The D type master-slave flip-flop of Fig. 1 has the advantage of small size and firm (Robust), but main defective promptly is can't high speed operation.
Please refer to Fig. 2, it is depicted as known another D type master-slave mode flip-flop circuit figure.This D type master-slave mode trigger comprise main latch (Master Latch) 30 with from latch (Slave Latch) 40.Main latch 30 is called sensor amplifier (Sense Amplifier) again, is called SR latch (SR Latch) again from latch 40.Main latch 30 comprises n transistor npn npn (Mn7, Mn8, Mn9, Mn10, Mn11, Mn12), p transistor npn npn (MP7, Mp8, Mp9, Mp10).Wherein, p transistor npn npn (Mp7) grid is connected to frequency signal (CLK), and p transistor npn npn (Mp7) and p transistor npn npn (Mp8) source electrode are connected to voltage source (Vdd) and drain electrode interconnects and become the setting end (Sb) of main latch 30; N transistor npn npn (Mn7) grid is connected to n transistor npn npn (Mn8) drain electrode and p transistor npn npn (Mp8) grid, and n transistor npn npn (Mn7) drain electrode is connected to p transistor npn npn (Mp8) drain electrode; N transistor npn npn (Mn9) drain electrode is connected to n transistor npn npn (Mn7) source electrode, and n transistor npn npn (Mn9) grid is the input (D) of D type master-slave mode trigger; N transistor npn npn (Mn11) drain electrode is connected to n transistor npn npn (Mn9) source electrode, and n transistor npn npn (Mn11) grid is connected to frequency signal (CLK), and n transistor npn npn (Mn11) source electrode is connected to earth terminal (Gnd).And p transistor npn npn (Mp10) grid is connected to frequency signal (CLK), and p transistor npn npn (Mp9) and p transistor npn npn (Mp10) source electrode are connected to voltage source (Vdd) and drain electrode interconnects and become the replacement end (Rb) of main latch 30; N transistor npn npn (Mn8) grid is connected to n transistor npn npn (Mn7) drain electrode and p transistor npn npn (Mp9) grid, and n transistor npn npn (Mn8) drain electrode is connected to p transistor npn npn (Mp9) drain electrode; N transistor npn npn (Mn10) drain electrode is connected to n transistor npn npn (Mn8) source electrode, and n transistor npn npn (Mn10) grid is the complementary input end (Db) of D type master-slave mode trigger, and n transistor npn npn (Mn10) source electrode is connected to n transistor npn npn (Mn11) drain electrode; N transistor npn npn (Mn12) grid is connected to voltage source (Vdd), and n transistor npn npn (Mn12) source electrode and drain electrode are connected to the drain electrode of n transistor npn npn (Mn9) and n transistor npn npn (Mn10) respectively.
The NAND gate (Nand Gate) 42,44 that comprises a pair of mutual connection (Cross-Coupled) from latch 40.The input of NAND gate 42 is connected to the setting end (Sb) of main latch 30, and the input of NAND gate 44 is connected to the replacement end (Rb) of main latch 30.Be the Q output and the Qb output of D type master-slave mode trigger from the output of the NAND gate 42,44 of latch 40.When setting end (Sb) be high level and the end (Rb) of resetting during for low level, and Q end output low level and Qb end are exported high level; When setting end (Sb) be low level and the end (Rb) of resetting during for high level, and Q end output high level and Qb hold output low level; When setting end (Sb) was high level with the end (Rb) of resetting, Q held with Qb end output level and remains unchanged; Moreover, set end (Sb) and do not allow to be simultaneously low level with the end (Rb) of resetting.
When frequency signal (CLK) is input (D) input high level of high level and D type master-slave mode trigger, n transistor npn npn in the main latch 30 (Mn7, Mn9, Mn11, Mn12) is opened (On), n transistor npn npn (Mn8, Mn10) is closed (Off), p transistor npn npn (Mp9) is opened, p transistor npn npn (Mp7, Mp8, Mp10) is closed, so end (Rb) is exported high level for high level makes Q hold and Qb holds output low level for low level is reset to set end (Sb).Moreover, when frequency signal (CLK) is input (D) input low level of high level and D type master-slave mode trigger, n transistor npn npn in the main latch 30 (Mn8, Mn10, Mn11, Mn12) is opened, n transistor npn npn (Mn7, Mn9) is closed, p transistor npn npn (Mp8) is opened, therefore p transistor npn npn (Mp7, Mp9, Mp10) is closed, and sets end (Sb) and makes Q end output low level and Qb end export high level for the high level end (Rb) of resetting for low level.Moreover, when frequency signal (CLK) is low level, no matter the input (D) of D type master-slave mode trigger why, p transistor npn npn in the main latch 30 (Mp7, Mp10) is opened, and therefore sets end (Sb) and makes Q end and Qb hold output level to remain unchanged for the high level end (Rb) of resetting for high level.
Because the D type master-slave flip-flop of Fig. 2 can be held the generation output signal at frequency signal (CLK) at Q and Qb during for high level.Yet owing to the NAND gate 42,44 that comprises mutual connection from latch 40, so the output signal of Q and the generation of Qb end can postpone lock delay (the Nand Gate Delay) time of 2 NAND gate.Therefore, the raising of the D type master-slave flip-flop service speed of Fig. 2 is limited.
Please refer to Fig. 3, it is depicted as U.S. Pat 6232810 disclosed D type master-slave mode flip-flop circuit figure.The topmost purpose of this D type master-slave mode trigger be to propose from latch 60 in order to replace Fig. 2 from latch 40, make the speed of D type master-slave mode trigger to improve.This D type master-slave mode trigger comprise main latch 50 with from latch 60.And main latch 50 is called sensor amplifier, is called the SR latch again from latch 60.
In general, because main latch 50 has multiple different implementation, for example U.S. Pat 6232810 Fig. 1 and main latch shown in Figure 3, so do not emphasize the circuit connecting relation of main latch 50.And the common trait that main latch 50 had is when promptly being frequency signal (CLK) for input (D) input high level of high level and D type master-slave mode trigger, makes that setting end (Sb) is high level for the low level end (Rb) of resetting.Moreover when main latch 50 was input (D) input low level of high level and D type master-slave mode trigger at frequency signal (CLK), make setting end (Sb) was low level for the high level end (Rb) of resetting.Moreover when main latch 50 was low level at frequency signal (CLK), make setting end (Sb) was high level for the high level end (Rb) of resetting.
From latch 60, be called the SR latch again, comprise not gate (Not Gate) 62,64, storage circuit (StorageCircuit) 65, n transistor npn npn (Mn13, Mn14), p transistor npn npn (Mp11, Mp12).Wherein, p transistor npn npn (Mp11) grid is connected to the setting end (Sb) of main latch 50, and p transistor npn npn (Mp11) source electrode is connected to voltage source (Vdd); Not gate 62 inputs are connected to the replacement end (Rb) of main latch 50; N transistor npn npn (Mn13) grid is connected to not gate 62 outputs, and n transistor npn npn (Mn13) drain electrode is connected to p transistor npn npn (Mp11) and drains and become the Q end, and n transistor npn npn (Mn13) source electrode is connected to earth terminal (Gnd).P transistor npn npn (Mp12) grid is connected to the replacement end (Rb) of main latch 50, and p transistor npn npn (Mp12) source electrode is connected to voltage source (Vdd); Not gate 64 inputs are connected to the setting end (Sb) of main latch 50; N transistor npn npn (Mn14) grid is connected to not gate 64 outputs, and n transistor npn npn (Mn14) drain electrode is connected to p transistor npn npn (Mp12) and drains and become the Qb end, and n transistor npn npn (Mn14) source electrode is connected to earth terminal (Gnd).Moreover storage circuit 65 comprises not gate 66,68, and the Q end is connected to not gate 68 input NAND gate 66 outputs, and the Qb end is connected to not gate 68 output NAND gate 66 inputs.
Therefore, reset end (Rb) during for high level when the setting end (Sb) of main latch 50 for low level, Q holds with Qb can export high level and low level apace.Reset end (Rb) during for low level when the setting end (Sb) of main latch 50 for high level, and Q and Qb hold output low level and high-low level apace.Moreover when the setting end (Sb) of main latch 50 is reset end (Rb) during for high level for high level, storage circuit 65 can be kept the output level that Q and Qb hold.That is the D type master-slave mode trigger of Fig. 3 does not have the lock time of delay of NAND gate, so service speed can be faster than the D type master-slave mode trigger of Fig. 2.
Because the D type master-slave mode trigger of Fig. 3 has symmetrical circuit structure from latch 60, therefore, this type of D type master-slave mode trigger can be simultaneously at Q and the complementary signal of Qb end output.As everyone knows, a not gate need be realized by two transistors, so main latch 60 needs 12 transistors to realize altogether, can occupy bigger layout area.
In the field of IC circuit design, except the bang path of design general data, whether bang path that must the otherwise designed test data can normally move in order to the circuit of Test Design.That is to say, when the circuit of design during at test pattern, input must the acceptance test data in order to carrying out the test of circuit, and when operational mode, input must receive general data.In order to reach above-mentioned effect, at prime adding multiplexer (Multiplexer) the 70 formation scan flip-flop circuits (Scan Flip-Flop) of trigger input.Please refer to Fig. 4, it is depicted as scan flip-flop circuit.When the selecting side of multiplexer 70 (SEL) was low level, the expression scan flip-flop circuit was in operational mode, and the signal of data input pin this moment (Da) can be imported D flip-flop 80.Otherwise when the selecting side of multiplexer 70 (SEL) was high level, the expression scan flip-flop circuit was at test pattern, and the signal of test input this moment (DT) can be imported D flip-flop.
In general, when scan flip-flop circuit operated in test pattern, the test data speed of test input (DT) input was slower.Therefore, when D flip-flop 80 operation, the D type master-slave mode trigger of Fig. 3 for example, (Hold Time Margin) is too short for the margin of holding time in the time of can causing test pattern, causes scan flip-flop circuit normally to move.In general, a plurality of buffers (Buffer) of can connecting on the bang path of test data are in order to the prolongation margin of holding time, yet, increase buffer and also can cause the increase of number of transistors purpose to cause layout area to increase too much.
Therefore, the scan flip-flop circuit that how to improve the bigger problem of known D type master-slave mode trigger layout area and provide prolongation to hold time margin is main purpose of the present invention.
Summary of the invention
The objective of the invention is to propose a kind of scan flip-flop circuit, make that the circuit layout area of scan flip-flop circuit is less.
Therefore, the present invention proposes a kind of scan flip-flop circuit, comprise: multiplexer and trigger, this multiplexer has selecting side, first input end and second input, and this multiplexer can and then will be passed to the input of this trigger corresponding to the signal of this first input end or this second input according to the selection signal of this selecting side input by the output of this multiplexer; Wherein, this multiplexer comprises: data transmission circuit, this data transmission circuit comprises at least 2 p transistor npn npns and at least 2 the n transistor npn npns that are serially connected with voltage source and earth terminal in regular turn, and p transistor npn npn and n transistor npn npn tie point are the output of this data transmission circuit, the grid of a pair of p transistor npn npn and n transistor npn npn is connected to this first input end, and another grid to p transistor npn npn and n transistor npn npn receives this selection signal and this complementary selection signal respectively, when this selection signal was first level, the output of this data transmission circuit can transmit with respect to the signal of this first input end output to this multiplexer; And, the test transmission circuit, this test transmission circuit comprises at least 2 p transistor npn npns being serially connected with voltage source and earth terminal in regular turn and 2+N n transistor npn npn at least, and p transistor npn npn and n transistor npn npn tie point are the output of this test transmission circuit, this selection signal that the grid of a pair of n transistor npn npn and p transistor npn npn receives this selection signal and complementation respectively connects, when this selection signal is second level, the output of this test transmission circuit can transmit with respect to the signal of this second input output to this multiplexer, and N is more than or equal to 1.
The present invention also proposes a kind of master-slave mode trigger, comprise: sensor amplifier, this sensor amplifier can produce first signal and secondary signal according to input signal and frequency signal, wherein, when this input signal is that first level and this frequency signal are during for this first level, for this first signal moves first state that this secondary signal is not moved, when this input signal is that second level and this frequency signal are during for this first level, do not move second state of this second input signal operation for this first signal, when this frequency signal is this second level, the third state of all not moving for this first signal and this second input signal; And, latch, this latch has the generation circuit, and in order to receiving this first signal and this secondary signal and then to produce output signal, and storage circuit receives this output signal and this secondary signal in order to keep this output signal of this generation circuit when this third state; Wherein, this generation circuit is a complementary relationship in the output signal of this first state and the output signal of this second state.
The present invention also proposes a kind of SR latch, comprise: produce circuit, this generation circuit receives first input signal and second input signal and produces output signal, and this first input signal and this second input signal have three states, comprise first state that this first input signal operation and this second input signal do not move, this first input signal does not move second state with this second input signal operation, does not move the third state of not moving with this second input signal with this first input signal; And storage circuit, this storage circuit receive this output signal and this second input signal in order to keep this output signal of this generation circuit when this third state; Wherein, this generation circuit is a complementary relationship in the output signal of this first state and the output signal of this second state.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet appended accompanying drawing only provide with reference to and explanation, be not to be used for the present invention is limited.
Description of drawings
Figure 1 shows that known D type master-slave mode flip-flop circuit figure.
Figure 2 shows that known another D type master-slave mode flip-flop circuit figure.
Figure 3 shows that U.S. Pat 6232810 disclosed D type master-slave mode flip-flop circuit figure.
Figure 4 shows that scan flip-flop circuit.
Figure 5 shows that D type master-slave mode flip-flop circuit figure of the present invention
Figure 6 shows that NAND gate circuit figure.
Figure 7 shows that scan flip-flop circuit of the present invention.
Main description of reference numerals
| 10,12 | 14,24 |
| 20 | |
| 22,62,64,66,68,102,104,116 not | |
| 30,50,90 | 40,60,100 from |
| 42,44,106 NAND gate | 65,105 storage circuits |
| 70,110 multiplexers | 80 D flip- |
| 101 generation units | 112 transmission circuits |
| 114 data transmission circuits |
Execution mode
Please refer to Fig. 5, it is depicted as D type master-slave mode flip-flop circuit figure of the present invention.Since present embodiment propose transistor size less from latch 100.Moreover the present invention is not limited to the circuit structure of main latch 90, as long as main latch 90 is called sensor amplifier again, has following feature and gets final product.That is, when frequency signal (CLK) is input (D) input high level of first level and D type master-slave mode trigger, can make that setting end (Sb) is high level for the low level end (Rb) of resetting.Moreover, when main latch 50 is input (D) input low level of first level and D type master-slave mode trigger at frequency signal (CLK), can make that setting end (Sb) is low level for the high level end (Rb) of resetting.Moreover, when main latch 50 is second level at frequency signal (CLK), can make that setting end (Sb) is high level for the high level end (Rb) of resetting.In general, first level of frequency signal (CLK) and second level are complementary level.
From latch 100, be called the SR latch again, comprise generation unit 101 and storage circuit 105.Generation unit 101 comprises not gate 102, n transistor npn npn (Mn15), p transistor npn npn (Mp13).And in the generation unit 101, p transistor npn npn (Mp13) grid is connected to the setting end (Sb) of main latch 90, and p transistor npn npn (Mp13) source electrode is connected to voltage source (Vdd); Not gate 102 inputs are connected to the replacement end (Rb) of main latch 90; N transistor npn npn (Mn15) grid is connected to not gate 102 outputs, and n transistor npn npn (Mn15) drain electrode is connected to p transistor npn npn (Mp13) and drains and become the Q end, and n transistor npn npn (Mn15) source electrode is connected to earth terminal (Gnd).Storage circuit 105 comprises not gate 104 and NAND gate 106, wherein, NAND gate 106 1 inputs are connected to the Q end, and NAND gate 106 another inputs are connected to the replacement end (Rb) of main latch 90, NAND gate 106 outputs are connected to not gate 104 inputs, and not gate 104 outputs are connected to the Q end.
Therefore, reset end (Rb) during for low level, can export high level apace from the Q end of latch 100 for high level when the setting end (Sb) of main latch 90, and NAND gate 106 output low levels in the storage circuit 105, not gate 104 output high level.And reset end (Rb) during for high level for high level when the setting end (Sb) of main latch 90, can keep the output of Q end from the storage circuit 105 of latch 100 can not change, just high level.
Moreover, when the setting end (Sb) of main latch 90 is reset end (Rb) during for low level for high level, from the Q end of latch 100 output low level apace, and the NAND gate 106 output high level in the storage circuit 105, not gate 104 output low levels.And reset end (Rb) during for high level for high level when the setting end (Sb) of main latch 90, can keep the output of Q end from the storage circuit 105 of latch 100 can not change, just low level.
That is to say that when the input signal of setting end (Sb) and replacement end (Rb) was represented operation respectively and do not moved, it was exportable high level that Q holds; Otherwise, to represent respectively when not moving and moving when setting end (Sb) and the input signal of the end (Rb) of resetting, the Q end gets final product output low level; Moreover when the input signal of setting end (Sb) and replacement end (Rb) was all represented not move, the output level of Q end can remain unchanged.
Please refer to Fig. 6, it is depicted as NAND gate circuit figure.By among the figure as can be known, when two inputs (In1 and In2) when being high level, the n transistor npn npn of serial connection is opened and is made output (O) output low level.And when the equal input low level of two inputs (In1 and In2) or one of them input low level, output (O) output high level.According to Fig. 6 as can be known, NAND gate can be made up of four transistors.Therefore, of the present inventionly only need ten transistors to realize from latch 100 (SR latch).
Please refer to Fig. 7, it is depicted as scan flip-flop circuit of the present invention.Comprising multiplexer 110 and D type master-slave mode trigger.Multiplexer 110 comprises data transmission circuit 114, test transmission circuit 112 NAND gate 116.Data transmission circuit 114 comprises two the p transistor npn npns (Mp14, Mp15) and two n transistor npn npns (Mn16, Mn17) that are serially connected with voltage source (Vdd) and earth terminal (Gnd) in regular turn, p transistor npn npn (Mp15) is data transmission circuit 114 outputs and is connected to not gate 116 inputs with n transistor npn npn (Mn16) tie point, and not gate 116 outputs are the input that multiplexer 110 outputs can be connected to D type master-slave mode trigger.Moreover a pair of p transistor npn npn (Mp14) is connected to selecting side (SEL) and complementary selecting side (SELB) respectively with the grid of n transistor npn npn (Mn17).Moreover another is connected to the data input pin (Da) of multiplexer 110 to the p transistor npn npn (Mp15) and the grid of n transistor npn npn (Mn16).According to embodiments of the invention, data transmission circuit 114 comprises 2 p transistor npn npns and 2 the n transistor npn npns that are serially connected with voltage source and earth terminal, and in the application of reality, utilize more p transistor npn npn of number and n transistor npn npn to be serially connected with the equivalent function that also can reach data transmission circuit between voltage source and the earth terminal.
Test transmission circuit 112 comprises two the p transistor npn npns (Mp16, Mp17) and three n transistor npn npns (Mn18, Mn19, Mn20) that are serially connected with voltage source (Vdd) and earth terminal (Gnd) in regular turn, and p transistor npn npn (Mp17) is test transmission circuit 112 outputs with n transistor npn npn (Mn18) tie point and is connected to not gate 116 inputs.Moreover a pair of n transistor npn npn (Mn18) is connected to selecting side (SEL) and complementary selecting side (SELB) respectively with the grid of p transistor npn npn (Mp17).Moreover the grid of other p transistor npn npn (Mp16) and n transistor npn npn (Mn19, Mp20) is connected to the test input (DT) of multiplexer 110.According to embodiments of the invention, test transmission circuit 112 comprises 2 p transistor npn npns and 3 the n transistor npn npns that are serially connected with voltage source and earth terminal, and in the application of reality, utilize more p transistor npn npn of number and n transistor npn npn to be serially connected with and also can reach the equivalent function of testing transmission circuit between voltage source and the earth terminal.
According to embodiments of the invention, scan flip-flop circuit is (SEL is a high level) when test pattern, because the test data speed of test input (DT) input is slower.Therefore the present invention increases the serial connection number of n transistor npn npn (Mn19, Mp20), reaches the effect that prolongs the margin of holding time, and makes scan flip-flop circuit can normally move at test pattern.And the number of n transistor npn npn serial connection can increase and decrease according to the demand of the margin of in fact holding time, and the present invention is not limited to the number of n transistor npn npn serial connection.
Moreover, scan flip-flop circuit of the present invention is not limited to D type master-slave mode trigger of the present invention, and scan flip-flop circuit that multiplexer 110 of the present invention realized can reach the effect that the present invention prolongs the margin of holding time to utilize other trigger to arrange in pairs or groups.
In sum, though the present invention with preferred embodiment openly as above, it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention, can do various changes and retouching, so protection scope of the present invention should be as the criterion with appended claim.
Claims (14)
1, a kind of scan flip-flop circuit comprises:
Multiplexer and trigger, this multiplexer has selecting side, first input end and second input, and this multiplexer can and then be passed to the signal of this first input end or this second input the input of this trigger according to the selection signal of this selecting side input by the output of this multiplexer;
Wherein, this multiplexer comprises:
Data transmission circuit, this data transmission circuit comprises at least 2 p transistor npn npns and at least 2 the n transistor npn npns that are serially connected with voltage source and earth terminal in regular turn, and p transistor npn npn and n transistor npn npn tie point are the output of this data transmission circuit, the grid of a pair of p transistor npn npn and n transistor npn npn is connected to this first input end, and another grid to p transistor npn npn and n transistor npn npn receives this selection signal and this complementary selection signal respectively, when this selection signal was first level, the output of this data transmission circuit can transmit with respect to the signal of this first input end output to this multiplexer; And
The test transmission circuit, this test transmission circuit comprises at least 2 p transistor npn npns being serially connected with voltage source and earth terminal in regular turn and 2+N n transistor npn npn at least, and p transistor npn npn and n transistor npn npn tie point are the output of this test transmission circuit, this selection signal that the grid of a pair of n transistor npn npn and p transistor npn npn receives this selection signal and complementation respectively connects, when this selection signal is second level, the output of this test transmission circuit can transmit with respect to the signal of this second input output to this multiplexer, and N is more than or equal to 1.
2, scan flip-flop circuit as claimed in claim 1, wherein the output of the output of this data transmission circuit and this test transmission circuit is connected to not gate, and this non-gate output terminal is the output of this multiplexer.
3, scan flip-flop circuit as claimed in claim 1, wherein this trigger is a D flip-flop.
4, scan flip-flop circuit as claimed in claim 1, but these second input input test data wherein.
5, a kind of master-slave mode trigger comprises:
Sensor amplifier, this sensor amplifier can produce first signal and secondary signal according to input signal and frequency signal, wherein, when this input signal is that first level and this frequency signal are during for this first level, for this first signal moves first state that this secondary signal is not moved, when this input signal is that second level and this frequency signal are during for this first level, do not move second state of this second input signal operation for this first signal, when this frequency signal is this second level, the third state of all not moving for this first signal and this second input signal; And
Latch, this latch has the generation circuit, and in order to receiving this first signal and this secondary signal and then to produce output signal, and storage circuit receives this output signal and this secondary signal in order to keep this output signal of this generation circuit when this third state;
Wherein, this generation circuit is a complementary relationship in the output signal of this first state and the output signal of this second state.
6, master-slave mode trigger as claimed in claim 5, wherein this latch is the SR latch.
7, master-slave mode trigger as claimed in claim 5, wherein this first signal and this secondary signal are setting signal and reset signal.
8, master-slave mode trigger as claimed in claim 5, wherein this generation circuit comprises:
The one p transistor npn npn, a p transistor npn npn grid receives this first signal, and a p transistor npn npn source electrode is connected to voltage source;
First not gate, this first not gate input receives this secondary signal; And
The one n transistor npn npn, a n transistor npn npn grid is connected to this first non-gate output terminal, and n transistor npn npn drain electrode is connected to this p transistor npn npn drain electrode and can produces this output signal, and a n transistor npn npn source electrode is connected to earth terminal.
9, master-slave mode trigger as claimed in claim 5, wherein this storage circuit comprises:
NAND gate, the input of this NAND gate can receive this secondary signal; And
Second not gate, this second not gate input is connected to this NAND gate output, and this second non-gate output terminal is connected to another input of this NAND gate in order to receive this output signal.
10, a kind of SR latch comprises:
Produce circuit, this generation circuit receives first input signal and second input signal and produces output signal, and this first input signal and this second input signal have three states, comprise first state that this first input signal operation and this second input signal do not move, this first input signal does not move second state with this second input signal operation, does not move the third state of not moving with this second input signal with this first input signal; And
Storage circuit, this storage circuit receive this output signal and this second input signal in order to keep this output signal of this generation circuit when this third state;
Wherein, this generation circuit is a complementary relationship in the output signal of this first state and the output signal of this second state.
11, SR latch as claimed in claim 10, wherein this first input signal and this second input signal are setting signal and reset signal.
12, SR latch as claimed in claim 10, wherein this generation circuit comprises:
The one p transistor npn npn, a p transistor npn npn grid receives this first input signal, and a p transistor npn npn source electrode is connected to voltage source;
First not gate, this first not gate input receives this second input signal; And
The one n transistor npn npn, a n transistor npn npn grid is connected to this first non-gate output terminal, and n transistor npn npn drain electrode is connected to this p transistor npn npn drain electrode and can produces this output signal, and a n transistor npn npn source electrode is connected to earth terminal.
13, SR latch as claimed in claim 10, wherein this storage circuit comprises:
NAND gate, this NAND gate one end can receive this second input signal; And
Second not gate, this second not gate input is connected to this NAND gate output, and this second non-gate output terminal is connected to the other end of this NAND gate in order to receive this output signal.
14, SR latch as claimed in claim 10, wherein this first input signal and this second input signal are to be produced by sensor amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710092152 CN101051827A (en) | 2007-04-02 | 2007-04-02 | Scanning trigger circuit with lenghtening maintenance time margin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710092152 CN101051827A (en) | 2007-04-02 | 2007-04-02 | Scanning trigger circuit with lenghtening maintenance time margin |
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| Publication Number | Publication Date |
|---|---|
| CN101051827A true CN101051827A (en) | 2007-10-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710092152 Pending CN101051827A (en) | 2007-04-02 | 2007-04-02 | Scanning trigger circuit with lenghtening maintenance time margin |
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| Country | Link |
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| CN (1) | CN101051827A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783660B (en) * | 2009-01-16 | 2012-03-28 | 联发科技股份有限公司 | Flip-flop and pipelined analog-to-digital converter |
| CN105740177A (en) * | 2014-12-08 | 2016-07-06 | 台湾积体电路制造股份有限公司 | Signal transmission control method and apparatus, and signal latch apparatus |
-
2007
- 2007-04-02 CN CN 200710092152 patent/CN101051827A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783660B (en) * | 2009-01-16 | 2012-03-28 | 联发科技股份有限公司 | Flip-flop and pipelined analog-to-digital converter |
| CN105740177A (en) * | 2014-12-08 | 2016-07-06 | 台湾积体电路制造股份有限公司 | Signal transmission control method and apparatus, and signal latch apparatus |
| CN105740177B (en) * | 2014-12-08 | 2019-05-21 | 台湾积体电路制造股份有限公司 | The control method and device and signal latch device of signal transmission |
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