CN101038870A - Method for manufacturing grid structure of semiconductor device - Google Patents
Method for manufacturing grid structure of semiconductor device Download PDFInfo
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- CN101038870A CN101038870A CN 200610024667 CN200610024667A CN101038870A CN 101038870 A CN101038870 A CN 101038870A CN 200610024667 CN200610024667 CN 200610024667 CN 200610024667 A CN200610024667 A CN 200610024667A CN 101038870 A CN101038870 A CN 101038870A
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Abstract
The invention provides a mehtod for making grid structure of semiconductor device, which includes providing a semiconductor substrate, and forming a grid medium layer on the substrate, and forming a grid electrode layer on the grid medium layer, and forming a mask layer on the grid electrode layer, and then inducing etching gas to etch the polysilicon grid electrode layer by employing plasma output by a plasma source, wherein the plasma source etches the grid medium layer in pulse outputting power manner. The invention provide method for making grid structure of semiconductor device is very effective for accuracy controlling the thickness of the grid oxide layer in a process node no more then 65 nm, and the etching depth can perfectly stop at the surface of the grid oxide layer without hurting the surface of an active region.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly a kind of manufacture method of complementary mos device grid structure.
Background technology
Develop rapidly along with semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function, semiconductor wafer develops towards higher component density, high integration direction, and the grid of cmos device becomes more and more thinner and length becomes shorter.For fear of short channel effect and obtain maximum drain current, the thickness of grid oxic horizon is done more and more thinlyyer usually.Adopt the thickness of thin grid oxic horizon, can strengthen the coupling of gate electrode and channel carrier, make the more approaching long ditch device of transistor characteristic.Because drain current and gate capacitance approximately are directly proportional, so the attenuate gate oxide thickness also helps deep submicron process.For example in 65nm and following technology, the thickness of grid oxic horizon has reached about about 10～12 .
Application number is the grid structure manufacture method that 200310102359.1 Chinese patent application has been introduced a kind of field-effect transistor.The manufacturing process of cmos device at first is to form field oxide isolator on silicon substrate, for example silicon oxide film and silicon nitride film, patterned insulation layer also forms opening by photoetching and etching technics on insulating barrier, opening has and defines the corresponding shape in active region isolation district.By utilizing silicon nitride film as mask, the etch silicon substrate utilizes the insulating barrier of chemical vapor deposition methods such as (CVD) deposition as silicon oxide film, so that this insulating barrier is imbedded or embedded in the isolated groove then to form isolated groove.The unnecessary dielectric film that utilizes chemical and mechanical grinding method (CMP) will be deposited on the silicon nitride film is removed.In ensuing processing step, remove silicon nitride film, and carry out necessary ion and inject as mask.Afterwards, on the surface of active area, form grid oxidation film and polysilicon film.Utilize the photoresist pattern by anisotropic etch process with grid oxidation film and polysilicon film patternization, to form insulated gate electrode.Can form gate electrode by pattern with high precisionization with utmost point short gate length.Be injected in the district of gate electrode both sides with after forming the expansion area at ion, the dielectric film of deposition as silicon oxide film also carries out anisotropic etching with the formation side wall spacers.By utilizing gate electrode and side wall spacers as mask, carry out ion and inject to form source/drain region high impurity concentration or dark and the LDD (low doped drain region) that prevents short-channel effect, annealing then forms source electrode and drain electrode to activate the foreign ion that injects.
Common using plasma etching technics feeds etching gas, for example the mist of oxygen and argon gas in reative cell in the etching of grid oxic horizon.Under certain temperature and pressure, utilize high frequency power source to provide high frequency voltage with certain power, in the plasma span, make oxygen ionization generate the high-energy oxygen plasma,, reach the purpose of etching grid oxic horizon by the grid oxic horizon of high energy oxygen plasma bombardment wafer surface.In the etching technics of traditional polysilicon gate, because high frequency power source is output high voltage in a continuous manner, oxonium ion bombards grid oxic horizon continuously, very easily make oxonium ion pass grid oxic horizon, enter into active area and LDD zone, make the following silicon of grid oxic horizon also become silica, in follow-up wet method HF cleaning, be removed, thereby produce depression inevitably.Fig. 2 is the schematic diagram that traditional etching technics produces depression.As shown in Figure 2, active area on the substrate 100 and LDD zone have produced depression, and this depression is approximately the degree of depth of 20-40 .To traditional technology node, 0.13um device for example, the about 70-200 of thickness of grid oxide layer, the depression of this 20-40 can not influence the performance of device for the cmos device of 0.13um.Yet, manufacturing process for 65nm and even 45nm, the thickness of grid oxic horizon has only about 10 , oxygen plasma is not objective can to penetrate grid oxic horizon with avoiding and makes following active area and LDD zone produce the cup depth of about 20 , device performance will seriously reduce, and the degree of depth of LDD will be difficult to control.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of grid structure of semiconductor device, adopt the carry out etching of the mode of pulse output power by plasma source when the etching grid oxic horizon, to solve that prior art ionic medium body penetrates grid oxic horizon and the problem that makes active area below it and LDD zone produce depression to grid oxic horizon.
For achieving the above object, the manufacture method of grid structure of semiconductor device provided by the invention comprises:
E., semi-conductive substrate is provided in reative cell, on substrate, forms gate dielectric layer;
F. on gate dielectric layer, form grid layer, on gate electrode layer, form mask layer,
G. feed etching gas etch polysilicon grid layer;
H. plasma source adopts the mode etching gate dielectric layer of pulse output power.
The output power range of described plasma source is 200-2000W.
The percentage that the time range of described plasma source power output accounts for whole etch period scope is 5%-90%.
Pressure in the described reative cell is 5mT-100mT.
Keep described substrate temperature between 20-80 ℃.
Described grid layer is the polysilicon gate layer.
Described gate dielectric layer comprises silica or silicon oxynitride at least.
Described etching gas comprises a kind of in the following gas at least: oxygen O
2, nitrogen N
2, argon Ar, helium He and neon Ne.
Compared with prior art, the present invention has the following advantages:
The manufacture method of grid structure of the present invention is when the etching grid oxic horizon, and plasma source adopts the carry out etching of the mode of pulse output power to grid oxic horizon, makes the controlled and buffering of the corrasion of plasma on grid oxic horizon.In that grid oxic horizon is as thin as a wafer carried out in the process of etching, can accurately control the degree of depth of etching, in the grid oxic horizon etching, can eliminate the phenomenon that produces depression in active area and LDD zone fully.The manufacture method of grid structure of the present invention is by using the mode of pulse plasma etching, the time width of plasma source power output accounts for the ratio of whole pulse period and can adjust arbitrarily, that is to say that in whole etch stages, the time interval of plasma etching grid oxic horizon can be provided with arbitrarily.The manufacture method of grid structure of the present invention is very effective for accurately controlling the grid thickness of oxide layer at 65nm and following process node, and etching depth can ideally stop at the gate oxidation laminar surface and can not cause any depression to surfaces of active regions.
Description of drawings
Fig. 1 is the grid structure of semiconductor device schematic diagram;
Fig. 2 is the grid structure schematic diagram after the existing etching technics etching of employing;
The grid structure schematic diagram of Fig. 3 after for the manufacture method etching that adopts grid structure of the present invention;
Fig. 4 is a plasma pulse way of output schematic diagram.
Embodiment
The present invention has disclosed a kind of manufacture method of grid structure of semiconductor device.Etching for 65nm and following grid oxic horizon has very high precision.This method can be used for making very lagre scale integrated circuit (VLSIC) (ULSI) grid oxic horizon semiconductor device as thin as a wafer.
The present invention also comprises the manufacture method of field-effect transistor, and such as CMOS (Complementary Metal Oxide Semiconductor) (CMOS) field-effect transistor, this field-effect transistor comprises metal gate electrode and ultra-thin gate dielectric layer (such as 10-20 ).Fig. 1 is the grid structure of semiconductor device schematic diagram.As shown in Figure 1, on substrate 100, form grid oxic horizon 110 and gate electrode layer 120.Technological process has comprised in the gate fabrication process process, the technology of being done on thin layer.Photoetching process and sub-technology thereof (such as exposure, gluing, cleaning substrate etc.) all belong to common process.The structure sheaf of growth field-effect transistor on substrate 100 at first utilizes the active area of the method formation of ion injection behind the transistor arrangement layer of grow, wherein comprise source region and lightly doped drain (LDD) in the active area, is used to prevent short channel effect.Each transistorized source region and drain region are all separated by raceway groove.Structure sheaf comprises polygate electrodes 120 and gate dielectric layer 110.Generally, gate electrode layer 120 adopts doped polycrystalline silicon materials, thickness 500-6000 .Gate electrode layer 120 can comprise a kind of metal (such as titanium Ti, tantalum Ta, tungsten w etc.) and metallic compound (such as titanium nitride TiN, tantalum nitride TaN, tungsten nitride WN etc.) at least.Gate dielectric layer 110 adopts silicon dioxide (SiO usually
2), material or its combination such as silicon oxynitride SiON.As selection, dielectric layer 110 can comprise hafnium.In this article, dielectric constant surpasses 4.0 medium and is meant hafnium.Gate dielectric layer 110 adopts earth silicon material, thickness 10-20 in the present embodiment.It should be noted that in different embodiment, gate dielectric layer 110 can adopt different materials, adopt different thickness.The growing method of gate dielectric layer 110 can be any conventional vacuum coating technology, such as atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like.
Form mask layer as etching barrier layer on gate electrode layer 120, etching is also removed gate electrode layer 120.Gate dielectric layer 110 is used as etch stop layer.The using plasma etching technics, the duration of technology is according to etch period, the specific reflection wavelength of plasma, laser interference, and other technology is controlled.Be etching gate electrode layer 120, etching agent adopts admixture of gas, and mist can comprise such as chlorine Cl
2, oxygen O
2, nitrogen N
2, helium He and oxygen O
2Mist, perhaps helium-oxygen He-O
2, and inert gas or its mist (such as hydrogen Ar, neon Ne, helium He or the like), or its combination.The etching agent that this etching gate electrode is used has very high corrosion selectivity for gate dielectric 110 (such as SiO2, SiON, high K medium).During etching, the directivity of etching can realize by control cathode (substrate just) substrate bias power.By the control substrate bias power can control grid electrode 120 etch period.In the present embodiment, feed etchant gas flow 50-400sccm in the reative cell, underlayer temperature is controlled between 20 ℃ and 90 ℃, and chamber pressure is 4-80mTorr, plasma source power output 1000W.
Gate dielectric layer 110 adopts silica material, and the etching agent during etching comprises chlorine Cl
2, oxygen O
2, nitrogen N
2, helium He and oxygen O
2Mist, perhaps helium one oxygen He-O
2, and inert gas or its mist (such as hydrogen Ar, neon Ne, helium He or the like), or its combination.Flow is 40-80sccm, and plasma source power output 200-2000W, underlayer temperature are controlled between 20 ℃ and 80 ℃, and chamber pressure is 5-50mTorr.In traditional etching technics, grid oxic horizon 110 is when etching, and the power output of plasma source is continuous, that is to say that plasma is continuous to the etching of substrate surface.Plasma very easily penetrates grid oxic horizon 110 and enters active area and LDD zone in the silicon substrate 100 below the grid oxic horizon, HF cleaning after etching, inevitably can be at the active area on silicon substrate 100 surfaces and the section profile (as shown in Figure 2) of LDD zone appearance depression, this depression can reach 20-40 .For 90nm and above technology, the depression of 20 is not remarkable to the influence of device performance.Yet for 65nm and following technology, the thickness of grid oxic horizon 110 has only about 10～12 .The depression of 20 will cause the variation of lightly doped drain (LDD) degree of depth and cause short-channel effect, reduce the performance of device.Grid structure manufacture method of the present invention is when etching grid oxic horizon 110, and plasma source adopts the mode of pulse output power, in etching process is to be interrupted rather than to export plasma continuously the grid oxic horizon 110 of substrate surface is carried out etching.Fig. 4 is a plasma pulse way of output schematic diagram.As shown in Figure 4, the axis of abscissas of Fig. 4 is represented the time that etching process is required, and ordinate is represented the power output of plasma source.In the period T of etch stages, the power output of plasma source adopts the mode of pulse output, comprises output cycle and dwelling period.At output cycle plasma source output plasma the grid oxic horizon of substrate surface is carried out etching, stop to export plasma at the dwelling period plasma source.And, the percentage that the output cycle accounts for whole period T can be controlled at 5-90%, can arbitrarily adjust output cycle proportion according to the thickness of grid oxic horizon, so just can accurately control the power output of plasma source and, reach the purpose of control grid oxic horizon etch thicknesses the etching intensity of grid oxic horizon.
The grid structure schematic diagram of Fig. 3 after for the manufacture method etching that adopts grid structure of the present invention.As shown in Figure 5, the manufacture method of grid structure of the present invention is after etching is finished grid 120 on the substrate 100, when etching grid oxic horizon 110, plasma source adopts the mode of pulse output power, the output plasma makes that to the etching of carrying out of grid oxic horizon 110 corrasion of plasma on grid oxic horizon 110 is controlled.To the etching of grid oxic horizon as thin as a wafer the time, adopt plasma etching mode as shown in Figure 4, make that etch thicknesses can be precisely controlled, in the grid oxic horizon etching, can eliminate the depressed phenomenon that produces in active area and LDD zone fully.Very effective for accurately controlling the grid thickness of oxide layer at 65nm and following process node.Etching depth can ideally stop at the gate oxidation laminar surface and can not cause any depression to surfaces of active regions.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1, a kind of manufacture method of grid structure of semiconductor device comprises:
A., semi-conductive substrate is provided in reative cell, on substrate, forms gate dielectric layer;
B. on gate dielectric layer, form grid layer, on gate electrode layer, form mask layer,
C. feed etching gas etch polysilicon grid layer;
D. plasma source adopts the mode etching gate dielectric layer of pulse output power.
2, the method for claim 1 is characterized in that: the output power range of described plasma source is 200-2000W.
3, method as claimed in claim 1 or 2 is characterized in that: the percentage that the time range of described plasma source power output accounts for whole etch period scope is 5%-90%.
4, method as claimed in claim 3 is characterized in that: the pressure in the described reative cell is 5mT-100mT.
5, method as claimed in claim 3 is characterized in that: keep described substrate temperature between 20-80 ℃.
6, the method for claim 1 is characterized in that: described grid layer is the polysilicon gate layer.
7, the method for claim 1 is characterized in that: described gate dielectric layer comprises silica or silicon oxynitride at least.
8, the method for claim 1 is characterized in that: described etching gas comprises a kind of in the following gas at least: oxygen O
2, nitrogen N
2, argon Ar, helium He and neon Ne.
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| CNB2006100246670A CN100459053C (en) | 2006-03-14 | 2006-03-14 | Method for manufacturing grid structure of semiconductor device |
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| CNB2006100246670A CN100459053C (en) | 2006-03-14 | 2006-03-14 | Method for manufacturing grid structure of semiconductor device |
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| CN101038870A true CN101038870A (en) | 2007-09-19 |
| CN100459053C CN100459053C (en) | 2009-02-04 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241103A (en) * | 2013-06-14 | 2014-12-24 | 无锡华润上华科技有限公司 | Method for manufacturing WSI composite gate |
| CN104752181A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Pseudo gate removing method |
| CN104979175A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Grid electrode formation method and transistor formation method |
| CN107275212A (en) * | 2016-04-07 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11224796A (en) * | 1998-02-05 | 1999-08-17 | Matsushita Electron Corp | Apparatus and method for plasma treatment |
| US6255221B1 (en) * | 1998-12-17 | 2001-07-03 | Lam Research Corporation | Methods for running a high density plasma etcher to achieve reduced transistor device damage |
| JP4425370B2 (en) * | 1999-04-28 | 2010-03-03 | 株式会社半導体エネルギー研究所 | Dry etching method and plasma ashing method |
| JP4121356B2 (en) * | 2002-10-31 | 2008-07-23 | 富士通株式会社 | Semiconductor device |
| JP2005072260A (en) * | 2003-08-25 | 2005-03-17 | Sanyo Electric Co Ltd | Plasma treatment method, plasma etching method, and method of manufacturing solid-state imaging element |
| US7303996B2 (en) * | 2003-10-01 | 2007-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics |
| JP4342984B2 (en) * | 2004-03-10 | 2009-10-14 | Ｏｋｉセミコンダクタ株式会社 | Etching method |
-
2006
- 2006-03-14 CN CNB2006100246670A patent/CN100459053C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241103A (en) * | 2013-06-14 | 2014-12-24 | 无锡华润上华科技有限公司 | Method for manufacturing WSI composite gate |
| CN104752181A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Pseudo gate removing method |
| CN104979175A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Grid electrode formation method and transistor formation method |
| CN107275212A (en) * | 2016-04-07 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
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|---|---|
| CN100459053C (en) | 2009-02-04 |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
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Effective date of registration: 20111108 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |