CN101035191B - Solid state image forming device, method of driving the same and camera - Google Patents
Solid state image forming device, method of driving the same and camera Download PDFInfo
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- CN101035191B CN101035191B CN2007100856727A CN200710085672A CN101035191B CN 101035191 B CN101035191 B CN 101035191B CN 2007100856727 A CN2007100856727 A CN 2007100856727A CN 200710085672 A CN200710085672 A CN 200710085672A CN 101035191 B CN101035191 B CN 101035191B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
- H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
- H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor
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Abstract
A solid imaging device includes: plural pixels which respectively convert incidence light quantity into electrical signals and are arranged in plural rows and deviate adjacent pixel in line direction or row direction; plural A/D conversion units which respectively convert the analog signal obtained from corresponding pixel into digital signal and are arranged along the row in parallel; plural row signal wires for outputting analog signal of pixel of all the plural pixel rows, and arranged along the pixel row, and forming in pair; and plural switch circuit units which respectively select one row signal wire in corresponding row signal wire-pair. In the solid imaging device, the A/D conversion units are connected to the output side of the switch circuit units.
Description
The cross reference of related application
The present invention comprises the relevant theme of Japanese patent application JP2006-059022 of submitting to Japan Office with on March 6th, 2006, merges its full content at this by reference.
Technical field
The present invention relates to solid-state imaging apparatus, drive method and the video camera of this solid-state imaging apparatus.
Background technology
The method that arranges a plurality of A/D converting units in MOS type solid-state imaging apparatus is disclosed, wherein this MOS type solid-state imaging apparatus comprise a plurality of photo-electric conversion elements of being arranged to be staggered (staggered) and a plurality of A/D converting unit (for example referring to, JP-A-2001-223350).
With reference to the block diagram of Figure 10 MOS type solid-state imaging apparatus according to the first example of correlation technique is described.
As shown in figure 10, in MOS type solid-state imaging apparatus 100, the a plurality of photo-electric conversion elements 110 that comprise separately photodiode are arranged on a surface in Semiconductor substrate 101, so that each photo-electric conversion element in the row direction or depart from adjacent photo-electric conversion element on the column direction, that is to say, photo-electric conversion element is arranged to is staggered.A plurality of output signal lines 130 are arranged as corresponding one by one with photo-electric conversion element row 111.As shown in figure 10, each output signal line 130 extends in the left side of the photo-electric conversion element row 111 of correspondence along the photo-electric conversion element row 111 of correspondence.Each output signal line 130 is electrically connected with photo-electric conversion element 110 in the corresponding photo-electric conversion element row 111 by switch circuit units.The output transistor that is included in each switch circuit units can according to the signal charge amount of storage in the corresponding photo-electric conversion element 110, and generate power detection signal at the output signal line 130 of correspondence.
On Semiconductor substrate 101, provide in a plurality of A/D converting units 140 each for per two output signal lines 130.In the A/D converting unit 140 each is electrically connected to the output signal line 130 of two correspondences.In addition, each in the A/D converting unit 140 is configured to have A/D converter 145.For example, a plurality of sample/hold circuit unit 141 is disposed between each A/D converter 145 and two output signal lines 130 corresponding to this A/D converter 145 separately.Each of A/D converter 145 sequentially generates the digital signal corresponding with the power detection signal that generates at two corresponding holding wires 130, and exports this digital signal.Because described a plurality of photo-electric conversion elements 110 are arranged to and are staggered, so on two output signal lines 130 corresponding with an A/D converting unit 140, do not generate simultaneously power detection signal.Only generate power detection signal at one of two output signal lines 130 corresponding with an A/D converting unit 140.
Figure 11 is the block diagram for the second example of explanation correlation technique.
As shown in figure 11, identical with operation according to those basic configuration in the first example of the basic configuration of the MOS type solid-state imaging apparatus 200 of correlation technique the second example and operation and correlation technique.Yet in the second example, a plurality of output signal lines 130 are arranged to separately complications and pass photo-electric conversion element row 110 corresponding to (meander) in plane graph.Therefore, can be with the decreased number of output signal line 130 in the first example half.
In any the MOS type solid-state imaging apparatus according to the first and second examples of correlation technique, a plurality of photo-electric conversion elements 110 are arranged to and are staggered.When taking above-mentioned configuration, that is to say, when a plurality of photo-electric conversion elements 110 are arranged to when being staggered, photo-electric conversion element is capable to comprise the photo-electric conversion element 110 that is arranged in even numbered columns or the photo-electric conversion element 110 that is arranged in odd numbered columns.Therefore, by for per two photo-electric conversion element row 111 provide an A/D converting unit 140, each A/D converting unit can receive the signal of telecommunication that the output transistor by correspondence generates individually, and generates the digital signal corresponding with the signal of telecommunication that receives.In this situation, describe such as top first and second examples that relate to, the sum of A/D converting unit 140 can be reduced to half of sum of photo-electric conversion element 111.That is to say, in correlation technique, the sum of A/D converting unit 140 can be reduced half.As a result, even when the integrated level of photo-electric conversion element uprises, also can form A/D converting unit 140, and not need to use very complicated micro-fabrication technology.Therefore, can reduce manufacturing cost.
Yet, in these examples, so that the sum of A/D converting unit 140 becomes half of sum of photo-electric conversion element row 111.Therefore, in the first example, because column signal line 130 is connected to each A/D converting unit 140 by twos, so the total length of the column signal line 130 that is connected with an A/D converting unit 140 becomes the twice of the total length in the correlation technique.In the second example, because column signal line 130 separately complications passes two photo-electric conversion element row, so the length of the column signal line 130 that is connected with an A/D converting unit 140 becomes the twice of the length in the correlation technique, perhaps the number of the photo-electric conversion element 110 on column signal line 130 becomes the twice of the number in the correlation technique.As a result, because wiring or the load capacitance of element, so that the signal-obtaining of photo-electric conversion element 110 is become longer to the time that column signal line 130 spends.
Particularly, in cmos image sensor, usually, in pixel, provide amplifier.This amplifier is carried out amplification and is read.The amplifying unit of amplifier is carried out source follower and is read.In source electrode-drain electrode read mode and since amplify to be by with current source arrangement in the upstream of column signal line or downstream and electric current is applied to the amplifier transistor of pixel carries out, so when the load capacitance increase of amplifier transistor, the time of reading is elongated.
Summary of the invention
In these examples, because the length of the column signal line that is connected with each A/D converting unit is approximately the twice in the correlation technique, so wiring capacitance or pixel capacitance become the twice in the correlation technique.Therefore, the signal of photo-electric conversion element arrives the time quantum increase that column signal line spends.As a result, the high speed operation performance degradation of solid-state imaging apparatus.
Therefore, expectation provide can be by the physical length that reduces each column signal line from pixel to the A/D converting unit solid-state imaging apparatus of high speed operation.
According to embodiments of the invention, a kind of solid-state imaging apparatus is provided, comprising: a plurality of pixels are used for separately incident light quantity is converted to the signal of telecommunication, and are disposed in and follow direction or column direction from a plurality of row that neighbor departs from; A plurality of AD conversion unit, the analog signal conversion that is used for separately obtaining from respective pixel is digital signal, and is arranged along row are parallel; A plurality of column signal lines are used for exporting each the analog signal of pixel of a plurality of pixel columns, arrange along pixel column, and form right; And a plurality of switch circuit units, separately for a column signal line selecting corresponding column signal line centering.In solid-state imaging apparatus, AD conversion unit is connected to the outlet side of switch circuit units.
In the solid-state imaging apparatus in an embodiment according to the present invention, in order to export the analog signal of a plurality of pixel columns, it is right that the column signal line of arranging along each pixel column forms, for every a pair of switch circuit units that provides selecting one of column signal line to reply, and described AD conversion unit is connected to the outlet side of switch circuit units.Therefore, the sum of AD conversion unit becomes half of pixel column sum, and simultaneously, because switch circuit units, becomes in the correlation technique half so that be connected to the number of the column signal line of each AD conversion unit.As a result, the physical length of the column signal line from each pixel to the AD conversion unit corresponding with it becomes shorter.
Solid-state imaging apparatus according to the embodiment of the invention provides switch circuit units, selecting one of two column signal lines of every centering, and provides AD conversion unit, so that corresponding one by one with the output of switch circuit units.Therefore, compare with correlation technique, can reduce the signal-obtaining of pixel to time that column signal line spends.As a result, solid-state imaging apparatus can be with higher speed operation.
Description of drawings
Fig. 1 is the block diagram that illustrates embodiments of the invention (the first embodiment);
Fig. 2 is the circuit diagram that illustrates the Circnit Layout example of pixel;
Fig. 3 is the circuit diagram that illustrates the Circnit Layout example of current source;
Fig. 4 is the circuit diagram that illustrates the Circnit Layout example of switch circuit units;
Fig. 5 is the block diagram for the operation of explanation the first embodiment;
Fig. 6 is the figure about the effect of the time of reading that has showed according to the embodiment of the invention;
Fig. 7 is the block diagram that illustrates an alternative embodiment of the invention (the second embodiment);
Fig. 8 is the circuit diagram that illustrates the Circnit Layout example of switch circuit units;
Fig. 9 is the block diagram for the operation of explanation the second embodiment;
Figure 10 is the block diagram that illustrates according to the first example of correlation technique;
Figure 11 is the block diagram that illustrates according to the second example of correlation technique; And
Figure 12 is the cross-sectional view that illustrates according to the video camera of third embodiment of the invention.
Embodiment
In connection with the block diagram of Fig. 1 embodiments of the invention (the first embodiment) are described.Fig. 1 shows MOS type solid-state imaging apparatus, and it comprises and is arranged to staggered a plurality of photo-electric conversion element and a plurality of analog to digital converter.
As shown in Figure 1, solid-state imaging apparatus 1 a plurality of pixels 12 of comprising a plurality of photo-electric conversion elements and having separately amplifier.Described pixel 12 that is to say with matrix arrangement, has formed pel array 11 thereby be arranged to be staggered.In the photo-electric conversion element each for example comprises photodiode." a plurality of photo-electric conversion elements are arranged to and are staggered " refers to: the photo-electric conversion element that consists of even-numbered photo-electric conversion element row has departed from half of pitch (pitch) P1 between two adjacent light electric transition elements each photo-electric conversion element row from the photo-electric conversion element that consists of odd-numbered photo-electric conversion element row on column direction; And consist of the capable photo-electric conversion element of even-numbered photo-electric conversion element and go up in the row direction half that has departed from pitch P2 between two adjacent light electric transition elements each photo-electric conversion element is capable from the capable photo-electric conversion element of formation odd-numbered photo-electric conversion element, so that the capable photo-electric conversion element that only comprises in even numbered columns or the odd numbered columns of each photo-electric conversion element.
When two adjacent pixels are arranged as in a zigzag as mentioned above, owing to may reduce pitch between the pixel, so can increase apparent resolution on the line direction (horizontal direction) and the apparent resolution on the column direction (vertical direction).Yet in cmos image sensor, the pitch between the pixel becomes less, more is difficult to the cloth circuits.
For this reason, in the present invention, it is right that a plurality of column signal lines that the analog signal that obtains from pixel 12 outputs to form, and be connected to a plurality of switch circuit units 21 be used to one of two column signal lines selecting described each centering.That is to say, for every a pair of column signal line provides a switch circuit units 21.The comparator 13 that the output of each switch circuit units 21 is connected to current source 22 and provides in analog to digital converter.Arranged a plurality of analog to digital converters, and described analog to digital converter has consisted of row Parallel ADC piece 15.Here, ADC is the abbreviation of analog to digital converter.
The counter 14 that each analog to digital converter of row Parallel ADC piece 15 comprises a comparator 13 and is used for counting comparing number of times, and have n position digital signal translation function (n is natural number).Comparator 13 relatively generated by digital to analog converter 19 (hereinafter, referred to as DAC) and the signal RAMP (slope) by reference line 23 inputs and by column signal line V0, V1 ... and from row signal line H0, H1 ... in the analog signal that obtains of pixel 12.
In addition, be used for to generate the timing control circuit 20 of internal clocking, the column scan circuit 17 that is used for the line-scan circuit 18 of control row addressing or line scanning and is used for control row addressing or column scan is arranged to the sequentially effect of the control circuit of the signal of read pixel array 11 that is used from.
In this embodiment, the number of the number of the number of horizontal output line 16, sensor circuit and the output circuit n that all respectively does for oneself.Yet, can the individual horizontal output line of parallelization n * m (m is natural number), n * m sensor circuit and n * m output circuit, thus its output speed increased.In some cases, can use n * m horizontal output line 16, n * m sensor circuit and an output circuit (m ≠ 1, n * 1, and the 1st, natural number), and can between sensor circuit and output circuit, arrange parallel-to-serial converter circuit or deserializer circuit.
Fig. 2 shows the example of the Circnit Layout of each pixel 12.A pixel (unit picture element) 12 comprises: photodiode 31; Transfering transistor 32 is used for to the electric charge of the diffusion layer 36 transfer phototransistors 31 of floating; Amplifier transistor 34 cooperates with executive signal to amplify by source follower and the current source that provides at terminal Vx place of the electric charge that reads the diffusion layer 36 of floating; Reset transistor 33, the electric charge of the diffusion layer 36 of for example floating for resetting; And select transistor 35, be used for read signal and the signal that reads is outputed to terminal Vx.In this ios dhcp sample configuration IOS DHCP, all crystals pipe all is the N channel transistor.Yet, even part or all crystals pipe can be p channel transistors, also obtain identical configuration.In addition, can omit transfering transistor 32.In addition, can omit and select transistor 35, and utilize power supply to carry out and select control.And a plurality of unit picture elements can be shared any parts.
Fig. 3 shows the Circnit Layout example of current source 22.Current source 22 comprises the N channel transistor 51 as the constant-current source operation.The source ground of N channel transistor 51, its drain electrode is connected to the output of commutation circuit 21, and its grid setovered arbitrarily, and in this ios dhcp sample configuration IOS DHCP, current source comprises a N channel transistor.Yet the configuration of current source is not limited to this.Current source can comprise any circuit that can stably be operating as constant-current source.For example, in order to improve operational stability, current source can comprise cascade transistor.
Fig. 4 shows the example of the Circnit Layout of a switch circuit units 21.Each switch circuit units 21 comprises switches N channel transistor 41 and 42 and inverter.Described switching N channel transistor 41 has the drain electrode that is connected to column signal line V2x (x be 0 or natural number), to grid and the source electrode of its input switch-over control signal a0, and described switching N channel transistor 42 has the drain electrode that is connected to column signal line V2x+1 (x be 0 or natural number), to its input by grid and the source electrode of inverter to the anti-phase inversion signal that obtains of switch-over control signal a0.The source electrode that switches N channel transistor 41 and 42 is connected to the comparator 13 (seeing Fig. 1) of current source 22 (seeing Fig. 1) and row Parallel ADC piece 15, as public output.When being directly inputted to switch-over control signal a0 (for example, address signal) in the switch circuit units 21, with this switch-over control signal a0 accordingly, switch N channel transistor 41 and 42 by separately conducting or cut-off, thereby switch switch circuit units 21.Because inverter is provided, thus with a control signal accordingly, must be to switch one of N channel transistor 41 and 42 conducting, and another cut-off.More specifically, according to control signal, must be, switch N channel transistor 41 conductings and switch 42 cut-offs of N channel transistor, perhaps switch 41 cut-offs of N channel transistor and switch 42 conductings of N channel transistor.
That is to say, need configuration switch circuit units 21, thus output from corresponding with selected pixel column from the column signal line V2x of read pixel and only one the signal the V2x+1, and therefore Circnit Layout is not limited to above-mentioned configuration.For example, except the N channel transistor, switch circuit units 21 can comprise that a plurality of p channel transistors or parallel join are with N channel transistor and the p channel transistor of complementary operation.
The example of the Circnit Layout when Fig. 5 shows least significant bit (LSB) when the row address signal before the address decoding and is set to the switch-over control signal of switch circuit units 21.In Fig. 5, only show the critical piece that from Fig. 1, extracts.
As shown in Figure 5, row address signal a0, a1 before the decoding of address ... least significant bit (LSB) when being used as the switch-over control signal of switch circuit units 21, wherein said row address signal a0, a1 ... be supplied to the row address decoding circuit that in line-scan circuit 18, comprises, therefore select column signal line V2x or the V2x+1 corresponding with selected row signal line (any among row signal line H0, H1, H2 and the H3), and do not need the switch-over control signal that provides independent.
In the solid-state imaging apparatus 1 according to the first embodiment, be used for exporting the analog signal of a plurality of pixel columns and formed by the column signal line of arranging along each pixel column right, a switch circuit units 21 is provided, it be used for to select forms the column signal line of a pair of two column signal line V2x and V2x+1, and the AD conversion unit of row Parallel ADC piece 15 is connected to the output of switch circuit units 21, so that corresponding one by one with switch circuit units 21.Therefore, the sum of AD conversion unit is reduced to half of pixel column number, and meanwhile, because described switch circuit units 21, and half in the correlation technique of the decreased number that makes the column signal line that is connected with AD conversion unit.Therefore, can reduce the length of the essence column signal line of the AD conversion unit from each pixel 12 to row Parallel ADC piece 15.In this mode, solved because column signal line V0, V1 ... arrange in staggered mode along the both sides of pixel column and increased the problem of length of arrangement wire.Therefore, since reduced with the signal-obtaining of unit picture element 12 to column signal line V0, V1 ... the time that spends is so the advantage of solid-state imaging apparatus 1 is its high speed operation.In addition, owing to the column circuits (being AD conversion unit) of row Parallel ADC piece 15 can be arranged according to the large pitch of pitch twice between the pixel 12, so its layout is simplified.In addition, since the number of AD conversion unit than reducing half in the correlation technique, so can reduce circuit area.
Referring now to the circuit diagram of the block diagram of Fig. 1 and 5 and Fig. 2 to 4 operation according to the MOS type solid-state imaging apparatus of this embodiment is described.
When having selected even-numbered row signal line H2x (x be 0 or natural number), signal is outputed to even-numbered row signal line V2x (x be 0 or natural number) from unit picture element 12.At this moment, based on switch-over control signal a0, switch circuit units 21 selection even-numbered column signal line V0, V2 ..., so that from even-numbered row signal line output signal, and disconnection odd-numbered column signal line V1, V3 ...Similarly, when having selected odd-numbered holding wire H2x+1 (x be 0 or natural number), signal is outputed to odd-numbered column signal line V2x+1 (x be 0 or natural number) from unit picture element 12.At this moment, based on switch-over control signal a0, switch circuit units 21 selection odd-numbered column signal line V1, V3 ..., in order to export described signal from this odd-numbered column signal line, and disconnection even-numbered column signal line V0, V2 ...In this embodiment, the even-numbered row signal line is corresponding to the odd-numbered column signal line, and the odd-numbered row signal line is corresponding to the odd-numbered column signal line.Even when the even-numbered row signal line during corresponding to the even-numbered column signal line, also can be disposed this situation by only changing switch control logic corresponding to odd-numbered column signal line and odd-numbered row signal line simply.
In above-mentioned operation, utilize switch circuit units 21, and the general only is connected to output corresponding to the column signal line of selected row signal line, and will disconnects with output corresponding to the column signal line of non-selected row signal line, and then read the signal of unit picture element 12.Therefore, the load capacitance of the wiring during signal-obtaining or element has reduced only about half of than the example of correlation technique.Thereby, can reduce the time quantum that read signal spends.
Fig. 6 shows the Simulation results according to the representative effect of the embodiment of the invention.More specifically, Fig. 6 show when with the signal-obtaining of unit picture element 12 during to column signal line, Measurement sensibility this read the figure of the Simulation results of the time that spends.The time of reading of the vertical axis representative among Fig. 6 is determined by various parameters, such as the length of holding wire, the thickness of holding wire, feature, component number, component size and the reading current of holding wire.In this drawing, the time of reading is the relative value under any condition, and represents with arbitrary unit.According to this figure, can find out, compare with the first and second comparative example of correlation technique, almost reducing half according to the time of reading in the solid-state imaging apparatus of the embodiment of the invention.In the time can reducing the time quantum that the signal-obtaining of unit picture element is spent to column signal line, solid-state imaging apparatus can be with higher speed operation.Therefore, can increase service speed of the present invention.
Fig. 7 is the block diagram that illustrates MOS type solid-state imaging apparatus according to a second embodiment of the present invention, wherein, this MOS type solid-state imaging apparatus comprises and is arranged to staggered a plurality of photo-electric conversion element and a plurality of AD conversion unit (hereinafter, be called ADC), and from this MOS type solid-state imaging apparatus outputting analog signal.
As shown in Figure 7, except the internal configurations of switch circuit units 24, has identical structure according to the solid-state imaging apparatus 2 of the second embodiment with solid-state imaging apparatus 1 according to the first embodiment.That is to say that solid-state imaging apparatus 2 has a plurality of pixels 12, each comprises photo-electric conversion element and the amplifier that forms therein.Pixel 12 is with matrix arrangement, more specifically, is arranged to and is staggered, thereby form pel array 11.
It is right that a plurality of column signal lines of the analog signals that obtain to its output from pixel 12 form, and provide switch circuit units 24 for every pair, to select to form one of two column signal lines to reply.That is to say, for per two column signal lines provide a switch circuit units 24.The comparator 13 that the output of each switch circuit units 24 is connected to current source 22 and provides in AD conversion unit.Described a plurality of AD conversion unit has formed row Parallel ADC piece 15.
The counter 14 that each analog to digital converter of row Parallel ADC piece 15 comprises a comparator 13 and is used for counting comparing number of times, and have n position digital signal translation function (n is natural number).Comparator 13 relatively generated by digital to analog converter 19 (hereinafter, referred to as DAC) and the signal RAMP by reference line 23 inputs and by column signal line V0, V1 ... and from row signal line H0, H1 ... in the analog signal that obtains of pixel 12.
In addition, be used for to generate the timing control circuit 20 of internal clocking, the column scan circuit 17 that is used for the line-scan circuit 18 of control row addressing or line scanning and is used for control row addressing or column scan is arranged to the control circuit for the signal of order read pixel array 11.
In this embodiment, the number of the number of the number of horizontal output line 16, sensor circuit and output circuit is respectively n.Yet, can the individual horizontal output line of parallelization n * m (m is natural number), n * m sensor circuit and n * m output circuit, in order to increase its output speed.In some cases, can use n * m horizontal output line 16, n * m sensor circuit and n * 1 output circuit (m ≠ 1 and 1 is natural number), and can be with parallel-to-serial converter circuit or deserializer circuit arrangement between sensor circuit and output circuit.
Fig. 8 is the circuit diagram that illustrates according to the ios dhcp sample configuration IOS DHCP of the switch circuit units 24 in the solid-state imaging apparatus 2 among the second embodiment.
As shown in Figure 8, except switch circuit units 24 has simpler configuration than the switch circuit units 21 of the first embodiment shown in Figure 4 and the outside complementations control of carrying out switch-over control signals of commutation circuit 24, the basic configuration of switch circuit units 24, operation and effect are identical with the switch circuit units 21 of the first embodiment.
That is to say that each of switch circuit units 24 comprises switches N channel transistor 41 and 42.This switching N channel transistor 41 has the drain electrode that is connected with column signal line V2x (x be 0 or natural number), to grid and the source electrode of its input switch-over control signal a0, have the drain electrode that is connected with column signal line V2x+1 (x be 0 or natural number), input grid and the source electrode of the inversion signal of switch-over control signal a0 to it and switch N channel transistor 42.The source electrode that switches N channel transistor 41 and 42 is connected to the comparator 13 (seeing Fig. 7) of current source 22 (seeing Fig. 7) and row Parallel ADC piece 15, as public output.When with switch-over control signal a0 (for example, when address signal) being directly inputted to switch circuit units 24, a0 is corresponding with this switch-over control signal, and this switches each conducting or cut-off in N channel transistor 41 and 42, thereby switches this switch circuit units 24.Corresponding to a control signal, must be to switch one of N channel transistor 41 and 42 conducting and another cut-off.More specifically, according to control signal, must be, switch N channel transistor 41 conductings and switch 42 cut-offs of N channel transistor, perhaps switch 41 cut-offs of N channel transistor and switch 42 conductings of N channel transistor.
Fig. 9 is the block diagram that illustrates the Circnit Layout example when the least significant bit (LSB) that is provided to the row address signal row address decoding circuit, before the address decoder is set to the switch-over control signal of switch circuit units 24.In Fig. 9, only show the critical piece that takes out from Fig. 7.
As shown in Figure 9, during address decoder, owing to generated the inversion signal of row address signal, so control respectively N channel transistor 41 and N channel transistor 42 as row address signal and the inversion signal thereof of two control signals, so that the conducting of one of N channel transistor 41 and 42 and another cut-off.More specifically, according to row address signal and inversion signal thereof, 42 cut-offs of 41 conductings of N channel transistor and N channel transistor, perhaps 41 cut-offs of N channel transistor and 42 conductings of N channel transistor.Therefore, switch circuit units 24 does not need for the circuit (inverter among the first embodiment) that carries out complementary control switching in switch circuit units 24.
Obtain and the effect identical according to the solid-state imaging apparatus 1 of the first embodiment according to the solid-state imaging apparatus 2 of the second embodiment.In addition, except the configuration of switch circuit units 24 was simpler than the switch circuit units 21 among the first embodiment, the basic configuration of switch circuit units 24, operation and effect were identical with described switch circuit units 21.
In addition, owing to all use least significant bit (LSB) according to two switch circuit units 21 and 24 of the first and second embodiment, so in Circnit Layout, automatically determine necessary row according to selected row.
Figure 12 is the cross-sectional view that illustrates according to the video camera of the 3rd embodiment, and wherein this video camera comprises the solid-state imaging apparatus according to the first or second embodiment.According to the video camera of the 3rd embodiment be can capture video the video camera example.
Video camera according to this embodiment comprises solid- state imaging apparatus 1 or 2, optical system 210, fast door equipment 211, drive circuit 212 and signal processing circuit 213.
It should be appreciated by those skilled in the art, according to design requirement and other factors, can carry out various modifications, combination, sub-portfolio and change, as long as they are in claims or its equivalent scope.
Claims (10)
1. solid-state imaging apparatus comprises:
A plurality of pixels are converted to the signal of telecommunication with incident light quantity separately, and are disposed in a plurality of row, to go up in the row direction or to depart from neighbor at column direction;
A plurality of AD conversion unit, the analog signal conversion that will obtain from respective pixel separately is digital signal, and arranges along row are parallel;
A plurality of column signal lines are exported the analog signal of the pixel in each of a plurality of pixel columns, arrange along pixel column, and form by two adjacent column signal lines right; And
A plurality of switch circuit units are selected a column signal line of respective column holding wire centering separately,
Wherein said AD conversion unit is connected to the outlet side of described switch circuit units.
2. according to claim 1 solid-state imaging apparatus,
Wherein each switch circuit units is selected a column signal line of respective column holding wire centering, and does not select another column signal line.
3. according to claim 1 solid-state imaging apparatus also comprises:
The a plurality of current sources corresponding with the holding wire that is connected to switch circuit units,
And wherein, described AD conversion unit is corresponding with switch circuit units.
4. according to claim 1 solid-state imaging apparatus,
Least significant bit (LSB) line-scan circuit, decoding row address signal before that wherein is supplied to for control row addressing and line scanning is used as the switch-over control signal of switch circuit units.
5. according to claim 1 solid-state imaging apparatus,
Wherein each switch circuit units all comprises selection or does not select the right commutation circuit of respective column holding wire.
6. according to claim 5 solid-state imaging apparatus,
Wherein for alternately to select described selection or not select the right commutation circuit of respective column holding wire corresponding to the AD conversion unit of this switch circuit units.
7. according to claim 5 solid-state imaging apparatus,
Wherein be supplied to the switch-over control signal that least significant bit (LSB) for the row address signal line-scan circuit of the addressing of control row or line scanning, before the decoding is used as described selection or does not select one of right commutation circuit of respective column holding wire, and the inversion signal of described least significant bit (LSB) signal is used as the switch-over control signal of another commutation circuit.
8. according to claim 5 solid-state imaging apparatus also comprises:
The a plurality of current source circuits corresponding with the holding wire that is connected to switch circuit units,
And wherein, described AD conversion unit is corresponding with switch circuit units.
9. method that drives solid-state imaging apparatus, this solid-state imaging apparatus comprises: a plurality of pixels are converted to the signal of telecommunication with incident light quantity separately, and are disposed in a plurality of row, to go up in the row direction or to depart from neighbor at column direction; A plurality of AD conversion unit, the analog signal conversion that will obtain from respective pixel separately is digital signal, and arranges along row are parallel; A plurality of column signal lines are exported the analog signal of the pixel in each of a plurality of pixel columns, arrange along pixel column, and form by two adjacent column signal lines right; And a plurality of switch circuit units, select separately a column signal line of respective column holding wire centering,
Wherein said AD conversion unit is connected to the outlet side of described switch circuit units, and
Least significant bit (LSB) line-scan circuit, decoding row address signal before that is supplied to for control row addressing or line scanning is used as the switch-over control signal of described switch circuit units.
10. video camera comprises:
Solid-state imaging apparatus, it comprises:
A plurality of pixels are converted to the signal of telecommunication with incident light quantity separately, and are disposed in a plurality of row, to go up in the row direction or to depart from neighbor at column direction;
A plurality of AD conversion unit, the analog signal conversion that will obtain from respective pixel separately is digital signal, and arranges along row are parallel;
A plurality of column signal lines are exported the analog signal of the pixel in each of a plurality of pixel columns, arrange along this pixel column, and form by two adjacent column signal lines right; And
A plurality of switch circuit units are selected a column signal line of respective column holding wire centering separately, and
Wherein said AD conversion unit is connected to the outlet side of described switch circuit units.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP059022/06 | 2006-03-06 | ||
| JP2006059022A JP4959207B2 (en) | 2006-03-06 | 2006-03-06 | Solid-state imaging device |
Publications (2)
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| CN101035191A CN101035191A (en) | 2007-09-12 |
| CN101035191B true CN101035191B (en) | 2013-03-20 |
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| CN2007100856727A Expired - Fee Related CN101035191B (en) | 2006-03-06 | 2007-03-06 | Solid state image forming device, method of driving the same and camera |
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| US (1) | US7864237B2 (en) |
| JP (1) | JP4959207B2 (en) |
| KR (1) | KR101331365B1 (en) |
| CN (1) | CN101035191B (en) |
| TW (1) | TWI350102B (en) |
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| JP4107269B2 (en) * | 2004-02-23 | 2008-06-25 | ソニー株式会社 | Solid-state imaging device |
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| JP4386118B2 (en) * | 2007-08-31 | 2009-12-16 | ソニー株式会社 | Imaging circuit |
| TWI504256B (en) * | 2008-04-07 | 2015-10-11 | Sony Corp | Solid-state imaging device, signal processing method of solid-state imaging device, and electronic apparatus |
| JP5178458B2 (en) * | 2008-10-31 | 2013-04-10 | キヤノン株式会社 | Solid-state imaging device, imaging system, and driving method of solid-state imaging device |
| FR2939919A1 (en) * | 2008-12-16 | 2010-06-18 | New Imaging Technologies Sas | MATRIX SENSOR |
| JP5272860B2 (en) * | 2009-04-08 | 2013-08-28 | ソニー株式会社 | Solid-state imaging device and camera system |
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| JP5429547B2 (en) | 2009-10-02 | 2014-02-26 | ソニー株式会社 | Solid-state imaging device, imaging device, AD conversion method |
| US8817153B2 (en) * | 2011-07-25 | 2014-08-26 | Aptina Imaging Corporation | Column parallel readout image sensors with shared column analog-to-digital converter circuitry |
| JP6041500B2 (en) * | 2012-03-01 | 2016-12-07 | キヤノン株式会社 | Imaging device, imaging system, driving method of imaging device, and driving method of imaging system |
| JP6083137B2 (en) * | 2012-06-26 | 2017-02-22 | ソニー株式会社 | Control apparatus and control method |
| US9294703B2 (en) | 2012-12-03 | 2016-03-22 | Samsung Electronics Co., Ltd. | Image sensor including data transmission circuit having split bus segments |
| JP6045379B2 (en) * | 2013-02-08 | 2016-12-14 | オリンパス株式会社 | Imaging device |
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| WO2019092994A1 (en) * | 2017-11-10 | 2019-05-16 | Sony Semiconductor Solutions Corporation | Solid-state imaging apparatus |
| JP2019092143A (en) * | 2017-11-10 | 2019-06-13 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging device, imaging apparatus, and control method of solid-state imaging device |
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- 2007-03-02 TW TW096107262A patent/TWI350102B/en not_active IP Right Cessation
- 2007-03-05 KR KR1020070021454A patent/KR101331365B1/en not_active IP Right Cessation
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Also Published As
| Publication number | Publication date |
|---|---|
| KR20070091553A (en) | 2007-09-11 |
| US7864237B2 (en) | 2011-01-04 |
| JP4959207B2 (en) | 2012-06-20 |
| TWI350102B (en) | 2011-10-01 |
| JP2007243265A (en) | 2007-09-20 |
| CN101035191A (en) | 2007-09-12 |
| TW200746807A (en) | 2007-12-16 |
| US20080117321A1 (en) | 2008-05-22 |
| KR101331365B1 (en) | 2013-11-19 |
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