CN101026203A - Semiconductor nano structure and its preparing method - Google Patents
Semiconductor nano structure and its preparing method Download PDFInfo
- Publication number
- CN101026203A CN101026203A CNA2006100031804A CN200610003180A CN101026203A CN 101026203 A CN101026203 A CN 101026203A CN A2006100031804 A CNA2006100031804 A CN A2006100031804A CN 200610003180 A CN200610003180 A CN 200610003180A CN 101026203 A CN101026203 A CN 101026203A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- layer
- nanometer
- island
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
This invention relates to a semiconductor nm structure including: a substrate as a carrier of semiconductor devices, a semiconductor buffer layer formed on the substrate by an epitaxial growing technology to buffer the stress of the substrate and other layers, a template layer formed on the buffer layer by an epitaxial growing technology as a supporting template, a passivation layer formed on the template layer by surface passivation to adsorb atoms on a surface migration potential, an inducement layer formed on the passivation layer to promote form of a semiconductor nm island, an nm island layer formed on the inducement layer as an active agent of photoelectronic devices, a cover layer on the island layer for protecting it or providing carriers.
Description
Technical field
The present invention relates to semi-conducting material and device and preparation method thereof, be meant a kind of nanometer semiconductor structure and preparation method thereof especially.
Background technology
Nanometer semiconductor structure relates to following content: press the material branch, be III-V family semi-conducting material, comprise III-V family binary semiconductor material and ternary and the quaternary compound semiconductor material be made up of them; Divide by the system size, be nanoscale, belong to Jie's sight system, quantum regime research field.Comprise with metal-organic chemical vapor deposition equipment by the growing method branch, molecular beam epitaxy, atomic beam extension etc. is the superlattice growth technology of representative, the ultrathin film of the atom magnitude of promptly can growing, the growth technology of nanostructure and abrupt interface; Comprise with the chemical composition difference that by epitaxial material kind branch the energy gap different materials is the heteroepitaxy of representative.Then comprise photoelectric device and coulomb blockade devices such as light-emitting diode, laser diode, detector, electronic devices such as quantum memory spare by the device function branch.
The nanometer island is the small crystal structure of size in nanometer scale, and its characteristic feature is the localization of electron wave function and the quantization of power spectrum.The nanometer island structure has some very significant quantization effects, and it directly influences the various physical propertys on nanometer island, as electronic structure, and carrier transport properties and optical property etc.Therefore has very wide device application prospect.Aspect optical device, be mainly used in and make luminous tube, laser and detector etc.The electronic device aspect can be used for making single-electronic transistor, and memory and digital information transmission, computing unit etc. are expected to play an important role in quantum calculation.Nanometer island luminescent device has isolychn width, and threshold current is low, the advantage of good temp characteristic.By the same token, it is narrow that nanometer island detector has detection window, the advantage that detectivity is high.
The proposition of this notion of low dimension semiconductor material is just produced the zero dimension semi-conducting material soon up to the 1980s.Application study that it should be noted that at present up-to-date in the world nanometer island structure is especially transferred to the quantum information that very likely obtains some breakthrough at present rapidly and is handled up, but its nanometer island structure remains common nanometer island structure.In this field, multiple research method or technology path are also deposited, and any good scheme all might obtain some and break through, thereby form the technology path of main flow.
The method on people's growing nano island mainly contains at present:
(1) adopts modern ripe semiconductor integrated circuit technique, particularly photoetching process, make the nanometer island of nanometer scale.
(2) at various natural surfaces or manually make growing nano island on the substrate of figure, as low-angle surface, super step surface, high index surface, and the V-type groove, growth or on mask surface, select local growth or the like on the side of cleavage heterostructure.Because the energy of some location point is lower on these substrate surfaces, adsorbed atom trends towards being deposited on these somes during epitaxial growth, thereby forms the nanometer island.
(3) strain self-organizing growth method.When epitaxial film, there is a critical thickness L in epitaxy layer thickness, when epitaxy layer thickness does not surpass critical thickness, extension is the two dimensional surface growth, and along with soakage layer thickness increases, strain energy constantly accumulates, when soakage layer thickness reaches critical thickness, epitaxial process then by two dimensional surface growth changing into three-dimensional island growth, forms three-dimensional cluster, becomes the array on nanometer island.Other adopt methods such as surfactant in addition.
Adopt as above that there are some problems in method growing nano island, main has:
(1) photoetching process can produce many dislocations on surface, nanometer island.When dislocation existed, electronics and hole can be carried out non-radiative compound, thereby reduced the probability of radiation recombination, reduced the luminous efficiency on nanometer island; In like manner, the temperature characterisitic on nanometer island also can be affected.This also is disadvantageous to making electronic device.
(2) photoetching process also has complex process, and the shortcoming that cost is high can increase substantially the technology cost when lithographic line width need reduce, and technology is more complicated, causes decrease in yield.
(3) utilize the existence of surface crater to come the shortcoming on growing nano island to be: can not form on the substrate surface of various needs and the substrate surface pit is irrelevant nanometer island and array structure thereof, this makes its application have significant limitation.
(4) shortcoming of self-assembled nanometer island method is: because its growth mechanism has utilized the S-K growth pattern, the size on nanometer island can be restricted, and adjustable extent is less; In addition, must adopt real-time monitoring, can only in molecular beam epitaxy (MBE) growing method, adopt at present.And can not be used for other growing methods, and as the metal-organic chemical vapor deposition equipment method (MOCVD) that adopts in the industrial production, hot wall epitaxy, hydride vapour deposition process (HVPE) etc.
Summary of the invention
The purpose of this invention is to provide a kind of nanometer semiconductor structure and preparation method thereof, it adopts the big high density nanometer island of easy process growth size adjustable extent.And this method is applicable to present various growth technology at present, and is not subjected to the restriction (pit that nanometer scale needn't be arranged) of substrate.The nanometer island that this method is made can be used to make the active layer of luminescent device and electricity device.Produce brightness height, good temp characteristic, luminescent device that cut-in voltage is low, and the electronic device of a new generation.
Technical scheme of the present invention is:
A kind of nanometer semiconductor structure of the present invention is characterized in that, this structure comprises:
One substrate is as the supporting body of semiconductor device;
The semiconductor resilient coating, this semiconductor buffer layer is formed on the substrate by growth technology, plays the effect of stress between buffering substrate and other layers;
The semiconductor template layer, this semiconductor module flaggy is formed on the semiconductor buffer layer by growth technology, as support shuttering;
One passivation layer, this passivation layer is formed on the semiconductor module flaggy by surface passivation, plays and improves the effect of adatom in the surface migration potential barrier;
The semiconductor inducing layer, this semiconductor inducing layer is produced on the passivation layer, plays the effect that promotes that the semiconductor nano island forms;
Semiconductor nanometer island layer, this semiconductor nano island layer is produced on the semiconductor inducing layer, as the active layer of opto-electronic device;
Semiconductor block layer, this semiconductor block layer is produced on the layer of semiconductor nano island, plays protection semiconductor nano island layer, and the effect of charge carrier perhaps is provided.
Wherein the material of said substrate is: gallium nitride, aluminium nitride, indium nitride monocrystal material, indium phosphide, developing zinc oxide composite material on growing aluminum nitride composite material, the silicon on grow on GaAs material, sapphire material, silicon single crystal material, spinel, carbofrax material, zinc oxide material, the silicon alumina composite material, the silicon.
Wherein the thickness of semiconductor buffer layer is the 10-500 nanometer, and growth temperature is 300 ℃-800 ℃.
Semiconductor inducing layer wherein, 300 ℃-800 ℃ of its growth temperatures, thickness is the 1-300 nanometer.
Wherein said semiconductor nano island layer is a single or multiple lift, each layer thickness be 1 nanometer to 300 nanometers, the material between the different layers is identical or inequality.
The manufacture method of a kind of nanometer semiconductor structure of the present invention is characterized in that, comprises the steps:
Step 1: on substrate, form the semiconductor resilient coating, play the effect of stress between buffering substrate and other layers by growth technology;
Step 2: on semiconductor buffer layer, form the semiconductor template layer, as support shuttering by growth technology.
Step 3: the semiconductor die layer is carried out passivation, on the semiconductor die laminar surface, form a passivation layer, play and improve the effect of adatom in the surface migration potential barrier;
Step 4: on passivation layer, make the semiconductor inducing layer, play the effect that promotes that the semiconductor nano island forms;
Step 5: on the semiconductor inducing layer, make semiconductor nano island layer, as the active layer of opto-electronic device;
Step 6: on the layer of semiconductor nano island, make semiconductor block layer, play protection semiconductor nano island layer, the effect of charge carrier perhaps is provided by growth technology.
Wherein the material of said substrate is: gallium nitride, aluminium nitride, indium nitride monocrystal material, indium phosphide, developing zinc oxide composite material on growing aluminum nitride composite material, the silicon on grow on GaAs material, sapphire material, silicon single crystal material, spinel, carbofrax material, zinc oxide material, the silicon alumina composite material, the silicon.
Wherein the thickness of semiconductor buffer layer is the 10-100 nanometer, and growth temperature is 300 ℃-800 ℃.
Wherein semiconductor inducing layer growth temperature is 300 ℃-800 ℃, and thickness is the 1-300 nanometer.
Wherein said semiconductor nano island layer is a single or multiple lift, each layer thickness be 1 nanometer to 300 nanometers, the material between the different layers is identical or inequality.
Description of drawings
In order to further specify feature of the present invention and effect, the present invention is described further below in conjunction with drawings and Examples, wherein:
Fig. 1 is the atomic force microscope vertical view of indium gallium nitrogen (InGaN) nanometer island sample;
Fig. 2 is the photoluminescence spectra figure on indium gallium nitrogen (InGaN) nanometer island;
Fig. 3 is the sectional view according to the III group-III nitride nanometer island light-emitting diode of first embodiment of the invention.
Embodiment
See also shown in Figure 3, a kind of nanometer semiconductor structure of the present invention, this structure comprises:
One substrate 1, supporting body as semiconductor device, the material of said substrate 1 is: gallium nitride, aluminium nitride, indium nitride monocrystal material, indium phosphide, developing zinc oxide composite material on growing aluminum nitride composite material, the silicon on grow on GaAs material, sapphire material, silicon single crystal material, spinel, carbofrax material, zinc oxide material, the silicon alumina composite material, the silicon;
Semiconductor resilient coating 2, this semiconductor buffer layer 2 is formed on the substrate 1 by growth technology, plays the effect of stress between buffering substrate 1 and other layers, and the thickness of this semiconductor buffer layer 2 is the 10-500 nanometer, and growth temperature is 300 ℃-800 ℃;
Semiconductor template layer 3, this semiconductor module flaggy 3 is formed on the semiconductor buffer layer 2, as support shuttering by growth technology;
One passivation layer 4, this passivation layer 4 is formed on the semiconductor module flaggy 3 by surface passivation, plays and improves the effect of adatom in the surface migration potential barrier;
Semiconductor nanometer island layer 6, this semiconductor nano island layer 6 is produced on the semiconductor inducing layer 5, active layer as opto-electronic device, this semiconductor inducing layer 5,300 ℃-800 ℃ of its growth temperatures, thickness is the 1-300 nanometer, this semiconductor nano island layer 6 is a single or multiple lift, each layer thickness be 1 nanometer to 300 nanometers, the material between the different layers is identical or inequality;
Please consult shown in Figure 1ly again, the manufacture method of a kind of nanometer semiconductor structure of the present invention comprises the steps:
Step 1: on substrate 1, form semiconductor resilient coating 2 by growth technology, play the effect of stress between buffering substrate 1 and other layers, the material of said substrate 1 is: gallium nitride, aluminium nitride, indium nitride monocrystal material, indium phosphide, developing zinc oxide composite material on growing aluminum nitride composite material, the silicon on grow on GaAs material, sapphire material, silicon single crystal material, spinel, carbofrax material, zinc oxide material, the silicon alumina composite material, the silicon; The thickness of this semiconductor buffer layer 2 is the 10-100 nanometer, and growth temperature is 300 ℃-800 ℃;
Step 2: on semiconductor buffer layer 2, form semiconductor template layer 3, as support shuttering by growth technology.
Step 3: semiconductor die layer 3 is carried out passivation, on semiconductor module flaggy 3 surfaces, form a passivation layer 4, play and improve the effect of adatom in the surface migration potential barrier;
Step 4: on passivation layer 4, make semiconductor inducing layer 5, play the effect that promotes that the semiconductor nano island forms, 300 ℃-800 ℃ of these semiconductor inducing layer 5 growth temperatures, thickness is the 1-300 nanometer;
Step 5: make semiconductor nano island layer 6 on semiconductor inducing layer 5, as the active layer of opto-electronic device, this semiconductor nano island layer 6 is a single or multiple lift, each layer thickness be 1 nanometer to 300 nanometers, the material between the different layers is identical or inequality;
Step 6: on semiconductor nano island layer 6, make semiconductor block layer 7, play protection semiconductor nano island layer 6, the effect of charge carrier perhaps is provided by growth technology.
Embodiment
In order to realize purpose of the present invention, adopted following method:
Known epitaxial growth pattern has three kinds at present: F-vdM (Frank-var derMerwe) pattern, V-M (Volmer-Webber) pattern, S-K (Stranski-Krastanov) pattern.Be two dimension or the three dimensional growth pattern dominates on earth in the epitaxial process, depend on the surface energy between substrate, interface and the epitaxial loayer.When epi-layer surface can and the interface energy summation greater than substrate surface can the time, V-W then takes place to grow, i.e. island growth is so can form the nanometer island.The purpose of passivated substrate surface is exactly to reduce the surface energy of substrate surface.The nanometer island that is deposited to the ground floor nano-scale on the substrate is as active layer, and utilize vertical coupled effect with it as adjusting layer, one or more layers nanometer island structure of regrowth in the above.
For meaning of the present invention better is described, below further explanation done in above mentioned vocabulary.
Said " heterogeneous " refers to two kinds of semi-conducting materials that composition is different.Both the most essential differences are energy gap differences, promptly in two kinds of semi-conducting materials, an energy difference are arranged between the energy at the bottom of the conduction band or between the energy between the top of valence band.
Said " passivation " implication is as follows: can be multiple passivating method.Can be the gas passivation, as adopting hydrogen, oxygen carries out passivation to the surface.Also can be liquid, solid passivation, as various sulfide, oxide or the like.As long as can effectively fill the dangling bonds of substrate surface, the transition potential barrier that improves the surface adsorption atom gets final product.
Said " list or plural layers " implication is as follows: single thin film is meant film or the nanometer island that one deck is all different with both sides, interface material.Plural layers then are index layer film or nanometer island structure, and every layer is made of different materials.
We utilize this method indium gallium nitrogen (InGaN) nanometer island of having grown.Be illustrated in figure 1 as the atomic force microscope vertical view of this sample, as seen from the figure, formed the nanometer island of nanometer scale.Because these spot sizes are nanometer scale, so can form quantum limitation effect.Fig. 2 is the photoluminescence spectra figure on this nanometer island.Give among Fig. 2 under the isometric growth condition, growth phase with the luminescence generated by light spectrogram of the individual layer InGaN film of time as a comparison.Can find that by contrast the luminous efficiency of nanometer island sample is much higher.
Embodiment: III group-III nitride nanometer island light-emitting diode
Fig. 3 represents the sectional view according to the III group-III nitride nanometer island light-emitting diode of first embodiment of the invention.The preparation of this structure may further comprise the steps:
Step 1: select substrate 1, the needed semi-conducting material of epitaxial growth on this substrate 1; For example adopt (0001) surface sapphire (C-Al2O3) to make substrate 1; Epitaxial growth one deck gallium nitride is as semiconductor buffer layer 2 on (0001) surface sapphire substrate, and the thickness of semiconductor buffer layer 2 is 10-50 nanometers, and growth temperature is 450 ℃-650 ℃; On semiconductor buffer layer 2, grow certain thickness n type gallium nitride as semiconductor module flaggy 3,950 ℃-1100 ℃ of growth temperatures, thickness is the 0.5-4 micron.
Step 2: epitaxially grown material surface is carried out passivation, be beneficial to the formation on nanometer island; Just semiconductor die layer 3 is carried out passivation, form one deck passivation layer 4 on the surface.Passivating method is that sample was at room temperature placed 12 hours in the oxygen atmosphere.
Step 3: on the low temperature gallium nitride nanometer island of growth one deck nano-scale on the surface after the passivation as semiconductor inducing layer 5.
Cover one or more layers indium gallium nitrogen (InGaN) nanometer island on the semiconductor inducing layer 5 that gallium nitride nanometer island constitutes, as semiconductor nano island layer 6, list of being grown or heterogeneous multi-layer nanometer island structure can be used as the active layer of optics or electronic device; Can be different materials between the different layers, for example A, the B that is indicated among Fig. 3, C represent different dissimilar materials layers respectively; Also can be same material between the different layers.For example the A layer that is indicated among Fig. 3 is identical with the C layer different with the B layer again, and the structure of concrete growth conditions and multilayer film is decided on designed structure.
Step 4: the P type gallium nitride of 0.1 to 3 micron of growth is as semiconductor block layer 7 on the layer 6 of semiconductor nano island.
Substrate 1 wherein is except that (0001) surface sapphire (C-Al2O3), also can adopt the sapphire of any one face to do substrate, perhaps gallium nitride (GaN) monocrystalline, silicon single crystal (Si), spinelle (MgAl2O4), carborundum (SiC), aluminium nitride (AlN), indium nitride (InN), zinc oxide (ZnO), various compound substrate of developing zinc oxide compound substrate (ZnO/Si) and AlN/SiC or the like on growing aluminum nitride compound substrate (AlN/Si), the silicon on growth aluminium oxide compound substrate (Al2O3/Si), the silicon on the silicon.In a word, as long as can make the III group-III nitride of extension on this substrate have preferable quality to can be used as the template on GaN nanometer island.Though extension can obtain same effect on multiple substrate, we think that to do substrate with (0001) surface sapphire at present better, and this substrate is compared with other substrates has cheapness, the advantage that is easy to obtain.
It is present best mode that the epitaxial growth method of aforementioned each material adopts the MOCVD method.
Passivation in aforementioned can be various effective passivating methods.Comprise various oxidants, sulfide, hydride.As long as can effectively fill the dangling bonds on surface, increase surface adsorption atomic transition potential barrier and get final product.
Semiconductor nano island layer 6 can be that individual layer can be a multilayer also in aforementioned, and the number of plies is not limit, and each layer thickness is that 1 nanometer is to 300 nanometers.
When being the active layer of device with such III group-III nitride nanometer island, the luminescent device of making will have high luminous efficiency, low cut-in voltage (threshold voltage), and good temperature characterisitic.
Table 1 is III group-III nitride nanometer island light-emitting diode growth structure of the present invention and growth conditions
Table 1
| Material | Thickness | Temperature | |
| Substrate 1 | Gallium nitride, aluminium nitride, the indium nitride monocrystal material, indium phosphide, GaAs material, sapphire material, silicon single crystal material, spinel, carbofrax material, zinc oxide material, the alumina composite material of growing on the silicon, growing aluminum nitride composite material on the silicon, developing zinc oxide composite material on the silicon. | 50 microns-1000 microns | |
| |
III-V family semi-conducting material | 10 nanometers-500 nanometer | 300-800 ℃ |
| Semiconductor module flaggy 3 | III-V family semi-conducting material | 0.5-10 microns of microns | 900-1300 ℃ |
| Passivation layer 4 | Oxide, hydride, sulfide | 0.5 nanometer-10 nanometer | 0-1000 ℃ |
| |
III-V family semi-conducting material | 1 nanometer-300 nanometer | 300-800 ℃ |
| Semiconductor nano island layer 6 | III-V family semi-conducting material | 1 nanometer-300 nanometer | 300-1300 ℃ |
| |
III-V family |
5 nanometers-10 micron | 300-1300 ℃ |
The present invention compares with technology in the past, and this invention has following meaning:
1) the nanometer island of this structure, the size amplitude of accommodation is larger, and density is high, can be applicable to different requirement on devices.
2) be applicable to all kinds of epitaxial growth equipments commonly used at present, such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition method (MOCVD), hydride vapour deposition process (HVPE), hot wall extension etc.
3) be applicable to all kinds of villages commonly used bottom material, for these materials, can carry out corresponding surface passivation, thereby reduce surface energy. That is to say and to adopt the grow nanometer island of each material system of this method.
Claims (10)
1. a nanometer semiconductor structure is characterized in that, this structure comprises:
One substrate is as the supporting body of semiconductor device;
The semiconductor resilient coating, this semiconductor buffer layer is formed on the substrate by growth technology, plays the effect of stress between buffering substrate and other layers;
The semiconductor template layer, this semiconductor module flaggy is formed on the semiconductor buffer layer by growth technology, as support shuttering;
One passivation layer, this passivation layer is formed on the semiconductor module flaggy by surface passivation, plays and improves the effect of adatom in the surface migration potential barrier;
The semiconductor inducing layer, this semiconductor inducing layer is produced on the passivation layer, plays the effect that promotes that the semiconductor nano island forms;
Semiconductor nanometer island layer, this semiconductor nano island layer is produced on the semiconductor inducing layer, as the active layer of opto-electronic device;
Semiconductor block layer, this semiconductor block layer is produced on the layer of semiconductor nano island, plays protection semiconductor nano island layer, and the effect of charge carrier perhaps is provided.
2. nanometer semiconductor structure according to claim 1, it is characterized in that, wherein the material of said substrate is: gallium nitride, aluminium nitride, indium nitride monocrystal material, indium phosphide, developing zinc oxide composite material on growing aluminum nitride composite material, the silicon on grow on GaAs material, sapphire material, silicon single crystal material, spinel, carbofrax material, zinc oxide material, the silicon alumina composite material, the silicon.
3. nanometer semiconductor structure according to claim 1 is characterized in that, wherein the thickness of semiconductor buffer layer is the 10-500 nanometer, and growth temperature is 300 ℃-800 ℃.
4. nanometer semiconductor structure according to claim 1 is characterized in that, semiconductor inducing layer wherein, and 300 ℃-800 ℃ of its growth temperatures, thickness is the 1-300 nanometer.
5. nanometer semiconductor structure according to claim 1 is characterized in that, wherein said semiconductor nano island layer is a single or multiple lift, each layer thickness be 1 nanometer to 300 nanometers, the material between the different layers is identical or inequality.
6. the manufacture method of a nanometer semiconductor structure is characterized in that, comprises the steps:
Step 1: on substrate, form the semiconductor resilient coating, play the effect of stress between buffering substrate and other layers by growth technology;
Step 2: on semiconductor buffer layer, form the semiconductor template layer, as support shuttering by growth technology;
Step 3: the semiconductor die layer is carried out passivation, on the semiconductor die laminar surface, form a passivation layer, play and improve the effect of adatom in the surface migration potential barrier;
Step 4: on passivation layer, make the semiconductor inducing layer, play the effect that promotes that the semiconductor nano island forms;
Step 5: on the semiconductor inducing layer, make semiconductor nano island layer, as the active layer of opto-electronic device;
Step 6: on the layer of semiconductor nano island, make semiconductor block layer, play protection semiconductor nano island layer, the effect of charge carrier perhaps is provided by growth technology.
7. nanometer semiconductor structure manufacture method according to claim 6, it is characterized in that, wherein the material of said substrate is: gallium nitride, aluminium nitride, indium nitride monocrystal material, indium phosphide, developing zinc oxide composite material on growing aluminum nitride composite material, the silicon on grow on GaAs material, sapphire material, silicon single crystal material, spinel, carbofrax material, zinc oxide material, the silicon alumina composite material, the silicon.
8. nanometer semiconductor structure manufacture method according to claim 6 is characterized in that, wherein the thickness of semiconductor buffer layer is the 10-100 nanometer, and growth temperature is 300 ℃-800 ℃.
9. nanometer semiconductor structure manufacture method according to claim 6 is characterized in that, wherein semiconductor inducing layer growth temperature is 300 ℃-800 ℃, and thickness is the 1-300 nanometer.
10. nanometer semiconductor structure manufacture method according to claim 6 is characterized in that, wherein said semiconductor nano island layer is a single or multiple lift, each layer thickness be 1 nanometer to 300 nanometers, the material between the different layers is identical or inequality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100031804A CN101026203A (en) | 2006-02-22 | 2006-02-22 | Semiconductor nano structure and its preparing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100031804A CN101026203A (en) | 2006-02-22 | 2006-02-22 | Semiconductor nano structure and its preparing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101026203A true CN101026203A (en) | 2007-08-29 |
Family
ID=38744273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100031804A Pending CN101026203A (en) | 2006-02-22 | 2006-02-22 | Semiconductor nano structure and its preparing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101026203A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258970A (en) * | 2012-09-19 | 2013-08-21 | 苏州大学 | Method for preparing core-shell organic/cadmium sulfide nanowire heterojunction arrays |
| CN103456602A (en) * | 2013-03-18 | 2013-12-18 | 深圳信息职业技术学院 | Method for preparing non-polar surface gallium nitride nanometer cone material |
-
2006
- 2006-02-22 CN CNA2006100031804A patent/CN101026203A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258970A (en) * | 2012-09-19 | 2013-08-21 | 苏州大学 | Method for preparing core-shell organic/cadmium sulfide nanowire heterojunction arrays |
| CN103456602A (en) * | 2013-03-18 | 2013-12-18 | 深圳信息职业技术学院 | Method for preparing non-polar surface gallium nitride nanometer cone material |
| CN103456602B (en) * | 2013-03-18 | 2016-12-07 | 深圳信息职业技术学院 | The preparation method of non-polar surface gallium nitride nanometer cone material |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI249246B (en) | Gallium nitride-based devices and manufacturing process | |
| EP2755227B1 (en) | Nitride semiconductor structure and method of preparing same | |
| US9478699B2 (en) | Nanoscale emitters with polarization grading | |
| US8803189B2 (en) | III-V compound semiconductor epitaxy using lateral overgrowth | |
| US8063549B2 (en) | Light-emitting diode element and method for fabricating the same | |
| CN105428482B (en) | A kind of LED epitaxial structure and production method | |
| JP2004524250A (en) | Gallium nitride materials and methods | |
| CN104518062B (en) | The method for manufacturing light emitting semiconductor device | |
| KR20110045056A (en) | Method of manufacturing group III nitride semiconductor light emitting device, group III nitride semiconductor light emitting device and lamp | |
| Nakamura et al. | Nanocontact heteroepitaxy of thin GaSb and AlGaSb films on Si substrates using ultrahigh-density nanodot seeds | |
| CN102244156A (en) | Epitaxial growth method of InGaN quantum dot and single photon source obtained thereby | |
| CN106848017B (en) | A kind of epitaxial wafer and its growing method of GaN base light emitting | |
| CN1414644A (en) | Manufacturing method of single/multiple layer hetero quntum point structure | |
| CN104412395B (en) | reduce or eliminate the nanotube defects in III-nitride structure | |
| CN103872204B (en) | A kind of p-type interposed layer with loop structure and growing method | |
| KR101274211B1 (en) | Semiconductor substrate, light emitting device employing the same and method for manufacturing the light emitting device | |
| CN101026203A (en) | Semiconductor nano structure and its preparing method | |
| TW201438270A (en) | Growth method for reducing defect density of gallium nitride | |
| CN110534626B (en) | Superlattice quantum dot structure and manufacturing method thereof | |
| CN211404521U (en) | Superlattice quantum dot structure | |
| US20210135050A1 (en) | Template substrate, electronic device, light emitting device, method of manufacturing template substrate, and method of manufacturing electronic device | |
| KR20070091901A (en) | Fabrication of high-quality group 3 nitride-based homoepitaxial substrate and its related light-emitting multistructures using the nanostructured layer | |
| US9231053B2 (en) | Light emitting diodes having zinc oxide fibers over silicon substrates | |
| CN212907772U (en) | Gallium nitride epitaxial chip | |
| CN212209534U (en) | Gallium nitride epitaxial chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |