CN101023614A - System and method for digital timing error correction in a communications system utilizing adaptive predistortion - Google Patents
System and method for digital timing error correction in a communications system utilizing adaptive predistortion Download PDFInfo
- Publication number
- CN101023614A CN101023614A CN 200580030275 CN200580030275A CN101023614A CN 101023614 A CN101023614 A CN 101023614A CN 200580030275 CN200580030275 CN 200580030275 CN 200580030275 A CN200580030275 A CN 200580030275A CN 101023614 A CN101023614 A CN 101023614A
- Authority
- CN
- China
- Prior art keywords
- cross
- timing error
- correct
- proofreaied
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
A system and method for rapidly correcting the time difference between two signals is disclosed. In particular, a system and method for very rapidly correcting timing errors to the very high degree of accuracy required for digital predistortion adaptation is disclosed. The method is a signal processing technique, which can be performed in either hardware or software, which employs a correlation computation. The correlation results are processed in a manner that enables very rapid and accurate estimation of the time difference between the two signals.
Description
Relevant application information
The application requires the U.S. Provisional Application sequence number NO.60/586 that proposed on July 9th, 2004,906 priority, and its whole disclosures are combined in this by reference.
Technical field
The present invention is relevant with wireless communication system and method.Especially, the present invention is relevant with cellular communications system and method, and more generally is that need to use the system of linearization technique to transmission amplifier relevant with those.
Background technology
Most of radio frequencies (RF) amplifier system presents non-linear.Nonlinear effect causes the distortion that is exaggerated signal, has reduced the performance of signal receiver, has produced the energy of the expectation wavelength band that exceeds system's operation, perhaps disturbs mutually with contiguous carrier frequency.These problems are particular importance in the cellular telephone system such such as GSM, UMTS, CDMA2000 and IS-95.
A kind of method that is reduced in the level of distortion of amplifier out generation is to allow amplifier operate in the more linearizing zone of its response.The shortcoming of this method is that amplifier operates in " compensation (backed-off) " pattern, and it means the energy of amplifier by wasting, and with the energy of efficient use in non-constant ground from power supply.Efficiency and heat dissipation are the key factors when selecting the employed equipment of cellular system.
Other more advanced methods that are used to reduce level of distortion are called as linearization technique.Two kinds of the most frequently used technology are feedforward linearized and digital pre-distortion (predistortion).
Digital pre-distortion technology has lot of advantages, yet is using digital pre-distortion to reduce owing to there is a known problem during distortion that the linearisation of amplifier system causes.Typically have " expectation " output signal of numeral in this type systematic, it is provided to amplifier system as an input.Simultaneously, also have " acquisition " signal of numeral, it is to take from actual amplifier output and transfer back to digital pre-distortion system.The purpose of digital pre-distortion system is that the difference between " acquisition " signal and " expectation " signal is minimized.Minimize be by use be commonly referred in the adaptive process masking amplifier and in the freq converting circuit related with it the time become and the time constant distortion realize.For self adaptation is carried out, must harmonize the in time very exactly input signal of expectation and the output signal of acquisition.Unfortunately, the time delay by the amplifier analog circuit is also all different for different amplifier units.Time delay also changes because of the amplifier variation of temperature, and also changes because of the aging of amplifier.
Because amplifier in the operating period time delay by amplifier can not know during fabrication, so digital pre-distortion system must be estimated timing offset and automatically proofread and correct it.The method that is used to carry out this class timing error estimation and proofreaies and correct is called as delay-locked loop, and it is the technology that the technical staff of radio modem design knows.But there are various defectives in the existing method that is exclusively used in the predistortion problem.At first, delay-locked loop is responsive to input power.Delay-locked loop gain is the function of power of the signal of " expectation " signal and " acquisition ".Therefore, be difficult to design following delay-locked loop, it can the needed low-down estimation error of digital pre-distortion system be restrained fast.Also have, delay-locked loop is responsive to the statistics of input signal.In multicarrier system, digital pre-distortion system and amplifier must can be supported more than one signal carrier, and the loop gain of delay-locked loop and capture range also depend on effective carrier number in the system.Have under the situation of many carrier waves at some, maybe when having two carrier frequencies of fully separating, the capture range of delay-locked loop may be very little and the timing error of all expections of " restriction " (pull in) reliably.In addition, need in delay-locked loop, carry out " compromise " inevitably at convergence time with between the noise in the constant time lag estimation that then takes place to restrain.For fully turning round, need many digital pre-distortion systems with the short as far as possible time.This has brought design limit for the accessible timing error estimated accuracy of utilizing delay locked loop to obtain.
The art methods that is used for the timing error estimation is applicable to the wireless receiver design, and wherein the timing error estimation for accuracy is not most important.In pre-distortion system, purpose is that the difference between feasible " expectation " and " acquisition " signal minimizes.Therefore, must minimize any difference between " expectation " and " acquisition " signal that causes owing to slight timing difference as much as possible.Compare the more urgent timing requirement of existence with common receiver system.
What therefore, need now is the improved system and method that is used for the timing error estimation and proofreaies and correct in the predistortion linear wireless communication system.
Summary of the invention
In first aspect, the invention provides the method that is used for carrying out the timing error correction in self-adapted pre-distortion linearisation communication system.This method comprises: reception comprises the input signal that is input to the discrete signal samples of communication system by, reception comprises the output signal of the discrete signal samples of the output that comes from this communication system, and the constant time lag between described input signal and the output signal is estimated as the mark of a sampling timing.This method comprises that further the constant time lag of using estimation proofreaies and correct the timing error between the input and output signal.
In the preferred embodiment of the method, the estimation time delay comprises the cross-correlation function that calculates between the input and output sampling and the position of definite cross-correlation function peak value.The cross-correlation calculation value disperses, and the position of definite cross-correlation function peak value comprises that the selected centrifugal pump that makes cross-correlation calculation approaches a polynomial function, and the maximum of definite polynomial function.The maximum of determining polynomial function preferably includes the evaluator function derivative and determines that derivative is 0 point.More specifically, the maximum of determining cross-correlation function preferably includes the peaked index value of determining cross-correlation calculation, determine N the value (N is an integer) in any side of maximum, 2N+1 centrifugal pump that makes that 2N rank multinomial is suitable for that cross-correlation calculation produces and evaluator derivative are 0 point.For example, if N equals 1, then multinomial is 2 times.In the same manner, odd multinomial and even multinomial can be used equally.Also have, the maximum of determining cross-correlation function can comprise the peaked index value of determining cross-correlation calculation equally, determine to be right after in the value of the N1 under the maximum and be right after N2 value (is integer at this N1 and N2) on maximum, N1+N2+1 centrifugal pump that makes that N1+N2 rank multinomial is suitable for that cross-correlation calculation produces and evaluator derivative are 0 point.Timing error is proofreaied and correct to preferably include with interpolating function and is handled one or more signals that input or output to eliminate estimated delay.More specifically, timing error is proofreaied and correct to preferably include with finite impulse response filter and is handled one or more signals that input or output.For example, interpolating function can be a windowing sinc function.
According on the other hand, the invention provides in self-adapted pre-distortion linearisation communication system and carry out timing error correction method, this method comprises: receive one and comprise the input signal that is input to the discrete signal samples of communication system from, receive an output signal that comprises the discrete signal samples of an output that comes from communication system, calculate the cross-correlation function between the input and output signal and start the delay-locked loop of using the cross-correlation calculation result.Use the relative timing of the output adjustment input and output signal of delay-locked loop.
In the preferred embodiment of the method, the start delay locked loop comprises that the setting that provides initial is to the numerically-controlled oscillator that uses the cross-correlation calculation result.The output of numerically-controlled oscillator is used to control interpolater, and interpolater receives and adjust one or more signals that input or output.Interpolater is preferably proofreaied and correct whole sampling timing skews of using index modification and is proofreaied and correct the mark timing slip that uses finite impulse response filter.Preferably use the setting of upgrading numerically-controlled oscillator through the cross-correlation calculation of filtering.
According on the other hand, the present invention proposes a kind of system that timing error is proofreaied and correct that carries out in self-adapted pre-distortion linearisation communication system.This system comprises: first input end receives from a digital input signals that is input to this communication system; Second input, reception comes from the digital output signal and the cross-correlation calculation functional block of the output of communication system, calculates the cross-correlation function between the input and output signal.This system further comprises cross-correlation peak value measuring ability piece, and the position and the constant time lag that are used for the peak value of definite cross-correlation function estimate that device is used for being determined by the position of cross-correlation function peak value the timing error of estimation.This system further comprises and is used for receiving and adjust the interpolater that one or more numerals input or output signal according to the timing error of being estimated.
At the preferred embodiment of the system that is used for the timing error correction, a summation block is coupled to the cross-correlation calculation functional block, with the output of the cross-correlation calculation functional block that adds up.Interpolater preferably includes a finite impulse response filter.For example, finite impulse response filter can be used windowing sinc function and carry out score interpolation (fractional interpolation) computing.In one embodiment, be used for system that timing error proofreaies and correct and can use numerically-controlled oscillator and the loop filter that the interpolater with delay-locked loop couples, and second the cross-correlation function piece that couples with cross-correlation function piece and loop filter, in this embodiment, the result of cross-correlation calculation is used to the initialization numerically-controlled oscillator, and the filtering of second cross-correlation function piece output is used to upgrade numerically-controlled oscillator.
Further feature of the present invention and aspect have been described in below " embodiment ".
Description of drawings
Fig. 1 is the schematic functional block of the self-adapted pre-distortion linearized amplifier system of timing error compensation used according to the invention.
Fig. 2 is according to the graphic representation of the preferred embodiment of the present invention for the quadratic polynomial match of the cross-correlation function that adopts in the timing error estimation.
Fig. 3 is the functional block diagram according to the timing error estimation according to the present invention and the system of elimination.
Fig. 4 is for the graphic representation of the fitting of a polynomial piecemeal of windowing sinc (x) function of employing in timing error is eliminated according to the present invention.
Fig. 5 is the functional block diagram of the timing error estimation in accordance with another embodiment of the present invention and the system of elimination.
Embodiment
The invention provides the system and method that in the communication system of using self-adapted pre-distortion, carries out digital timing error estimation and proofread and correct.In advantageous applications, the present invention can be combined in the adaptive digital pre-distortion linearized amplifier system, and the amplifier system of having improved also is provided, as shown in Figure 1.
As shown in Figure 1, adaptive digital pre-distortion linearized amplifier system comprises digital computer 16, and it is for assessing to the digitized sampling of the input of amplifier system 13 and in the corresponding outputs of changing amplifier system after 14 down.Amplifier system 13 can comprise and is used for the freq converting circuit of figure signal to carrier frequency, the amplifying stage that is used to reduce the filter circuit of out-of-band energy and comprises power amplifier, and its structure is well known to those skilled in the art.One or more in these grades have introduced distortion.Digitized output signal obtains from A/D converter 15.If input signal is an analog signal, then can obtain the used digital input signal of computer 16 from A/D converter, perhaps input signal can offer amplifier system and is converted to analog signal and amplifies for amplifier system by using D/A 12 with digital form.
By carry out numerical calculation on digital input signals and digital output signal, digital computer can apply control signals to the predistortion circuit 11 of separation, and described predistortion circuit is applied to distortion on the digital input signals of amplifier system.After being converted to analog signal, the signal that has applied distortion is applied on the amplifier system 13.The purposes of predistortion is to make the input signal distortion, so that the nonlinear transmission characteristic of its compensated amplifier.
The purpose of predistortion circuit design is to make that the residual distortion level that keeps is very low in the output of amplifier system.In order to reach this purpose, digital computer is digitized representations input signal and output signal very accurately.And two signals must very accurately be aimed in time.Signal because being the paraphase amplifier system, digital computer how to change output signal, so must very accurately be aimed in time with respect to input signal.
In a preferred embodiment of the invention, use cross-correlation to analyze the input and output digital signal.Constant time lag between the position of the output peak value by checking cross-correlation function, two signals can be determined to the accuracy of a sampling.The present invention by use polynomial function in the peak value of cross-correlation function output with and neighbouring sample, improved the accuracy of constant time lag estimation.By using differentiate, the accuracy of constant time lag can be improved to much smaller than single sampling.
In a preferred embodiment, proofread and correct the constant time lag of using the above-mentioned steps estimation with interpolation filter.Digitlization output signal from amplifier system is transmitted through interpolation filter.The output of interpolation filter is the digitlization output of amplifier system, and it has effectively zero constant time lag with respect to digital input signal.In this embodiment, the effect of constant time lag estimation device and interpolation filter is to eliminate by amplifier system to be incorporated into all delays in the signal.
The delay of eliminating through amplifier system is important, because be because the distortion effect in the amplifier system causes by the tangible any signal change that becomes of the input and output digitized signal in the comparative figures processor.In addition, change as the delay that causes because of aging effect or temperature effect by the constant time lag of amplifier is tracked.The advantage of system and method for the present invention is, directly calculates the feedback loop that constant time lag rather than use converge on the constant time lag result of expectation.The shortcoming of feedback loop methods is its level and power spectrum sensitivity to the digitized signal input.Be difficult to design a kind of for all input power spectrum that run between the described linearized amplifier system operation operating period can both the operation of robust ground constant time lag estimator and corrective system.In addition, under all input signal situations, do not know how long feedback loop will converge to correct result.Method of the present invention has been eliminated all these type of considerations and has been caused the design of reliable more and robust.
The detailed implementation of timing error correction system and method will be described below.Calculate two timing errors between the digitized signal according to the estimation of the cross-correlation function between two signals.Such calculating is at " Digital Signal Processing:Principles; Algorithms andApplications ", the third edition, Johu G.Proakis and Dimitris G.Manolakis, Prentice Hall, in New Jersey one book description is arranged, it is combined in this by reference.Equation (1) is described cross-correlation calculation.I and O are vectors, and they have comprised the input and output digitized sampling that produces with the systematic sampling rate.LAGS be carry out cross-correlation based on the number of hysteresis (lag); This is a design parameter and the maximum constant time lag that should be not less than the expection of process amplifier system.
Equation (1) has been described the plural form of cross-correlation calculation, but the known real form can be used for real-valued input and output signal.In addition, equation (2) combines the real part and the imaginary part of the plural form output of the cross-correlation function described in the equation (1) incoherently.If do not expect the phase place rotation, then can carry out the combination of dry form mutually for real part and imaginary part.Know that equally equation (1) described a kind of special expression mode of cross-correlation, and some other expression way of cross-correlation is fit to equally.
Constant time lag in whole-sample numerical value is the peaked index i of equation (1).In preferred way of the present invention, further improve initial timing error estimation.This process at first finds the maximum of cross-correlation function, then writes down the maximum of cross-correlation and N value of maximum either side.Next stage is to fit a polynomial of order 2 n to a resulting 2N+1 data point.The ensuing stage is to be the position that 0 point removes to seek multinomial turning point (turning point) by seeking its derivative.Equivalently, the odd multinomial is the same with the even multinomial can use.More generally, this process can comprise the peaked index value of determining cross-correlation calculation, determine to be right after in the value of the N1 under the maximum and be right after N2 value on maximum, here N1 and N2 are integers, with a N1+N2 rank fitting of a polynomial to N1+N2+1 centrifugal pump of described cross-correlation calculation and to calculate this polynomial derivative be 0 point.Be appreciated that N1 and N2 can be that equate or unequal in the above.
As an example, describe above process in more detail, wherein N is selected as equaling 1; In this case, multinomial is second order or secondary.The peak value of cross-correlation estimation is provided by equation (1), uses y
2Expression.Use y
1And y
3Represent two adjacent samples.This is for example middle explanation in Fig. 2.Note, the timing value on the X-axis elect as-1,0 and+1.These values and will understand just for convenience, and any set point on the X-axis can be with (for example 1,2,3 or-0.5,0,0.5).In order to obtain the estimation of improved constant time lag, the step below carrying out:
1. multinomial is y=ax
2The form of+bx+c:
2. when x=-1, y
1=a-b+c
3. when x=0, y
2=c
4. when x=1, y
3=a+b+c
5. use 3,2a=y
1+ y
3-2y
2
6. use 3,2b=y
3-y
1
7.1 middle multinomial is 2ax+b about the first order derivative of x
8. turning point is at X
TP=-b/2a=1/2 (y
1-y
3)/(y
1+ y
3-2y
2)
This program is presented below:
Peak in the p=cross-correlation
·y
2＝E
IO[p]
·y
1＝E
IO[p-1]
·y
3＝E
IO[p+1]
Fractional_error (fractional error)=0.5* (y1-y3)/(y1+y3-2y2)
·P＝P+fractional_error；
TimingError (timing error)=LAGS+1-P
In case finished initial timing estimate, then upgraded the timing error filter.
First embodiment of digital timing error estimation of the present invention and correcting circuit is shown in Fig. 3.Should be appreciated that, can exist with the form of example, in hardware, form of software or software and hardware combining in the functional block shown in this figure.These functional blocks have constituted the part of digital computer 16 among Fig. 1.
The cross-correlation calculation of top equation (1) is to carry out in the functional block 23 of Fig. 3.The input of this functional block is the numeral input 21 of linearized amplifier system and from the digitlization output 22 of amplifier system.Digitlization output from amplifier system is exported corresponding to the digitlization of A/D converter among Fig. 1 15.Summation block 24 is finished the noncoherent accumulation of proofreading and correct output.In addition, should understand summation block 24 can be used to the to add up continuous output of cross-correlation unit 23, improve the accuracy of estimation by the noise average treatment of knowing.
Functional block 25 is calculated the peak value of search, and it provides 2N+1 to output to functional block 26.Functional block 26 is carried out the timing error estimation of a mark that is accurate to sample.Represented in the described in the above calculation procedure 8 one use N=1 (under the situation of secondary) by functional block 26 practiced example calculation.At last, whole-sample and part sampling timing postpone to be passed to interpolator block 27 from functional block 26.The output 28 of interpolator block is aimed in time with numeral input 21.
In this embodiment, an interpolation filter is preferably used for proofreading and correct timing error.Timing error is updated periodically so that follow the tracks of the time Yanzhong and the aging drift relevant with temperature of process amplifier system.The method has reduced the computation burden of digital computer, and if the sample rate of input signal and A/D, D/A converter known be to equate then be the solution of a robust.In this case, constant time lag is a constant value, as mentioned above, has prevented the long term drift in the simulated assembly.
If the sample rate of A/D and D/A converter is unequal, for example, if there is very little frequency error between sample rate, the constant time lag estimated value will not be constant and need to estimate again that constantly (this situation can be overcome by second embodiment that discusses below so.)
In this embodiment, can use the interpolation filter of Farrow type, described in hereinafter: " A Continuously Variable Digital Delay Element ", C.W.Farrow; Circuits andSystems, 1988, IEEE International Symposium, June 7-9,1988, Pages 2641-2645, Vol.3 is combined in this with its disclosure by reference, all can use although know any interpolation filter.In this case, fractional sampling more regularly filter carry out the correction of timing of any positive fractional part of sampling.Though know the negative fractional part that also can use by sampling, the two comes correcting interpolated filter perhaps positive fractional part and negative fractional part.The whole-sample timing slip is proofreaied and correct by using index modification (indexing modification), and index modification is that the technical staff of digital processing field knows.The remainder of delay sampling utilizes finite impulse response (FIR) (FIR) filter and is inserted into, and the tap-weights of FIR filter is approximately equal to the low pass filter by sinc (x) function interpolation.
When constant time lag estimation device 26 changes the fractional part of constant time lag, all recomputate the FIR tap-weights.This tap-weights is that polynomial approximation obtains according to carrying out piecemeal to suitable total filter response.This principle is seen shown in Figure 4.Here it is is generally used for calculating the Farrow method of impulse response taps.Use the polynomial approximation value by the actual interpolater of Farrow structure and upgraded tap continuously.See " A Continuously Variable Digital DelayElement ", C.W.Farrow; Circuits and Sysrem, 1988 IEEE InternationalSymposium, June 7-9,1988, Pages 2641-2645, Vol.3.The realization of interpolater can be different, but preferably use the principle of polynomial approximation piecemeal at this, to save the digital computer computing cost.
Then, referring to Fig. 5, second embodiment of digital timing error correcting circuit will be described.Can recognize that in this embodiment the many problems that interrelate with the delay-locked loop method of timing error correction are relevant with the initial convergence of feedback loop.In case reached convergence, can alleviate many design problems of above affirmation by selecting a low-down loop bandwidth.Though low loop bandwidth is considered to undesirable in other application, the shortcoming of low loop bandwidth can not be applied under the linearized amplifier system situation, because do not need to overcome independent frequency benchmark and Doppler shift problem.But problem of initial convergence remains the main difficulty of delay lock method, and it is overcome in the present invention.
By checking the step 8 of above-mentioned first embodiment, can understand the denominator of division is set at 1 calculating that has reduced delay-locked loop.See " Spread SpectrumCommunications Handbook ", M.K.Simon, J.K.Omura, R.A.Scholtz, B.K.Levitt, McGraw-Hill Professional, 2001, ISBN:0071382152, it openly is combined in this for your guidance.Therefore, using the calculating of step 8 to obtain initial point-device constant time lag estimated value is a very useful step.Thereafter, the time delay variation of following the tracks of aging slowly and temperature correlation can be finished by the delay-locked loop of very low loop bandwidth.
By adopting well-known numerically-controlled oscillator (NCO) method, for example, at LarsErup, Floyd M.Gardner and Robert A.Harris, described in " Interpolation in DigitalModems-Part II:Implementation and Performance; IEEE Transactionson Communications; Vol.41; no.6; June 1993; PP.998-1108 " literary composition, it openly is combined in this for your guidance, and the present invention can be used to provide an initial constant time lag valuation that has improved.This initial valuation is used for initialization NCO 311, and along the interpolation filter 37 of 312 lines.The morning that functional block 38 by Fig. 5 calculates delay-locked loop is relevant with evening, and early proofreaies and correct difference between being correlated with evening (corresponding to the Y of step 8 among first embodiment
1And Y
3) by loop filter 39 eliminations.The output 310 of loop filter is accumulated among the NCO 311, and the initial value of the output setting of functional block 36 is arranged on the NCO 311.The program of stating among above-mentioned first embodiment has been followed in functional block 33,34,35 and 36 output.
To each iteration, the accumulated value among the NCO upgrades according to following equation:
NCO_ACC(T)＝NCO_ACC(T-1)-LOOP_FILTER_OUTPUT (3)
Whole-sample postpones to use following equation (4) to calculate in NCO 311.It has adopted the Erup at Lars, Floyd M.Gardner and Robert A.Harris, the principle of summarizing in " Interpolation in Digital Modems-Part II:Implementation andPerformance; IEEE Transactions on Communications; Vol.41; no.6, Tune1993, PP.998-1108 " literary composition.
WHOLE_TIMING_DELAY(T)＝floor(NCO_ACC(T)) (4)
Fractional sampling postpones to use following equation (5) to calculate in NCO.It has also used the Erup at Lars, Floyd M.Gardner and Robert A, Harris, the principle of summarizing in " Interpolation in Digital Modems-Part II:Implementation andPerformance; IEEE Transactions on Communications, Vol.41, no.6; Tune1993, PP.998-1108 " literary composition.
FRACTIONAL_TIMING_DELAY(T)＝NCO_ACC(T)-WHOLE_TIMING_DELAY (5)
The whole-sample and the fractional sampling timing slip that upgrade are provided for interpolater 37 along line 313.Proofread and correct the whole-sample timing slip by the index modification of using the digital signal processing technique field personnel to know.The remainder of sampling delay preferably utilizes finite impulse response (FIR) (FIR) filter and is inserted into, and the tap-weights that the FIR filter has is approximately equal to the low pass filter that uses sinc (x) function interpolation, and this is well known to those skilled in the art.
Therefore system and method for the present invention provides in the mode of the power that can stand each signal and has estimated two timing errors between the similar signal fast; Stand the power spectral density of these signals; Have and obtain the good required scheduled time of estimation; " once by (one-shot) " estimation of timing error is provided; The clearly estimation (at second, or in any desired unit) of timing error is provided; Enough accurately calculate to carry out the predistortion self adaptation.
Although described concrete specific embodiment, these should not be regarded as actual restriction, because as skilled in the art to understand, utilize instruction of the present invention that various modifications can be provided.
Claims (21)
1. one kind is used for carrying out the method that timing error is proofreaied and correct in self-adapted pre-distortion linearisation communication system, comprising:
Receive an input signal that comprises discrete signal samples from input to this communication system;
Receive an output signal that comprises from the discrete signal samples of this communication system output;
With the constant time lag between the described input and output signal estimate sampling timing mark and
The constant time lag that use is estimated is proofreaied and correct the timing error between the described input and output signal.
2. described in claim 1, be used for the method that timing error is proofreaied and correct, wherein, comprise the peak that calculates the cross-correlation function between the described input and output sampling and determine cross-correlation function during the estimation fixed response time.
3. be used for the method that timing error is proofreaied and correct described in claim 2, wherein, the cross-correlation calculation value disperses, and determines that wherein the position of cross-correlation function peak value comprises the centrifugal pump approximating polynomial function that makes selected cross-correlation calculation.
4. described in claim 3, be used for the method that timing error is proofreaied and correct, wherein, determine that the position of cross-correlation function peak value further comprises the maximum of determining polynomial function.
5. described in claim 4, be used for the method that timing error is proofreaied and correct, wherein, determine that the maximum of polynomial function comprises the derivative that calculates this polynomial function and determines that derivative is 0 point.
6. described in claim 2, be used for the method that timing error is proofreaied and correct, wherein, the maximum of determining cross-correlation function comprises the peaked index value of determining that cross-correlation function calculates, determine N value in any side of maximum, wherein N is an integer, and 2N+1 centrifugal pump that makes that 2N rank fitting of a polynomial produces to cross-correlation calculation and evaluator derivative are 0 point.
7. described in claim 6, be used for the method that timing error is proofreaied and correct, wherein N be 1 and multinomial be secondary.
8. be used for the method that timing error is proofreaied and correct described in claim 1, wherein, timing error is proofreaied and correct and is comprised with interpolating function and act on one or more inputing or outputing on the signal, to eliminate the delay of estimation.
9. be used for the method that timing error is proofreaied and correct described in claim 8, wherein, timing error is proofreaied and correct and is comprised with the finite impulse response (FIR) interpolation filter and act on one or more inputing or outputing on the signal.
10. be used for the method that timing error is proofreaied and correct described in claim 8, wherein, interpolating function is a windowing sinc function.
11. in self-adapted pre-distortion linearisation communication system, be used for the method that timing error is proofreaied and correct, comprise:
Receive an input signal that comprises the discrete signal samples from the input to the communication system;
Receive an output signal that comprises from the discrete signal samples of the output of communication system;
The cross-correlation function of calculating between described input and output signal;
Start a delay-locked loop of using described cross-correlation calculation result; With
Use the output of described delay-locked loop to adjust the relative timing of described input and output signal.
12. be used for the method that timing error is proofreaied and correct described in claim 11, wherein, the delay-locked loop that starts the described cross-correlation calculation result of application comprises provides initial setting to the numerically-controlled oscillator that uses described cross-correlation calculation result.
13. described in claim 12, be used for the method that timing error is proofreaied and correct, wherein, the relative timing of adjusting described input and output signal comprises that the output of using described numerically-controlled oscillator removes to control interpolater, and described interpolater receives and adjust one or more signals that input or output.
14. be used for the method that timing error is proofreaied and correct described in claim 13, wherein, described interpolater is proofreaied and correct whole-sample timing slip that uses index modification and the mark timing slip that uses finite impulse response filter.
15. described in claim 12, be used for the method that timing error is proofreaied and correct, further comprise and use the setting of upgrading numerically-controlled oscillator through the cross-correlation calculation of filtering.
16. one kind is used for carrying out the system that timing error is proofreaied and correct in self-adapted pre-distortion linearisation communication system, comprises:
First input end receives the digital input signals from an input to this communication system;
Second input receives the digital output signal from the output of communication system;
The cross-correlation calculation functional block is calculated the cross-correlation function between the described input and output signal;
Cross-correlation peak value measuring ability piece is used for determining the position of the peak value of cross-correlation function;
Constant time lag estimation device is used for determining the timing error estimated by the position of the peak value of described cross-correlation function; And
Interpolater according to described estimation timing error, receives and adjusts one or more numerals and input or output signal.
17. as being used for the system that timing error is proofreaied and correct as described in the claim 16, further comprise the summation block that is coupled to the cross-correlation calculation functional block, the output of the described cross-correlation calculation functional block that is used to add up.
18. be used for the system that timing error is proofreaied and correct as described in claim 16, wherein said interpolater comprises finite impulse response filter.
19. be used for the system that timing error is proofreaied and correct as described in claim 18, wherein said finite impulse response filter is used windowing sinc function and is carried out the score interpolation computing.
20. as described in claim 16, be used for the system that timing error is proofreaied and correct, further comprise numerically-controlled oscillator and loop filter, in the delay-locked loop configuration, be couple to described interpolater.
21. as described in claim 20, be used for the system that timing error is proofreaied and correct, further comprise the second cross-correlation function piece that is couple to described cross-correlation function piece and loop filter, the result of wherein said cross-correlation calculation is used to start described numerically-controlled oscillator, and the filtering of described second cross-correlation function piece output is used to upgrade described numerically-controlled oscillator.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US58690604P | 2004-07-09 | 2004-07-09 | |
| US60/586,906 | 2004-07-09 | ||
| US11/175,509 | 2005-07-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101023614A true CN101023614A (en) | 2007-08-22 |
Family
ID=38710455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200580030275 Pending CN101023614A (en) | 2004-07-09 | 2005-07-08 | System and method for digital timing error correction in a communications system utilizing adaptive predistortion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101023614A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102668383A (en) * | 2009-07-30 | 2012-09-12 | 电信教育集团(国家高等电信学校) | Correction of analog defects in parallel analog-to-digital converters, in particular for multi-standard, software-defined radio, and/or cognitive radio use |
| CN102984099A (en) * | 2012-11-23 | 2013-03-20 | 陕西理工学院 | Algorithm for digital predistortion fraction time delay estimation and signal alignment and achievement thereof |
| CN104320095A (en) * | 2014-10-23 | 2015-01-28 | 清华大学 | Method and device for decreasing ADC (analog to digital converter) sampling rate in digital pre-distortion |
| CN104123267B (en) * | 2014-07-21 | 2017-02-15 | 电子科技大学 | High-precision fine synchronization device and method |
| CN107171645A (en) * | 2012-03-04 | 2017-09-15 | 匡坦斯公司 | Power amplifier system and delay calibration method |
| CN109347612A (en) * | 2018-11-01 | 2019-02-15 | 四川安迪科技实业有限公司 | A kind of timing offset estimation method based on correlation function approximation by polynomi-als |
| CN109639404A (en) * | 2018-12-28 | 2019-04-16 | 四川安迪科技实业有限公司 | A kind of timing offset estimation method based on difference correlation function approximation by polynomi-als |
| WO2020186383A1 (en) * | 2019-03-15 | 2020-09-24 | 深圳市汇顶科技股份有限公司 | Correction circuit and related signal processing circuit, and chip |
| CN114859308A (en) * | 2022-07-11 | 2022-08-05 | 陕西昱琛航空设备股份有限公司 | Radar target simulator and calibration method thereof |
-
2005
- 2005-07-08 CN CN 200580030275 patent/CN101023614A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102668383A (en) * | 2009-07-30 | 2012-09-12 | 电信教育集团(国家高等电信学校) | Correction of analog defects in parallel analog-to-digital converters, in particular for multi-standard, software-defined radio, and/or cognitive radio use |
| CN107171645A (en) * | 2012-03-04 | 2017-09-15 | 匡坦斯公司 | Power amplifier system and delay calibration method |
| CN102984099A (en) * | 2012-11-23 | 2013-03-20 | 陕西理工学院 | Algorithm for digital predistortion fraction time delay estimation and signal alignment and achievement thereof |
| CN102984099B (en) * | 2012-11-23 | 2015-09-02 | 陕西理工学院 | Digital pre-distortion fractional delay is estimated and signal alignment method and system |
| CN104123267B (en) * | 2014-07-21 | 2017-02-15 | 电子科技大学 | High-precision fine synchronization device and method |
| CN104320095A (en) * | 2014-10-23 | 2015-01-28 | 清华大学 | Method and device for decreasing ADC (analog to digital converter) sampling rate in digital pre-distortion |
| CN109347612A (en) * | 2018-11-01 | 2019-02-15 | 四川安迪科技实业有限公司 | A kind of timing offset estimation method based on correlation function approximation by polynomi-als |
| CN109639404A (en) * | 2018-12-28 | 2019-04-16 | 四川安迪科技实业有限公司 | A kind of timing offset estimation method based on difference correlation function approximation by polynomi-als |
| CN109639404B (en) * | 2018-12-28 | 2021-03-02 | 四川安迪科技实业有限公司 | Timing deviation estimation method based on differential correlation function polynomial approximation |
| WO2020186383A1 (en) * | 2019-03-15 | 2020-09-24 | 深圳市汇顶科技股份有限公司 | Correction circuit and related signal processing circuit, and chip |
| CN114859308A (en) * | 2022-07-11 | 2022-08-05 | 陕西昱琛航空设备股份有限公司 | Radar target simulator and calibration method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101023614A (en) | System and method for digital timing error correction in a communications system utilizing adaptive predistortion | |
| US10523159B2 (en) | Digital compensator for a non-linear system | |
| EP1727277B1 (en) | Power series predistorter and control method thereof | |
| US8731105B2 (en) | Multi-rate filter and filtering method for digital pre-distorters | |
| EP1723725B1 (en) | Digital predistortion system and method for linearizing an rf power amplifier with nonlinear gain characteristics and memory effects | |
| US6836517B2 (en) | Distortion compensating apparatus | |
| US7091779B2 (en) | Non-linear modeling method | |
| US7239671B2 (en) | System and method for digital timing error correction in a communications system utilizing adaptive predistortion | |
| US7822146B2 (en) | System and method for digitally correcting a non-linear element | |
| EP2202879B1 (en) | A predistortion apparatus and predistortion method | |
| JP4255361B2 (en) | Distortion compensation amplifier | |
| EP2221962B1 (en) | Predistorter and distortion compensation method | |
| US8121560B1 (en) | Pre-distortion with enhanced convergence for linearization | |
| US20080130789A1 (en) | System and methods for digitally correcting a non-linear element using a digital filter for predistortion | |
| EP1932308B1 (en) | Amplifier system employing analog polynomial predistortion with sub-nyquist digital adaptation | |
| CN101971507A (en) | Receiver second order intermodulation correction system and method | |
| CA2815541A1 (en) | Joint process estimator with variable tap delay line for use in power amplifier digital predistortion | |
| JP2005203960A (en) | Method for adjusting timing of radio communication equipment | |
| EP3262752A1 (en) | Vector signal alignment for digital vector processing using vector transforms | |
| EP2525488A1 (en) | Amplifying device and signal processing device | |
| US7881404B2 (en) | Distortion correction control apparatus and distortion correction control method | |
| JP4755937B2 (en) | Distortion compensation apparatus and distortion compensation method | |
| US8295394B1 (en) | Error signal formation for linearization | |
| CN104510471A (en) | Signal processing method, device and magnetic resonance system | |
| US8957729B2 (en) | Memory structure having taps and non-unitary delays between taps |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20070822 |