CN101018456A - 裸芯片嵌入式pcb及其制造方法 - Google Patents

裸芯片嵌入式pcb及其制造方法 Download PDF

Info

Publication number
CN101018456A
CN101018456A CNA2007100075845A CN200710007584A CN101018456A CN 101018456 A CN101018456 A CN 101018456A CN A2007100075845 A CNA2007100075845 A CN A2007100075845A CN 200710007584 A CN200710007584 A CN 200710007584A CN 101018456 A CN101018456 A CN 101018456A
Authority
CN
China
Prior art keywords
bare chip
pcb
insulated substrate
filler
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007100075845A
Other languages
English (en)
Other versions
CN100576977C (zh
Inventor
韩庚真
金亨泰
金汶日
李在杰
李斗焕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of CN101018456A publication Critical patent/CN101018456A/zh
Application granted granted Critical
Publication of CN100576977C publication Critical patent/CN100576977C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/184—Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01002—Helium [He]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种具有嵌入式裸芯片的PCB及其制造方法。制造PCB的方法可以包括：将裸芯片嵌入到板中，从而露出裸芯片的电极焊盘；以及在电极焊盘上形成电极凸块。这样，可使得裸芯片嵌入式PCB的量产***具有简单的工艺和较低的成本。

Description

裸芯片嵌入式PCB及其制造方法
相关申请交叉参考
本申请要求于2006年2月9日向韩国知识产权局提交的第10-2006-0012512号韩国专利申请的权益，其全部内容结合于此作为参考。
技术领域
本发明涉及一种印刷电路板，具体地说，涉及一种具有嵌入式电子元件的印刷电路板及其制造方法。
背景技术
近年来，电子元件的尺寸变得越来越小，同时对在单个封装件中提供各种功能的高端产品的需求越来越大。为了满足消费者的这些需求，迄今粘附于基板表面上的元件正被嵌入到基板内部。但是，这种嵌入技术导致了成本增加的问题，并且该成本增加必须用电特性的改进和小型化来补偿。因此需要廉价的嵌入技术，以便促进嵌入式板的商业化。
到现在为止，大多数嵌入技术已应用到晶圆级封装件，其中由金或铜制成的凸块以面积陈列的形式分布于芯片的整个表面上，原因是在将芯片嵌入到厚度较薄(大约1μm厚度)的铝焊盘(其通常用作芯片的表层金属(finish metal))中之后难以进行激光处理。但是，就面积陈列而言，由于重新布线和形成金属凸块的费用，因而提高了整个封装件的价格。
图1是根据现有技术的具有嵌入式芯片的PCB的横截面视图，其中具有电极凸块27的芯片22嵌入于芯板23的内部。
传统地，为了嵌入如图1所示的芯片，进行在芯片的焊盘上形成电极凸块的操作，这种操作通常由外国公司进行。因此，形成凸块的工艺产生了额外的成本和时间。
发明内容
本发明的一方面在于提供一种具有嵌入式裸芯片的PCB及其制造方法，其中省略了在电极焊盘上形成凸块的工艺，而裸芯片照原状嵌入。
本发明的一个方面提供了一种制造PCB的方法，该方法包括：在板中嵌入裸芯片，从而露出裸芯片的电极焊盘；以及在电极焊盘上形成电极凸块。
优选地，电极凸块的形成步骤包括形成电路。还优选地，该电路与电极凸块电连接。
本发明的另一方面提供了一种制造PCB的方法，包括：将带粘附到绝缘基板的一侧，该绝缘基板具有形成于其中的穿透孔，并将裸芯片粘附到穿透孔内部的带上，从而裸芯片的电极焊盘面向带；用填充物填充穿透孔，并去除带；将金属层层压到填充物和绝缘基板的去除带的表面上；以及通过去除部分金属层而形成电极凸块。
制造PCB的方法还可包括：在填充穿透孔与层压之间，清洁填充物和绝缘基板的一侧。
在制造PCB的方法中，层压步骤可包括：将扩散阻挡层层压到绝缘基板的一侧上；以及将厚膜层压到扩散阻挡层的上侧上。
电极凸块的形成步骤可进一步包括：去除部分金属层；以及在绝缘基板的一侧上形成电路。
本发明的另一方面提供了具有嵌入式裸芯片的PCB(印刷电路板)，其包括：绝缘基板，具有形成于其中的穿透孔；填充物，填充于穿透孔的内部；裸芯片，嵌入于填充物中，使得形成于裸芯片一侧上的电极焊盘暴露于填充物的表面处；以及电极凸块，粘附于电极焊盘的表面。
优选地，电极凸块包括：扩散阻挡层，位于电极焊盘的表面处；以及厚膜，层压于扩散阻挡层的表面上。另外，扩散阻挡层可由钛制成。
附图说明
图1是根据现有技术的具有嵌入式芯片的PCB的横截面视图；
图2A是制造根据本发明第一公开实施例的具有嵌入式裸芯片的PCB的方法的流程图；
图2B是根据本发明第一公开实施例的裸芯片嵌入式PCB的制造简图；
图3A是制造根据本发明第二公开实施例的具有嵌入式裸芯片的PCB的方法的流程图；
图3B是示出了根据本发明第二公开实施例的具有嵌入式裸芯片的PCB的制造过程的概念简图；
图4是根据本发明第三公开实施例的裸芯片的仰视图；
图5是制造根据本发明第四公开实施例的具有嵌入式裸芯片的PCB的方法的概念简图；
图6是根据本发明第五公开实施例的具有嵌入式裸芯片的PCB的横截面视图。
具体实施方式
下面，将参照附图详细描述根据本发明的裸芯片嵌入式PCB的实施例。在参照附图的描述中，与图号无关，那些相同或相关的元件以相同的参考标号表示，并且省略了重复的解释。
图2A是制造根据本发明第一公开实施例的具有嵌入式裸芯片的PCB的方法的流程图，而图2B是根据本发明第一公开实施例的裸芯片嵌入式PCB的制造简图。参照图2B，示出了板21、电极焊盘24、裸芯片23、填充物25、电路图案28、以及电极凸块29。
图2A的S11是将裸芯片嵌入到板21内部以露出电极焊盘24的操作。在通过使用钻孔机形成凹槽之后，可以通过使用如图2B的(a)中的填充物25而***裸芯片23，或也可以使用粘合剂而***裸芯片。重要的是裸芯片23的电极焊盘24暴露于板21的表面处。
图2A的S12是在电极焊盘的表面上形成电极凸块的操作。电极凸块29通常可以通过电镀、或溅射或其它类型的丝网印刷术而形成。在形成电极凸块29之前，可在电极焊盘24的表面上形成扩散阻挡层。
电路图案28可在形成电极凸块29的同时形成，或可在不同的操作中形成。另外，电路图案28可直接与电极凸块29连接。
图3A是制造根据本发明第二公开实施例的具有嵌入式裸芯片的PCB的方法的流程图，图3B是示出了根据本发明第二公开实施例的具有嵌入式裸芯片的PCB的制造过程的概念简图，而图4是根据本发明第三公开实施例的裸芯片的仰视图。参照图3B和图4，示出了绝缘基板31、带32、裸芯片33、电极焊盘34、填充物35、金属层36、扩散阻挡层36a、厚膜36b、穿透孔38、电极凸块39、以及PCB 100。
与图3B的(a)相对应，图3A的S21是如下的操作：将带32粘附到其中形成有穿透孔38的绝缘基板31的一侧，以及沿电极焊盘34的方向将裸芯片33粘附到穿透孔38内部的带32。
绝缘基板31通常可由聚酯胶片制成。聚酯胶片是一种通常由树脂和玻璃纤维制成的材料，并且用作PCB的绝缘材料。当然，其它材料也可用作绝缘基板31，只要它满足绝缘功能即可。
当准备该绝缘基板31时，对其中将***裸芯片33的穿透孔38打孔。机械钻孔是打孔方法的一个实例。穿透孔38可以比裸芯片33宽，但不需要将穿透孔38形成为过宽的尺寸。过宽尺寸的穿透孔38将需要更多的填充物35，以在裸芯片33***之后填充空区，并且可能降低绝缘基板31的强度。
接着，将带32粘附到绝缘基板31。带可在至少一侧上具有粘附力。这是为了易于与绝缘基板31粘合，并将裸芯片33固定在穿透孔38的内部。
当将带32粘附到绝缘基板31的一侧时，通过穿透孔38另一侧上的开口侧将裸芯片33***并粘附地固定到带32。此时，重要的是裸芯片33的电极焊盘34面向带32。这是因为将在电极焊盘34的上表面上顺序形成金属层36。
裸芯片33是恰恰在进行封装之前从晶圆上切割下来的芯片。如图4所示，在将连接到外部电极的裸芯片33的一侧上形成有多个电极焊盘34。
与图3B的(b)和(c)相对应，图3A的S22是在穿透孔38内部填入填充物35并去除带32的操作。
当在操作S21中已将裸芯片33粘附地固定到带32的表面时，将填充物35填充到穿透孔38内部。虽然通常使用环氧树脂来作为填充物，但是也可使用具有绝缘和粘附特性的任何其它材料。
在填充物35硬化之后，去除带32。当去除带32后，如图3B的(c)中所示，裸芯片33的电极焊盘34被暴露于外部。
与图3B的(d)、(e)相对应，图3A的S23是形成金属层36的操作。金属层36具有足够的厚度，以便形成电极凸块39。
因此，通过非电解镀或溅射工艺形成将作为籽层的扩散阻挡层36a。扩散阻挡层36a不仅用作籽层，并且还防止镀于扩散阻挡层36a上的厚膜36b与电极焊盘34之间的扩散。
通常，电极焊盘34可由铝制成，而厚膜36b可由铜制成。当铝和铜彼此直接接触时，它们具有易于被应力破坏的特性，从而发生扩散。
因此，必须具有上述的扩散阻挡层36a。就扩散阻挡层36a而言，通常可使用钛。但是，也可使用实现相同目的的任何其它材料。
理想地是采用诸如溅射等的干式工艺来形成具有钛的扩散阻挡层36a，原因是在液态下难以获得沉淀。
在形成该扩散阻挡层36a之后，通过电镀在相对较短的时间内形成厚膜(5mm)。
与图3A的S24相对应，在图3B的(f)中，在绝缘基板31和填充物35中嵌入裸芯片33之后，通过进行诸如光刻工艺的蚀刻工艺，在包括扩散阻挡层36a和厚膜36b的金属层36上形成电极凸块39。从而完成PCB 100。其间，可以通过蚀刻同时形成电路图案。
虽然上述的图3B的制造过程是使用消减(subtractive)法的操作，但是也可以使用半加(semi-additive)法来获得同样的效果。下面，将详细描述使用半加法的本发明的实施例。
图5是制造根据本发明第四公开实施例的具有嵌入式裸芯片的PCB的方法的概念简图。参照图5，示出了绝缘基板31、裸芯片33、电极焊盘34、填充物35、扩散阻挡层36a、厚膜36b、金属层36、电极凸块39、干膜41、图案44、电路图案49、以及PCB 100。
该实施例省略了图5的操作(a)至(d)，原因是它们与图3B的实施例的操作相同。后续的操作如下：
图5中的图(g)示出了以下操作：将感光干膜41粘附到扩散阻挡层36a的上侧上，以及在曝光和显影工艺之后形成图案。在本实施例中，将要形成电路图案49和电极凸块39的部分同时被显影。
扩散阻挡层36a暴露于显影部分中。由于扩散阻挡层36a是金属层，所以通过电镀在图5的(h)中形成厚膜36b。
当在去除干膜41之后通过蚀刻已去除了扩散阻挡层时，在绝缘基板31的上侧上形成电路图案49，并在电极焊盘34的表面上形成电极凸块39。
上述的消减法和半加法是用于形成电路图案的一般工艺。在这些工艺期间，自然地形成了裸芯片的电极凸块，从而不需要用于形成电极凸块的其它工艺。
在图3B的(f)和图5的(j)中，可以使用RCC(涂覆有铜的树脂)或聚酯胶片在PCB 100上继续进行堆叠工艺。另外，在堆叠工艺之后，通过使用激光钻孔机或机械钻孔机可形成导通孔。在导通孔内部进行电镀以便将电极凸块与电路图案相连接之后，就完成了具有嵌入式裸芯片的PCB。
图6是根据本发明第五公开实施例的具有嵌入式裸芯片的PCB的横截面视图。参照图6，示出了绝缘基板31、裸芯片33、电极焊盘34、填充物35、金属层36、扩散阻挡层36a、厚膜36b、穿透孔38、电极凸块39、以及PCB 100。
绝缘基板31内部的穿透孔38填充有填充物35。聚酯胶片通常可用作绝缘基板31。穿透孔38可通过机械方法形成。穿透孔38的内部填充有填充物35，其中环氧树脂可用作填充物35的材料。优选地，填充物35具有绝缘特性和粘附特性。
同时，裸芯片33嵌入于填充物35中。优选地，裸芯片33的具有电极焊盘34的侧面暴露于填充物35的表面处。电极凸块39形成在电极焊盘34的上侧上。从而，电极凸块39从PCB 100的表面呈现突出的形状。由于在堆叠工艺期间电极凸块39突出于绝缘基板的内部，这种形状使得相对容易通过诸如激光钻孔等工艺形成导通孔。
理想地，电极凸块39由两个金属层形成，其中电极凸块39可包括与电极焊盘34相接触的扩散阻挡层36a以及设置于扩散阻挡层36a上的厚膜36b。具体地说，理想地，扩散阻挡层36a由诸如钛等的金属制成。钛可设置在铝(通常用于电极焊盘34)与铜(通常用于厚膜36b)之间，以防止扩散。
厚膜36b通常可通过电镀制成，原因是电镀具有可在相对较短的时间内形成厚层的优点。通常，该厚膜36b由铜层制成。但是，如果可获得同样的效果，也可使用任何其它金属。
根据上述组成的本发明，以前在裸芯片状态下曾应用的重新布线工艺可在PCB的一般生产线中进行。从而，可使得具有嵌入式裸芯片的PCB的量产***具有简单的工艺和较低的成本。
虽然上面的描述已经指出了应用于各种实施例时的本发明的新颖特征，但是，本领域技术人员可以理解，在不背离本发明范围的前提下，可以对示出的装置或工艺在形式或细节方面进行各种省略、替换、和改变。因此本发明的范围通过所附权利要求限定，而非通过上面的描述限定。在所述权利要求等同的意义和范围内的所有变化都包含在本发明的范围内。

Claims (10)

1.一种制造具有嵌入式裸芯片的PCB(印刷电路板)的方法，所述方法包括：
在板中嵌入裸芯片，从而露出所述裸芯片的电极焊盘；以及
在所述电极焊盘上形成电极凸块。
2.根据权利要求1所述的方法，其中，电极凸块的形成步骤包括形成电路。
3.根据权利要求2所述的方法，其中，所述电路与所述电极凸块电连接。
4.一种制造具有嵌入式裸芯片的PCB(印刷电路板)的方法，所述方法包括：
将带粘附到绝缘基板的一侧，所述绝缘基板具有形成于其中的穿透孔，并将所述裸芯片粘附到所述穿透孔内部的所述带上，从而所述裸芯片的电极焊盘面向所述带；
用填充物填充所述穿透孔，并去除所述带；
将金属层层压到所述填充物和所述绝缘基板的去除所述带的表面上；以及
通过去除部分所述金属层而形成电极凸块。
5.根据权利要求4所述的方法，进一步包括：在所述填充与所述层压之间，清洁所述填充物和所述绝缘基板的一侧。
6.根据权利要求4所述的方法，其中，所述层压步骤包括：
将扩散阻挡层层压到所述绝缘基板的一侧上；以及
将厚膜层压到所述扩散阻挡层的上侧上。
7.根据权利要求4所述的方法，其中，电极凸块的形成步骤进一步包括：去除部分所述金属层；以及在所述绝缘基板的一侧上形成电路。
8.一种具有嵌入式裸芯片的PCB(印刷电路板)，所述PCB包括：
绝缘基板，具有形成于其中的穿透孔；
填充物，填充于所述穿透孔的内部；
裸芯片，嵌入于所述填充物中，从而形成于所述裸芯片一侧上的电极焊盘暴露于所述填充物的表面处；以及
电极凸块，粘附于所述电极焊盘的表面。
9.根据权利要求8所述的PCB，其中，所述电极凸块包括：扩散阻挡层，位于所述电极焊盘的表面处；以及厚膜，层压于所述扩散阻挡层的表面上。
10.根据权利要求8所述的PCB，其中，所述扩散阻挡层包含钛。
CN200710007584A 2006-02-09 2007-02-08 裸芯片嵌入式pcb及其制造方法 Expired - Fee Related CN100576977C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060012512 2006-02-09
KR1020060012512A KR100736635B1 (ko) 2006-02-09 2006-02-09 베어칩 내장형 인쇄회로기판 및 그 제조 방법

Publications (2)

Publication Number Publication Date
CN101018456A true CN101018456A (zh) 2007-08-15
CN100576977C CN100576977C (zh) 2009-12-30

Family

ID=37832239

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200710007584A Expired - Fee Related CN100576977C (zh) 2006-02-09 2007-02-08 裸芯片嵌入式pcb及其制造方法

Country Status (6)

Country Link
US (2) US8184448B2 (zh)
JP (1) JP2007214572A (zh)
KR (1) KR100736635B1 (zh)
CN (1) CN100576977C (zh)
DE (1) DE102007005920A1 (zh)
FI (1) FI20075088L (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100576976C (zh) * 2007-11-21 2009-12-30 健鼎（无锡）电子有限公司 直接埋入被动组件的电路板制造方法
CN107046771A (zh) * 2017-05-30 2017-08-15 邹时月 一种埋入式电路板的制造方法
CN107124822A (zh) * 2017-05-30 2017-09-01 邹时月 一种裸芯片嵌入式电路板的制造方法
CN112203433A (zh) * 2019-07-07 2021-01-08 深南电路股份有限公司 埋入式电路板的制造方法、埋入式电路板以及应用
CN113766731A (zh) * 2020-06-02 2021-12-07 苏州旭创科技有限公司 一种电路板组件的组装方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101019642B1 (ko) * 2009-04-27 2011-03-07 삼성전기주식회사 인쇄회로기판 제조 방법
US8390083B2 (en) * 2009-09-04 2013-03-05 Analog Devices, Inc. System with recessed sensing or processing elements
US8120158B2 (en) * 2009-11-10 2012-02-21 Infineon Technologies Ag Laminate electronic device
WO2012051340A1 (en) 2010-10-12 2012-04-19 Analog Devices, Inc. Microphone package with embedded asic
CN102693968B (zh) 2012-05-25 2014-12-03 华为技术有限公司 芯片堆叠封装结构
KR101420514B1 (ko) * 2012-10-23 2014-07-17 삼성전기주식회사 전자부품들이 구비된 기판구조 및 전자부품들이 구비된 기판구조의 제조방법
US9202162B2 (en) 2012-11-09 2015-12-01 Maxim Integrated Products, Inc. Embedded radio frequency identification (RFID) package
CN104576883B (zh) 2013-10-29 2018-11-16 普因特工程有限公司 芯片安装用阵列基板及其制造方法
WO2016002803A1 (ja) * 2014-07-04 2016-01-07 三菱マテリアル株式会社 パワーモジュール用基板ユニット及びパワーモジュール
US9666558B2 (en) 2015-06-29 2017-05-30 Point Engineering Co., Ltd. Substrate for mounting a chip and chip package using the substrate
CN105050338B (zh) * 2015-07-07 2017-12-26 深圳市迅捷兴科技股份有限公司 内层带有镶嵌物的电路板压合结构及其制造方法
JP2018056314A (ja) * 2016-09-28 2018-04-05 京セラ株式会社 印刷配線板の製造方法および印刷配線板

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293637A (en) 1977-05-31 1981-10-06 Matsushita Electric Industrial Co., Ltd. Method of making metal electrode of semiconductor device
US4635356A (en) 1984-12-28 1987-01-13 Kabushiki Kaisha Toshiba Method of manufacturing a circuit module
FR2599893B1 (fr) * 1986-05-23 1996-08-02 Ricoh Kk Procede de montage d'un module electronique sur un substrat et carte a circuit integre
US5563449A (en) * 1995-01-19 1996-10-08 Cornell Research Foundation, Inc. Interconnect structures using group VIII metals
JP2842378B2 (ja) * 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
US6162652A (en) * 1997-12-31 2000-12-19 Intel Corporation Process for sort testing C4 bumped wafers
JP2000124248A (ja) * 1998-10-16 2000-04-28 Fujitsu Ltd 半導体装置の製造方法
KR101084526B1 (ko) * 1999-09-02 2011-11-18 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
JP3813402B2 (ja) 2000-01-31 2006-08-23 新光電気工業株式会社 半導体装置の製造方法
JP4851652B2 (ja) * 2000-02-09 2012-01-11 日本特殊陶業株式会社 配線基板及びその製造方法
KR20080031522A (ko) 2000-02-25 2008-04-08 이비덴 가부시키가이샤 다층프린트배선판 및 다층프린트배선판의 제조방법
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
JP3895156B2 (ja) 2000-12-28 2007-03-22 日本特殊陶業株式会社 配線基板
US6770965B2 (en) 2000-12-28 2004-08-03 Ngk Spark Plug Co., Ltd. Wiring substrate using embedding resin
US6894399B2 (en) * 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) * 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) * 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
JP3934906B2 (ja) 2001-10-19 2007-06-20 京セラ株式会社 回路基板
TW546800B (en) * 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
JP2004055967A (ja) 2002-07-23 2004-02-19 Matsushita Electric Ind Co Ltd 電子部品内蔵基板の製造方法
JP2004007006A (ja) 2003-09-16 2004-01-08 Kyocera Corp 多層配線基板
FI117814B (fi) 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
TWI260056B (en) * 2005-02-01 2006-08-11 Phoenix Prec Technology Corp Module structure having an embedded chip
TWI275149B (en) * 2005-05-09 2007-03-01 Phoenix Prec Technology Corp Surface roughing method for embedded semiconductor chip structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100576976C (zh) * 2007-11-21 2009-12-30 健鼎（无锡）电子有限公司 直接埋入被动组件的电路板制造方法
CN107046771A (zh) * 2017-05-30 2017-08-15 邹时月 一种埋入式电路板的制造方法
CN107124822A (zh) * 2017-05-30 2017-09-01 邹时月 一种裸芯片嵌入式电路板的制造方法
CN112203433A (zh) * 2019-07-07 2021-01-08 深南电路股份有限公司 埋入式电路板的制造方法、埋入式电路板以及应用
WO2022007275A1 (zh) * 2019-07-07 2022-01-13 深南电路股份有限公司 埋入式电路板的制造方法、埋入式电路板以及应用
US11632861B2 (en) 2019-07-07 2023-04-18 Shennan Circuits Co., Ltd. Method for manufacturing embedded circuit board, embedded circuit board, and application
CN113766731A (zh) * 2020-06-02 2021-12-07 苏州旭创科技有限公司 一种电路板组件的组装方法

Also Published As

Publication number Publication date
CN100576977C (zh) 2009-12-30
US8929091B2 (en) 2015-01-06
FI20075088L (fi) 2007-08-10
US20110277320A1 (en) 2011-11-17
US8184448B2 (en) 2012-05-22
JP2007214572A (ja) 2007-08-23
DE102007005920A1 (de) 2007-09-06
FI20075088A0 (fi) 2007-02-07
US20070181988A1 (en) 2007-08-09
KR100736635B1 (ko) 2007-07-06

Similar Documents

Publication Publication Date Title
CN100576977C (zh) 裸芯片嵌入式pcb及其制造方法
US8745860B2 (en) Method for manufacturing printed wiring board
CN100588310C (zh) 电路板及其制造方法
KR100997199B1 (ko) 전자소자 내장형 인쇄회로기판 제조방법
US20080102410A1 (en) Method of manufacturing printed circuit board
CN101166394A (zh) 安装有电子元件的多层配线基板及其制造方法
CN101683006B (zh) 电子部件内置线路板及其制造方法
CN102656955A (zh) 制造具有不对称积层的基板的方法
CN101315917A (zh) 配线基板及其制造方法
KR101255954B1 (ko) 인쇄회로기판 및 인쇄회로기판 제조 방법
TW201123326A (en) Method of manufacturing substrate for flip chip and substrate for flip chip manufactured using the same
JP2010118633A (ja) 埋込み型ソルダーバンプを持つプリント基板及びその製造方法
TW201123391A (en) Lead frame and manufacturing method of the same
JP5982760B2 (ja) 電子デバイス及びその製造方法
CN105722299A (zh) 中介基板及其制法
CN101083214A (zh) 封装基板的制造方法
KR100923501B1 (ko) 패키지 기판 제조방법
JP4870501B2 (ja) 電子部品内蔵基板の製造方法
JP4549693B2 (ja) 配線基板の製造方法
JP2005243986A (ja) 配線基板の製造方法
CN104952858B (zh) 半导体器件、半导体层叠模块构造、层叠模块构造以及它们的制造方法
CN115241135A (zh) 一种晶圆级封装结构及工艺
CN115241136A (zh) 一种晶圆级封装结构及工艺
JP2006278413A (ja) 半導体基板実装構造、表示装置、接着シートおよび基板実装方法
KR20090032831A (ko) 웨이퍼를 패키징하는 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091230

Termination date: 20220208

CF01 Termination of patent right due to non-payment of annual fee