CN101017834A - SOI integrated circuit structure and its making method - Google Patents
SOI integrated circuit structure and its making method Download PDFInfo
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- CN101017834A CN101017834A CN 200710037775 CN200710037775A CN101017834A CN 101017834 A CN101017834 A CN 101017834A CN 200710037775 CN200710037775 CN 200710037775 CN 200710037775 A CN200710037775 A CN 200710037775A CN 101017834 A CN101017834 A CN 101017834A
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Abstract
The provided SOI IC structure comprises: from top to bottom, a monocrystal-Si layer with shallow groove isolation structure, an insulation material buried layer, and a Si substrate. Wherein, there is insulation material on side wall of former groove throughout the buried layer to contact with Si substrate. This invention improves heat dispersion efficiency and device performance.
Description
[technical field]
The present invention relates to SOI (Silicon On Insulator, silicon-on-insulator) integrated circuit fields, relate in particular to a kind of SOI integrated circuit structure that strengthens heat-sinking capability and preparation method thereof.
[background technology]
Follow the continuous progress of integrated circuit fabrication process, it is more and more littler that the volume of semiconductor device is just becoming, and the thing followed is a large amount of problems that device size is produced when approaching physics limit.This makes industry begin to seek the solution except simple reduction of device size, further improves device performance.SOI is as an important developing direction and by industry broad research and use.Compare the conventional bulk silicon materials, the characteristics of SOI are, are insulating barriers under a monocrystalline silicon layer of very thin surface, mainly are as insulating material with silica.Be traditional body silicon materials under the insulating barrier, the effect of this one deck is that top structure is played the mechanical support effect.The mechanism of SOI has reduced the leakage current of device greatly under the prerequisite that does not change device size, reduced the device heating amount, thereby device performance is improved greatly.
But, when SOI possesses these advantages, also brought the problem of heat radiation aspect.The conductive coefficient of single crystal silicon material in the time of 25 ℃ is 83.5, and the conductive coefficient of silicon dioxide only is 1.5～39.Particularly at STI (Shallow Trench Isolation, shallow trench isolation from) in the structural manufacturing process, after STI finishes, device is just as being held by the formed bowl of silicon dioxide by one, heat can't effectively be discharged in the substrate body silicon materials and go, thereby has influence on the Performance And Reliability of device.
[summary of the invention]
The object of the present invention is to provide a kind of SOI integrated circuit structure, it is poor to have overcome existing SOI technology heat-sinking capability, and the deficiency that heat can't effectively discharge is utilized insulating heat-conduction material structure heat conduction loop, improve the soi chip heat-sinking capability, improve the general performance of chip.
In order to realize this purpose, the invention provides a kind of SOI integrated circuit structure, have the soi structure that is followed successively by monocrystalline silicon layer, insulating material buried regions and substrate body silicon materials from top to bottom, have fleet plough groove isolation structure at monocrystalline silicon layer.Described shallow trench sidewall and bottom are provided with insulating heat-conduction material, and described insulating heat-conduction material runs through the insulating material buried regions, and the bottom of described insulating heat-conduction material contacts with substrate body silicon materials.Described insulating heat-conduction material thickness is 5～30 nanometers.Described insulating heat-conduction material conductive coefficient is greater than silicon dioxide.Described insulating heat-conduction material is a carborundum.
Another object of the present invention is to provide a kind of manufacture method of SOI integrated circuit structure, to improve the soi chip heat-sinking capability, the general performance that improves chip.
In order to realize this goal of the invention, the invention provides a kind of manufacture method of SOI integrated circuit structure, make fleet plough groove isolation structure, etch groove at monocrystalline silicon layer, further etching is removed described bottom portion of groove insulating material buried regions, at described groove inwall deposit one deck insulating heat-conduction material, be communicated with described monocrystalline silicon layer and substrate body silicon materials, the silica of deposit fleet plough groove isolation structure.
Wherein, described further etching is anisotropic insulating barrier etching.Described further etching is carved the insulating barrier buried regions of wearing in the soi wafer, stops on the substrate body silicon materials.Described insulating heat-conduction material is a carborundum.Described deposit insulating heat-conduction material film thickness is 5～30 nanometers.
The invention provides the manufacture method that another program provides a kind of SOI integrated circuit structure, may further comprise the steps: a. makes and also to finish the hard mask lithography of upper surface, and etching and removing photoresist is formed with the hard mask layer of figure; B. the etching single crystal silicon layer forms groove, cleans; C. further etching removal bottom portion of groove insulating material buried regions exposes substrate body silicon materials, cleans; D. at groove inwall deposit one deck insulating heat-conduction material, anneal; E. the deposit shallow trench isolation is from silica.
Wherein, the etching among the described step b is the plasma dry etching, and etching gas is a halogen gas.Etching stopping among the described step b is on the insulating material buried regions.Cleaning among the described step b adopts ammonium hydroxide and hydrogen peroxide mixed liquor to clean.
Etching among the described step c is the plasma dry etching, and etching gas is the carbon fluorine type gas.Cleaning among the described step c adopts one or more combinations in standard cleaning program, hydrochloric acid and hydrogen peroxide mixed liquor, ammonium hydroxide and hydrogen peroxide mixed liquor, the dilute hydrofluoric acid to clean.
The insulating heat-conduction material of deposit is a carborundum in the described steps d.High-density plasma chemical vapor deposition or plasma auxiliary chemical vapor deposition are adopted in deposit in the described steps d, and deposited gas is methane and silane.Deposition parameters is in the described steps d: temperature is 150 ℃～400 ℃, and pressure is 0.001～50 holder, and deposition film thickness is 5～30 nanometers.Annealing temperature is 800 ℃～1200 ℃ in the described steps d.
The invention has the advantages that: the present invention utilizes heat conductivility good insulation performance Heat Conduction Material (as carborundum, conductive coefficient 100～125), between surface single crystal silicon and substrate body silicon materials, made up a heat conduction loop, this structure can form a passage of heat that goes up between the lower silicon layer, the heat that the device that is produced on the monocrystalline silicon layer is produced when work can be more convenient be delivered on the substrate, thereby improved heat-sinking capability.Chip performance and reliability have been improved.
Simultaneously, the present invention has made full use of existing structure, need not additionally to increase lithography step, compare with existing technology, the advantage of this structure is can not change existing device architecture, also only needing on technology increases an etching and a deposit, has great advantage on cost and feasibility, has good feasibility and cost performance.
[description of drawings]
Fig. 1 is the structural section figure after the present invention finishes traditional STI etching;
Fig. 2 is the structural section figure after the present invention finishes insulating material buried regions etching;
Fig. 3 is the structural section figure after the present invention finishes the insulating heat-conduction material deposit;
Fig. 4 is the structural section figure after the present invention finishes the STI deposit.
[embodiment]
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail:
An embodiment of the manufacture method of SOI integrated circuit structure of the present invention is, at one is on the soi structure of monocrystalline silicon layer, insulating material buried regions and substrate body silicon materials from top to bottom successively, at first make fleet plough groove isolation structure, etch groove at monocrystalline silicon layer, further etching is removed described bottom portion of groove insulating material buried regions, at described groove inwall deposit one deck insulating heat-conduction material, be communicated with described monocrystalline silicon layer and substrate body silicon materials, the silica of deposit fleet plough groove isolation structure.Thereby, finished the making that the present invention has the SOI integrated circuit structure of heat radiation conducting structure by transformation to traditional shallow groove isolation structure manufacturing method.
Etching for bottom portion of groove insulating material buried regions is anisotropic insulating barrier etching, and its specification requirement is to carve the insulating barrier buried regions of wearing in the soi wafer, stops on the substrate body silicon materials.Therefore its etching depth should be more than or equal to the thickness of insulating barrier buried regions.
At first please refer to Fig. 1, Fig. 1 is the structural section figure after the present invention finishes traditional STI etching, and in Fig. 1, being positioned at uppermost is monocrystalline silicon layer 1, and monocrystalline silicon layer 1 below is an insulating material buried regions 2, and bottom one deck is a substrate body silicon material layer 3.Monocrystalline silicon layer 1 and substrate body silicon material layer 3 have preferable conduction and heat conductivility, and insulating material buried regions 2 generally is a silicon dioxide, its heat conductivility is relatively poor, and the conductive coefficient of single crystal silicon material in the time of 25 ℃ is 83.5, and the conductive coefficient of silicon dioxide only is 1.5～39.
In traditional STI technology, as shown in Figure 1, adopt and use plasma dry etching single crystal silicon layer 1, main gas is halogen gas, etch thicknesses depends on employed silicon chip, is 30～500 nanometers, and etching stopping is on insulating material buried regions 2, use APM (ammonium hydrogen peroxidemixture ammonium hydroxide, hydrogen peroxide mixed liquor) to clean.
Certainly, before implementing traditional STI, at first will make and finish the hard mask lithography of upper surface, etching and removing photoresist is formed with the hard mask layer of figure, to determine to form particular location, shape and the size of sti structure.
See also Fig. 2, Fig. 2 is the structural section figure after the present invention finishes insulating material buried regions etching.In Fig. 2, in forming Fig. 1 on the basis of monocrystalline silicon layer 1 shallow trench, further use plasma dry etching insulating material buried regions (silicon dioxide) 2, main etching gas is the carbon fluorine type gas, etch thicknesses depends on employed silicon chip, be 100～1000 nanometers, etching stopping is on substrate body silicon materials 3.Among use RCA (radio corporation of amencan standard cleaning program), HPM (hydrochloric-peroxide mix hydrochloric acid, hydrogen peroxide mixed liquor), APM and the DHF (dilutedhydrofluoric acid dilute hydrofluoric acid) one or more clean.
Next see also Fig. 3, Fig. 3 is the structural section figure after the present invention finishes the insulating heat-conduction material deposit.As shown in Figure 3, at groove inwall deposit one deck insulating heat-conduction material 5, be communicated with described monocrystalline silicon layer 1 and substrate body silicon material layer 3, and carry out annealing in process.Can use PECVD (Plasma EnhancedChemical Vapor Deposition, the plasma auxiliary chemical vapor deposition) or HDPCVD (HighDensity Plasma Chemical Vapor Veposition, high-density plasma chemical vapor deposition) deposit.
Insulating heat-conduction material 5 described here must be an insulating material, and its thermal conductivity is better than silicon dioxide (conductive coefficient is 1.5～39) simultaneously, as carborundum (SiC, conductive coefficient are 100～125).In the embodiment that selects for use carborundum as insulating heat-conduction material 5, the deposit using gases is methane and silane, and 150 ℃～400 ℃, pressure is 0.001～50torr.Deposition film thickness is 5～30 nanometers.Annealing temperature is 800 ℃～1200 ℃.
Deposit in certain embodiments can only be carried out the two side of shallow trench, and the insulating heat-conductive 5 of Huo Deing only is to be communicated with monocrystalline silicon layer 1 and substrate body silicon material layer 3 like this, but contact area is less, and radiating effect is not very good; Then the whole inwall of shallow trench is comprised that its two side and bottom all carried out the insulating heat-conduction material deposit among other embodiment, insulating heat-conduction material 5 bottom it contacts with the face of substrate body silicon material layer 3 and has increased area of dissipation, has played better thermolysis.
At last, see also Fig. 4, Fig. 4 is the structural section figure after the present invention finishes the STI deposit.As shown in Figure 4, the deposit shallow trench isolation is from silica 4 in the shallow trench that twice etching forms, and final formation has the shallow trench sidewall, also comprises the shallow ditch groove structure of the insulating heat-conduction material 5 of shallow trench bottom in part embodiment.
In some embodiments of the invention, described substrate body silicon materials 3 thickness are greater than 10000 nanometers, described shallow trench isolation is slightly larger than the thickness sum of monocrystalline silicon layer 1 and insulating material buried regions 2 from silica 4 degree of depth, described shallow trench isolation is 60～350 nanometers from the width of silica 4, and described insulating heat-conduction material 5 thickness are 5～30 nanometers.The specific design size should be according to actual conditions and technological ability change, and those skilled in the art can be implemented according to above-mentioned introduction.
SOI integrated circuit structure of the present invention, has the soi structure that is followed successively by monocrystalline silicon layer 1, insulating material buried regions 2 and substrate body silicon materials 3 from top to bottom, has fleet plough groove isolation structure at monocrystalline silicon layer 1, the shallow trench sidewall is provided with insulating heat-conduction material 5, and this insulating heat-conduction material 5 runs through insulating material buried regions 2 and contacts with substrate body silicon materials 3.Insulating heat-conduction material 5 further comprises the bottom of the insulating heat-conduction material of two shallow trench sidewalls that contacts with substrate body silicon materials 3 and be connected.Among the embodiment shown in Fig. 1 to Fig. 4, insulating heat-conduction material 5 sidewall sections tilt, and bottom connects the insulating heat-conduction material of two shallow trench sidewalls just.But in other embodiment of the present invention, insulating heat-conduction material 5 sidewall sections also can be through holes vertical or that tilt with other angles and direction, bottom also is not limited only to just connect the insulating heat-conduction material of two shallow trench sidewalls, and it can have bigger and contact-making surfaces substrate body silicon materials 3 to obtain better radiating effect.
This structure of the present invention can form a passage of heat that goes up between the lower silicon layer, and the transfer of heat of being convenient to the device generation helps to improve the device radiating efficiency to substrate body silicon materials.
That more than introduces only is based on several preferred embodiment of the present invention, can not limit scope of the present invention with this.Any device of the present invention is done replacement, the combination, discrete of parts well know in the art, and the invention process step is done well know in the art being equal to change or replace and all do not exceed exposure of the present invention and protection range.
Claims (19)
1, a kind of SOI integrated circuit structure, has the soi structure that is followed successively by monocrystalline silicon layer, insulating material buried regions and substrate body silicon materials from top to bottom, has fleet plough groove isolation structure at monocrystalline silicon layer, it is characterized in that: described shallow trench sidewall and bottom are provided with insulating heat-conduction material, described insulating heat-conduction material runs through the insulating material buried regions, and the bottom of described insulating heat-conduction material contacts with substrate body silicon materials.
2, SOI integrated circuit structure as claimed in claim 1 or 2 is characterized in that: described insulating heat-conduction material thickness is 5～30 nanometers.
3, claim 1 or 2 described SOI integrated circuit structures, it is characterized in that: described insulating heat-conduction material conductive coefficient is greater than silicon dioxide.
4, SOI integrated circuit structure as claimed in claim 4, it is characterized in that: described insulating heat-conduction material is a carborundum.
5, a kind of manufacture method of SOI integrated circuit structure, make fleet plough groove isolation structure, etch groove at monocrystalline silicon layer, it is characterized in that: further etching is removed described bottom portion of groove insulating material buried regions, at described groove inwall deposit one deck insulating heat-conduction material, be communicated with described monocrystalline silicon layer and substrate body silicon materials, the silica of deposit fleet plough groove isolation structure.
6, the manufacture method of SOI integrated circuit structure as claimed in claim 6 is characterized in that: described further etching is anisotropic insulating barrier etching.
7, the manufacture method of SOI integrated circuit structure as claimed in claim 6 is characterized in that: described further etching is carved the insulating barrier buried regions of wearing in the soi wafer, stops on the substrate body silicon materials.
8, the manufacture method of SOI integrated circuit structure as claimed in claim 6 is characterized in that: described insulating heat-conduction material is a carborundum.
9, the manufacture method of SOI integrated circuit structure as claimed in claim 6 is characterized in that: described deposit insulating heat-conduction material film thickness is 5～30 nanometers.
10, a kind of manufacture method of SOI integrated circuit structure is characterized in that may further comprise the steps:
A. make and finish the hard mask lithography of upper surface, etching and removing photoresist is formed with the hard mask layer of figure;
B. the etching single crystal silicon layer forms groove, cleans;
C. further etching removal bottom portion of groove insulating material buried regions exposes substrate body silicon materials, cleans;
D. at groove inwall deposit one deck insulating heat-conduction material, anneal;
E. the deposit shallow trench isolation is from silica.
11, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: the etching among the described step b is the plasma dry etching, and etching gas is a halogen gas.
12, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: the etching stopping among the described step b is on the insulating material buried regions.
13, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: the cleaning among the described step b adopts ammonium hydroxide and hydrogen peroxide mixed liquor to clean.
14, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: the etching among the described step c is the plasma dry etching, and etching gas is the carbon fluorine type gas.
15, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: the cleaning among the described step c adopts one or more combinations in standard cleaning program, hydrochloric acid and hydrogen peroxide mixed liquor, ammonium hydroxide and hydrogen peroxide mixed liquor, the dilute hydrofluoric acid to clean.
16, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: the insulating heat-conduction material of deposit is a carborundum in the described steps d.
17, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: high-density plasma chemical vapor deposition or plasma auxiliary chemical vapor deposition are adopted in deposit in the described steps d, and deposited gas is methane and silane.
18, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: deposition parameters is in the described steps d: temperature is 150 ℃～400 ℃, and pressure is 0.001～50 holder, and deposition film thickness is 5～30 nanometers.
19, the manufacture method of SOI integrated circuit structure as claimed in claim 11 is characterized in that: annealing temperature is 800 ℃～1200 ℃ in the described steps d.
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Application publication date: 20070815 |