CN101000597A - IP kernel of embedded Java processor based on AMBA - Google Patents
IP kernel of embedded Java processor based on AMBA Download PDFInfo
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- CN101000597A CN101000597A CN 200710026369 CN200710026369A CN101000597A CN 101000597 A CN101000597 A CN 101000597A CN 200710026369 CN200710026369 CN 200710026369 CN 200710026369 A CN200710026369 A CN 200710026369A CN 101000597 A CN101000597 A CN 101000597A
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Abstract
An IP kernel of embedded Java processor based AMBA bus consists of Java kernel VP6000, AMBA bus unit, storage unit, DMA controller, Ethernet interface and SPI / I2C interface. It is featured as applying 0.25 micron SoC chip of CMOS process and applying stack form structure for enabling to execute Java command directly.
Description
Technical field
The present invention relates to the Embedded Real-Time application, specifically, design a kind of embedded Java processor IP kernel based on the AMBA bus.
Background technology
The java applet travelling speed is slow, consume too much memory resource, this makes it run into some problems in the application of built-in field, this is because Java has adopted virtual machine technique in order to guarantee cross-platform operation characteristic, has the middle layer between Java application and system platform---Java Virtual Machine.The key of operation java applet is to realize Java Virtual Machine by software or hardware mode.
Software solution comprises instant compiler and two kinds of forms of local code compiler.So-called instant compiler is exactly dynamically class methods unknown in the Java bytecode (Bytecode) to be compiled into local code when operation, its major defect is need to consume a large amount of memory resources and have uncertain compilation time to postpone, and this is for resource-constrained and have the embedded system that real-time requires and inapplicable.The local code compiler then is java applet to be compiled become local code before downloading-running, and this disposal route has been lost the plurality of advantages that the Java technology is used in embedded system, is not used widely.
Realizing Java Virtual Machine with hardware, serves as that the processor design is carried out in local instruction with the Java Virtual Machine instruction set, directly moves the Java bytecode program that is generated by standard Java compiler on processor.The special-purpose Java processor that exists on the present domestic and international market, comprise the picoJava series of Sun Microsystems, the Jazelle technology of ARM company and some products such as aJile processor of aJile company, its shortcoming mainly is a hardware cost and power consumption is too high, processor performance is lower, the portability of Java operating system is poor,, construction cycle relatively poor to the software object code compatibility is long etc.
Summary of the invention
At above deficiency, the present invention proposes a kind of embedded Java processor IP kernel based on the AMBA bus, this Java processor IP nuclear adopts storehouse type architecture specially at the needs of Embedded Real-Time application system, makes that it is low in energy consumption, the construction cycle short.Its maximum characteristic do not need to be the support of Java Virtual Machine, just can directly carry out the Java instruction.These instructions meet the Java Virtual Machine standard fully, have developed the portable good advantage of Java language.
Basic structure based on the embedded Java processor IP kernel of AMBA bus comprises Java nuclear VP6000, AMBA bus system, accumulator system and dma controller/Ethernet interface/SPI/I
2C interface.
Described IP kernel is based upon on the AMBA bus basis, adopts the SoC chip of 0.25 micrometre CMOS process, and dominant frequency is that 100MHz, power consumption are less than 100mW.
Described Java nuclear VP6000 is articulated on the AMBA bus system by the ahb bus interface, fetches byte code instruction (Bytecode Instructions), storehouse (Stack A and B) top data and a large amount of control signals (Control Signals) from memory module.
The microprocessor of the full flowing structure of described Java nuclear VP6000 processor adopting, it propose a kind of novelty with the approach of Java command mappings to self micro-code instruction, and micro-code instruction can be finished in the monocycle, and the VP6000 processor core comprises level Four flowing water: get bytecode, get microcode, decoding and execution.
Described IP kernel uses AMBA ahb bus connection processing device nuclear and memory controller and other high-speed cells, adopt the APB bus to provide the simple and easy interconnection of low-power consumption for the low-speed peripheral of system, the bridge between system bus and the peripheral bus provides access agent and the buffering between AHB parts and APB parts.
Described accumulator system comprises normal memory controller (RAM and ROM on NOR Flash, SRAM, SDRAM, the sheet) and NAND FLASH controller.
Described IP kernel makes the message transmission rate of NAND Flash obtain certain raising by the data transfer mode of direct memory access (DMA), has satisfied the designing requirement of practical application.
Described SPI interface is made of SDI (serial data input), SDO (serial data output), SCK (serial-shift clock) and four kinds of signals of CS (from enable signal).
Described I
2The C bus is the universal serial bus that is made of data line SDA and clock SCL, can transmit and receive data, and is used to connect microcontroller and peripherals thereof.
Beneficial effect of the present invention:
1, this IP kernel is a Java processor of developing at the Embedded Real-Time application specially, and maximum characteristic do not need to be the support of Java Virtual Machine, just can directly carry out the Java instruction.These instructions meet the Java Virtual Machine standard fully, have developed the portable good advantage of Java language;
2, CPU nuclear VP6000 is the microprocessor with full flowing structure, and its proposes a kind of with the new method of Java command mappings to self micro-code instruction, and micro-code instruction can be finished in the monocycle.Therefore, Java language is a sophisticated vocabulary, and VP6000 is the microprocessor of reduced instruction set computer;
3, this IP kernel is based upon on the AMBA bus basis, and extensibility is good, can have the IP kernel of AMBA bus interface by compatible other;
4, this IP kernel adopts the SoC chip that 0.25 micrometre CMOS process stream becomes, dominant frequency be 100MHz, power consumption less than 100mW, the construction cycle is short, cost is lower, is fit to drop into middle and low-end market and uses.
Description of drawings
Fig. 1 is the embedded Java processor IP kernel basic block diagram based on the AMBA bus;
Fig. 2 is the embedded Java processor functional framework figure based on the AMBA bus;
Fig. 3 is a VP6000 processor flowing water Organization Chart;
Fig. 4 is the SoC structural drawing based on the AMBA bus.
Embodiment
Below in conjunction with accompanying drawing the present invention is further set forth.
As shown in Figure 1, the basic structure based on the embedded Java processor IP kernel of AMBA bus comprises Java nuclear VP6000, AMBA bus system, accumulator system and dma controller/Ethernet interface/SPI/I
2C interface.This IP kernel is based upon on the AMBA bus basis, and extensibility is good, can have the IP kernel of AMBA bus interface by compatible other.Adopt the SoC chip of 0.25 micrometre CMOS process, dominant frequency be 100MHz, power consumption less than 100mW, the construction cycle is short, cost is lower, is fit to drop into middle and low-end market and uses.
This IP kernel designs CPU IP kernel VP6000, the AMBA bus IP kernel with 4 grades of flowing water, SDRAM, SRAM, NAND FLASH and the NOR FLASH memory interface IP kernel of supporting variable bit width respectively, and Ethernet, SPI and I
2Peripheral Interface IP kernels such as C are designed to complete SoC system, behind checking, test, flow production and finished product test, enter application testing again, finish complete design and manufacturing process.Its functional block diagram as shown in Figure 2.
Each structure division specifies:
1, Java nuclear VP6000
Java nuclear VP6000 can directly move the Java bytecode program that is generated by standard Java compiler.It is articulated on the AMBA bus system by the ahb bus interface, fetches byte code instruction (Bytecode Instructions), storehouse (Stack A and B) top data and a large amount of control signals (Control Signals) from memory module.
The VP6000 processor is the microprocessor of full flowing structure, it propose a kind of novelty with the approach of Java command mappings to self micro-code instruction, and micro-code instruction can be finished in the monocycle.The VP6000 processor core comprises level Four flowing water: get bytecode, get microcode, decoding and execution, as shown in Figure 3.
2, AMBA bus system
This IP kernel uses AMBA ahb bus connection processing device nuclear and memory controller and other high-speed cells, adopts the APB bus that the simple and easy interconnection of low-power consumption is provided for the low-speed peripheral of system.Bridge between system bus and the peripheral bus provides access agent and the buffering between AHB parts and APB parts.
Along with the deep submicron process technology is increasingly mature, the scale of integrated circuit (IC) chip is increasing.The method for designing of numeral IC from driving based on sequential develops into the method for designing based on IP reuse, and obtained widespread use in the SOC design.In the SoC design based on IP reuse, the on-chip bus design is the problem of most critical.For this reason, a lot of on-chip bus standards have appearred in industry.Wherein, the AMBA on-chip bus of being released by ARM company has been subjected to numerous IP developer and SoC system integration person's favor, has become structure on a kind of popular industrial standard sheet.The AMBA standard has mainly comprised AHB (Advanced High performance Bus) system bus and APB (AdvancedPeripheral Bus) peripheral bus.AMBA on-chip bus AMBA 2.0 standards comprise four part: AHB, ASB, APB and Test Methodology.The interconnecting of AHB adopted and traditional had primary module and from the shared bus of module, interface separates with interconnect function, and this is significant to the interconnection between the chip upper module.AMBA has been not only a kind of bus, a kind of especially interconnection system that has interface module.
SOC (system on a chip) based on AMBA; One typically based on the system chart of AMBA bus as shown in Figure 3; Great majority hang over module (the comprising processor) functional module of single attribute just on the bus: primary module or from module.Primary module is to the module of sending read-write operation from module, as CPU, and DSP etc.; From module is the module that takes orders and make a response, as the RAM on the sheet, and AHB/APB bridge etc.In addition, also have some modules to have two kinds of attributes simultaneously, for example direct memory access (DMA) (DMA) is from module when being programmed, but must be primary module when reading to transmit data in system.If there are a plurality of primary modules on the bus, just need moderator to decide and how to control of the visit of various primary modules bus.16 primary modules and a plurality of from module arbitrarily can be arranged, if the primary module number greater than 16, then need add one deck structure again on the ahb bus at most.The APB bridge is a primary module unique on the APB bus, also be on the AHB system bus from module.Its major function is address, data and the control signal that latchs from the AHB system bus, and the selection signal of two-stage decode with generation APB peripherals is provided, thereby realizes the conversion of AHB agreement to the APB agreement.As shown in Figure 4.
3, accumulator system
Accumulator system is used for storing start-up routine, real time operating system and file system.
1) normal memory controller (RAM and ROM on NOR Flash, SRAM, SDRAM, the sheet)
NOR Flash is used for storing start-up routine, microcode table, address offset amount mapping table, classloader and RTOS start-up routine; ROM is used for the stores low level start-up routine on the sheet; RAM is used for dynamic memory microcode table and address offset amount mapping table on the sheet; SRAM is used for storing large-scale java application and system's runtime data; SDRAM and SRAM function class are seemingly.These five kinds of storeies are unified addressing.NOR Flash is 8, and SDRAM is 16, and SRAM and NORFLASH address wire and data line can be multiplexing, compatible 8 and 16.
2) NAND FLASH controller
NAND FLASH is used for storing RTOS and file system, and its effect is similar to the hard disk in the PC.
4, dma controller, Ethernet interface, SPI and I
2C interface
Be the range of application of expansion Java processor, this IP kernel provides dma controller, Ethernet interface, SPI and I
2C interface.
NAND Flash has obtained using widely in modern digital product with the cost performance of its superior characteristic and Geng Gao.Integrated NAND Flash controller becomes a kind of trend in on-chip system chip.This IP kernel makes the message transmission rate of NAND Flash obtain certain raising by the data transfer mode of direct memory access (DMA), has satisfied the designing requirement of practical application.
This IP kernel provides Ethernet interface, to satisfy the network application scope of Java processor.
Serial peripheral interface SPI (Serial Peripheral Interface) is a kind of serial synchronous communication agreement, is made up of a main equipment and one or more slave unit, and main equipment starts a synchronous communication with slave unit, thereby finishes the exchange of data.(serial-shift clock, four kinds of signals of CS (from enable signal) constitute the SPI interface by SDI (serial data input), SDO (serial data output), SCK, CS has determined unique slave unit of communicating by letter with main equipment, as there is not a CS signal, then can only have a slave unit, main equipment is initiated communication by producing shift clock.During communication, data are exported by SDO, the SDI input, and data are exported by SDO at the rising or the negative edge of clock, are read in by SDI in back to back decline or rising edge, like this through the change of 8 or 16 clocks, finish the transmission of 8 or 16 bit data.
I
2The C bus is the universal serial bus that is made of data line SDA and clock SCL, can transmit and receive data, and is used to connect microcontroller and peripherals thereof.Between CPU and the controlled module, carry out two-way transmission between module and the module, various Be Controlled modules all are connected in parallel on this bus, and each module all has unique address, in the transmission of Information process, and I
2On the C bus and each modular circuit that connects be primary controller (or controlled device), be again transmitter (or receiver), this depends on the function that it will be finished.Though each control circuit hangs on same the bus, and is independently of one another, uncorrelated mutually.I
2The C bus has three types of signals in transmitting data procedures, they are respectively: commencing signal, end signal and answer signal.Integrated I on a lot of SIC (semiconductor integrated circuit) is arranged at present
2C interface, a lot of peripheral components such as storer, monitoring chip etc. also provide I
2C interface is so this IP kernel also provides I
2C interface.
Claims (9)
1, a kind of embedded Java processor IP kernel based on the AMBA bus is characterized in that, it mainly comprises Java nuclear VP6000, AMBA bus system, accumulator system and dma controller/Ethernet interface/SPI/I
2C interface.
2, the embedded Java processor IP kernel based on the AMBA bus according to claim 1, it is characterized in that, described IP kernel is based upon on the AMBA bus basis, adopts the SoC chip of 0.25 micrometre CMOS process, and dominant frequency is that 100MHz, power consumption are less than 100mW.
3, the embedded Java processor IP kernel based on the AMBA bus according to claim 1, it is characterized in that, described Java nuclear VP6000 is articulated on the AMBA bus system by the ahb bus interface, fetches byte code instruction (Bytecode Instructions), storehouse (Stack A and B) top data and a large amount of control signals (Control Signals) from memory module.
4, the embedded Java processor IP kernel based on the AMBA bus according to claim 1, it is characterized in that, the microprocessor of the full flowing structure of described Java nuclear VP6000 processor adopting, it propose a kind of novelty with the approach of Java command mappings to self micro-code instruction, and micro-code instruction can be finished in the monocycle, and the VP6000 processor core comprises level Four flowing water: get bytecode, get microcode, decoding and execution.
5, the embedded Java processor IP kernel based on the AMBA bus according to claim 1, it is characterized in that, described IP kernel uses AMBAAHB bus connection processing device nuclear and memory controller and other high-speed cells, adopt the APB bus to provide the simple and easy interconnection of low-power consumption for the low-speed peripheral of system, the bridge between system bus and the peripheral bus provides access agent and the buffering between AHB parts and APB parts.
6, the embedded Java processor IP kernel based on the AMBA bus according to claim 1, it is characterized in that described accumulator system comprises normal memory controller (RAM and ROM on NOR Flash, SRAM, SDRAM, the sheet) and NAND FLASH controller.
7, the embedded Java processor IP kernel based on the AMBA bus according to claim 1, it is characterized in that, described IP kernel is by the data transfer mode of direct memory access (DMA), make the message transmission rate of NAND Flash obtain certain raising, satisfied the designing requirement of practical application.
8, the embedded Java processor IP kernel based on the AMBA bus according to claim 1, it is characterized in that described SPI interface is made of SDI (serial data input), SDO (serial data output), SCK (serial-shift clock) and four kinds of signals of CS (from enable signal).
9, the embedded Java processor IP kernel based on the AMBA bus according to claim 1 is characterized in that described I
2The C bus is the universal serial bus that is made of data line SDA and clock SCL, can transmit and receive data, and is used to connect microcontroller and peripherals thereof.
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100454319C (en) * | 2007-10-15 | 2009-01-21 | 北京航空航天大学 | Micro-processor IP nuclear design method for navigation system |
| CN101790030A (en) * | 2010-03-16 | 2010-07-28 | 中山大学 | Digital set top box based on Java processor |
| CN101797432A (en) * | 2010-03-16 | 2010-08-11 | 中山大学 | Java SoC (System-on-Chip) hand-held game platform |
| CN102546582A (en) * | 2010-12-30 | 2012-07-04 | 中国科学院声学研究所 | Method and system of improving transmission speed of embedded data transmission system |
| CN102567253A (en) * | 2010-12-13 | 2012-07-11 | 深圳市硅格半导体有限公司 | DMA (direct memory access)-based SPI (serial peripheral interface) data transmission method and DMA-based SPI data transmission device |
| CN102782667A (en) * | 2010-03-09 | 2012-11-14 | 高通股份有限公司 | Interconnect coupled to master device via at least two different connections |
| CN102968396A (en) * | 2012-10-30 | 2013-03-13 | 北京华芯微特科技有限公司 | Special data transmission module from flash chip to static random access memory (SRAM) chip |
| CN103171240A (en) * | 2011-12-21 | 2013-06-26 | 北大方正集团有限公司 | Realization method and device of Tiff Download |
| CN103455460A (en) * | 2012-06-01 | 2013-12-18 | 广东新岸线计算机***芯片有限公司 | Device for verifying advanced microcontroller bus interface |
| CN104135410A (en) * | 2014-06-20 | 2014-11-05 | 浙江中控研究院有限公司 | EPA (Ethernet for Plant Automation) communication IP (Intellectual Property) core and system on chip (SOC) based on AMBA (Advanced Microcontroller Bus Architecture) bus structure |
| CN104597832A (en) * | 2014-12-31 | 2015-05-06 | 浙江中控研究院有限公司 | PLC program scheduler IP core based on AMBA bus |
| CN105205018A (en) * | 2015-10-14 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Device and method for controlling read-write of Nand flash internal storage |
| CN107291655A (en) * | 2017-06-14 | 2017-10-24 | 北方电子研究院安徽有限公司 | A kind of SoC bootstrapping IP circuits of band APB EBIs |
| CN108228520A (en) * | 2018-01-10 | 2018-06-29 | 郑州云海信息技术有限公司 | A kind of rapid transmission method of I2C controllers towards BMC |
| CN109801853A (en) * | 2018-12-28 | 2019-05-24 | 上海华岭集成电路技术股份有限公司 | A kind of SOC chip test preferred method |
| CN110865954A (en) * | 2019-11-25 | 2020-03-06 | 南京科远智慧科技集团股份有限公司 | Method for automatically defining variable-length frame end based on DMA (direct memory access) SPI (serial peripheral interface) inter-device communication |
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- 2007-01-17 CN CN 200710026369 patent/CN101000597A/en active Pending
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| CN100454319C (en) * | 2007-10-15 | 2009-01-21 | 北京航空航天大学 | Micro-processor IP nuclear design method for navigation system |
| CN102782667A (en) * | 2010-03-09 | 2012-11-14 | 高通股份有限公司 | Interconnect coupled to master device via at least two different connections |
| CN101790030A (en) * | 2010-03-16 | 2010-07-28 | 中山大学 | Digital set top box based on Java processor |
| CN101797432A (en) * | 2010-03-16 | 2010-08-11 | 中山大学 | Java SoC (System-on-Chip) hand-held game platform |
| CN102567253A (en) * | 2010-12-13 | 2012-07-11 | 深圳市硅格半导体有限公司 | DMA (direct memory access)-based SPI (serial peripheral interface) data transmission method and DMA-based SPI data transmission device |
| CN102546582A (en) * | 2010-12-30 | 2012-07-04 | 中国科学院声学研究所 | Method and system of improving transmission speed of embedded data transmission system |
| CN103171240B (en) * | 2011-12-21 | 2015-02-25 | 北大方正集团有限公司 | Realization method and device of Tiff Download |
| CN103171240A (en) * | 2011-12-21 | 2013-06-26 | 北大方正集团有限公司 | Realization method and device of Tiff Download |
| CN103455460B (en) * | 2012-06-01 | 2017-11-14 | 广东新岸线计算机***芯片有限公司 | A kind of device for verifying Advanced Microcontroller Bus interface |
| CN103455460A (en) * | 2012-06-01 | 2013-12-18 | 广东新岸线计算机***芯片有限公司 | Device for verifying advanced microcontroller bus interface |
| CN102968396A (en) * | 2012-10-30 | 2013-03-13 | 北京华芯微特科技有限公司 | Special data transmission module from flash chip to static random access memory (SRAM) chip |
| CN102968396B (en) * | 2012-10-30 | 2016-06-29 | 佛山华芯微特科技有限公司 | Dedicated data transmission module from Flash chip to sram chip |
| CN104135410A (en) * | 2014-06-20 | 2014-11-05 | 浙江中控研究院有限公司 | EPA (Ethernet for Plant Automation) communication IP (Intellectual Property) core and system on chip (SOC) based on AMBA (Advanced Microcontroller Bus Architecture) bus structure |
| CN104597832A (en) * | 2014-12-31 | 2015-05-06 | 浙江中控研究院有限公司 | PLC program scheduler IP core based on AMBA bus |
| CN104597832B (en) * | 2014-12-31 | 2017-04-19 | 浙江中控研究院有限公司 | PLC program scheduler IP core based on AMBA bus |
| CN105205018A (en) * | 2015-10-14 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Device and method for controlling read-write of Nand flash internal storage |
| CN107291655A (en) * | 2017-06-14 | 2017-10-24 | 北方电子研究院安徽有限公司 | A kind of SoC bootstrapping IP circuits of band APB EBIs |
| CN107291655B (en) * | 2017-06-14 | 2020-10-09 | 北方电子研究院安徽有限公司 | SoC bootstrap IP circuit with APB bus interface |
| CN108228520A (en) * | 2018-01-10 | 2018-06-29 | 郑州云海信息技术有限公司 | A kind of rapid transmission method of I2C controllers towards BMC |
| CN108228520B (en) * | 2018-01-10 | 2020-06-16 | 苏州浪潮智能科技有限公司 | BMC-oriented I2C controller fast transmission method |
| CN109801853A (en) * | 2018-12-28 | 2019-05-24 | 上海华岭集成电路技术股份有限公司 | A kind of SOC chip test preferred method |
| CN109801853B (en) * | 2018-12-28 | 2021-02-09 | 上海华岭集成电路技术股份有限公司 | SOC chip testing method |
| CN110865954A (en) * | 2019-11-25 | 2020-03-06 | 南京科远智慧科技集团股份有限公司 | Method for automatically defining variable-length frame end based on DMA (direct memory access) SPI (serial peripheral interface) inter-device communication |
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