CN100594677C - Power level shift circuit - Google Patents
Power level shift circuit Download PDFInfo
- Publication number
- CN100594677C CN100594677C CN200810107903A CN200810107903A CN100594677C CN 100594677 C CN100594677 C CN 100594677C CN 200810107903 A CN200810107903 A CN 200810107903A CN 200810107903 A CN200810107903 A CN 200810107903A CN 100594677 C CN100594677 C CN 100594677C
- Authority
- CN
- China
- Prior art keywords
- coupled
- voltage
- transistor
- level
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
A level shift circuit which is used for increasing the voltage level of an input signal comprises a voltage dividing circuit and a buffer circuit. The voltage dividing circuit is coupled to the inputsignal and is used for outputting a first voltage signal according to the input signal. The voltage dividing circuit comprises a first load which is coupled between a first supply voltage and a firstnode, and a second load which is coupled between the input end and the first node. The buffer circuit is coupled to the first node and is used for increasing the voltage level of the first voltage signal to form a second voltage signal and outputting a second voltage signal. The level shift circuit according to the invention adopts an active load for operation as the active load can reduce the requirement of the threshold voltage (VTH). Therefore the level shift circuit of the invention can increase the operation stability of the circuit and at the same time increase the operation speed of thecircuit.
Description
Technical field
The present invention relates to a kind of level shift circuit, refer to a kind of especially critical voltage (V
TH) level shift circuit of the low and suitable low input of sensitiveness operation.
Background technology
Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and wherein LCD has been various electronic equipments such as TV, mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or the extensive use of laptop screen institute gradually.(LowTemperature Poly-Silicon, LTPS) LCD is the main flow of present consumer products exploitation to low temperature polycrystalline silicon, is mainly used in height integration characteristic and high image quality display.
See also Fig. 1, Fig. 1 is the functional block diagram of the source electrode driver of prior art.Source electrode driver 10 comprises an output-stage circuit 161, a digital analog converter 162, a level shift circuit 163, a data latching device 164, a data buffer 165 and a shift registor 166.Shift registor 166 is to be used for that translation is from the outside shift pulse of coming in that transmits continuously according to the pulse of clock pulse signal CLK, and 165 of data buffers are stored according to the shift clock impulsive synchronization ground of shift registor 166 each outputs output data-signal D00P/N～D02P/N, D10P/N～D102P/N, the D20P/N～D22P/N with input.164 of data latching devices be with the data-signal breech lock of data buffer 165 certain during after again in same time output.163 of level shift circuits are the voltage levels that is used for promoting 164 outputs of data latching device.Digital analog converter 162 is that the data-signal with numeral converts corresponding simulating voltage to.Control signal STB is feed-in data latching device 164 and output-stage circuit 161 respectively, and when control signal STB was the rising edge, data were by data buffer 165 feed-in data latching devices 164; When control signal STB is the drop edge, export aanalogvoltage to each data wire to be used for promoting the pixel of display panels by output-stage circuit 161.
See also Fig. 2, Fig. 2 is the circuit diagram of the level shift circuit 163 of prior art.Though the LCD that the LTPS manufacture process is produced can be with circuit integrated on display glass, the element uniformity and the stability of LTPS manufacture process all have great variation property, especially transistorized critical voltage (V
TH) very big to the influence of circuit characteristic with electron transfer rate (μ), so become a kind of challenge of height on the circuit design skill.Be usually used in improving the level shift circuit 163 of voltage level at present owing to can't satisfy design and go up, cause level shift circuit 163 operations to be gone up occurring serious delay phenomenon or can't correct operation for the demand of low-voltage and relatively poor transistor characteristic.
Summary of the invention
In view of this, the present invention proposes a kind ofly can resist high critical voltage (V
TH) level shift circuit, to improve the normal running of Circuits System, therefore solved prior art problems.
The invention provides a kind of level shift circuit, be used for promoting the voltage level of an input signal, it comprises a bleeder circuit and a buffer circuit.This bleeder circuit is coupled to this input signal, be used for exporting one first voltage signal according to this input signal, it comprises first load that is coupled between one first supply voltage and the first node, and is coupled to second load between this input and this first node.This buffer circuit is coupled to this first node, and the voltage level that is used for promoting this first voltage signal to be forming one second voltage signal, and exports this second voltage signal.
According to one embodiment of the invention, this first load is a resistive element, and this second load is a resistive element.
According to another embodiment of the present invention, this first load be a P-type mos element (P-type metal oxide semiconductor, PMOS).This second load be a N type metal oxide semiconductor element (N-type metal oxide semiconductor, NMOS).One grid of this P-type mos element is coupled to a second source voltage, and a grid of this P-type mos element is coupled to this anti-phase input signal.One grid of this N type metal oxide semiconductor element is coupled to this first supply voltage.
According to above-mentioned level shift circuit, wherein this buffer circuit comprises two inverters.
Another embodiment of the present invention provides a kind of level shift circuit, be used for promoting the voltage level of an input signal, it comprises one first inverter, one first level adjusting circuit, one second level adjusting circuit, a first transistor, a transistor seconds and one second inverter.This first inverter is coupled to input signal, is used for exporting one first voltage signal according to this input signal.This first level adjusting circuit couples this first inverter, is used for adjusting average voltage level to one first level of this first voltage signal.This second level adjusting circuit couples this first inverter, is used for promoting average voltage level to one second level of this first voltage signal.The grid of this first transistor is coupled to this first level adjusting circuit, and the source electrode of this first transistor is coupled to one first supply voltage.The grid of this transistor seconds is coupled to this second level adjusting circuit, and the source electrode of this transistor seconds is coupled to a second source voltage.This second inverter is coupled to the drain electrode of this first transistor and the drain electrode of this transistor seconds.
Embodiments of the invention also comprise a voltage stabilizing circuit, and this voltage stabilizing circuit is coupled between this input signal and this first inverter, are used for fixing the voltage level of this input signal.This voltage stabilizing circuit comprises an electric capacity, one first resistive element and one second resistive element, this first resistive element is coupled between this first supply voltage and this first inverter, this second resistive element is coupled between this second source voltage and this first inverter, and this electric capacity is coupled between this first inverter and this input signal.
According to above-mentioned level shift circuit, wherein this first level adjusting circuit comprises the 3rd transistor and the 4th transistor, and the 3rd transistor is the P-type mos element, and the 4th transistor is a N type metal oxide semiconductor element.
According to above-mentioned level shift circuit, wherein the 3rd transistorized grid is coupled to this first voltage signal, the 3rd transistorized source electrode is coupled to this first supply voltage, the 3rd transistor drain is coupled to the grid of this first transistor, the 4th transistorized grid is coupled to this first supply voltage, the 4th transistorized source electrode is coupled to this input signal, and the 4th transistor drain is coupled to the grid of this first transistor.
According to above-mentioned level shift circuit, wherein this second level adjusting circuit comprises the 5th transistor and the 6th transistor, and the 5th transistor is the P-type mos element, and the 6th transistor is a N type metal oxide semiconductor element.
According to above-mentioned level shift circuit, wherein the 5th transistorized grid is coupled to this second source voltage, the 5th transistorized source electrode is coupled to this input signal, the 5th transistor drain is coupled to the grid of this transistor seconds, the 6th transistorized grid is coupled to this first voltage signal, the 6th transistorized source electrode is coupled to this second source voltage, and the 6th transistor drain is coupled to the grid of this transistor seconds.
Level shift circuit of the present invention adopts active load to operate, because active load can reduce critical voltage (V
TH) demand.Therefore, level shift circuit of the present invention can improve circuit operation stability, can increase circuit operation speed simultaneously.
Description of drawings
Fig. 1 is the functional block diagram of the source electrode driver of prior art.
Fig. 2 is the circuit diagram of the level shift circuit of prior art.
Fig. 3 is the functional block diagram of level shift circuit of the present invention.
Fig. 4 is the equivalent circuit diagram of the level shift circuit of first embodiment of the invention.
Fig. 5 is the signal waveforms of the level shift circuit of Fig. 4.
Fig. 6 A is the equivalent circuit diagram of the level shift circuit of second embodiment of the invention.
Fig. 6 B is the equivalent circuit diagram of the level shift circuit of third embodiment of the invention.
Fig. 7 is the signal waveforms of the level shift circuit of Fig. 6 A and Fig. 6 B.
Fig. 8 is the equivalent circuit diagram of the level shift circuit of fourth embodiment of the invention.
Fig. 9 is the signal waveforms of the level shift circuit of Fig. 8.
Figure 10 is the equivalent circuit diagram of the level shift circuit of fifth embodiment of the invention.
Wherein, description of reference numerals is as follows:
10 source electrode drivers, 100,200 level shift circuits
102,202 bleeder circuits, 104,204 buffer circuits
106,108 loads of 161 output-stage circuits
162 digital analog converters, 163 level shift circuits
164 data latching devices, 165 data buffers
166 shift registors, 306,308 level adjusting circuits
206 PMOS 208 NMOS
INV inverter INV1, INV2 inverter
T1-T6 transistor 200 ', 300 ' level shift circuit
310 voltage stabilizing circuits, 315 electric capacity
312 first resistive elements, 314 second resistive elements
Embodiment
See also Fig. 3, Fig. 3 is the functional block diagram of level shift circuit 100 of the present invention.Level shift circuit 100 can be applicable within the source electrode driver of LCD, in order to promote the voltage level of input signal.Level shift circuit 100 comprises a bleeder circuit 102 and a buffer circuit 104.Bleeder circuit 102 is coupled to input I, is used for receiving inputted signal, and is used for according to input signal to export one first voltage signal in first node P.Bleeder circuit 102 comprises one first load 106 and one second load, 108, the first loads 106 are coupled to the first supply voltage V
DDAnd between the first node P.Second load 108 is coupled between input I and the first node P.Buffer circuit 104 is coupled to first node P, and the voltage level that is used for promoting first voltage signal to be forming one second voltage signal, and exports this second voltage signal in output O.
See also Fig. 4 and Fig. 5, Fig. 4 is the equivalent circuit diagram of the level shift circuit 100 of first embodiment of the invention, and Fig. 5 is the signal waveforms of the level shift circuit 100 of Fig. 4.The purpose of level shift circuit 100 is to make the gap of high and low voltage level of voltage of input signal more obvious.For instance, the high and low voltage level of input signal is respectively Vcc and earthed voltage GND, and then the purpose of level shift circuit 100 is to make the high and low voltage level of its output be respectively V
DDAnd earthed voltage GND.Buffer circuits 104 comprises two reverser INV, and the maximum of each reverser INV and minimum operation voltage are respectively supply voltage V
DDAnd earthed voltage GND.In order to allow level shift circuit 100 boosted voltage level not be subjected to transistor critical voltage V
THInfluence is so first load 106 of bleeder circuit 102 and second load 108 all are the resistance-type loads.The first voltage signal V of node P output
PWith the first supply voltage V
DDWith input signal V
IRelation as follows:
That is to say the first voltage signal V
PHigh-voltage level equal
Low voltage level equals
Utilize buffer circuit 104 with the first voltage signal V at last
PHigh and low voltage level be adjusted to V
DD, GND.
In design, need be with the first voltage signal V of node P
PAverage center voltage level be adjusted to
Just can make buffer circuit 104 last high and low voltage levels be adjusted to V
DD, GND output.Because V
PHigh-voltage level-V
PCenter voltage level=V
PCenter voltage level-V
PLow voltage level, so:
Wherein
R
1The ohmic load value of representing first load 106, R
2The ohmic load value of representing second load 108.
So the relation of first load 106 and second load 108 is as follows:
See also Fig. 6 A and Fig. 7, Fig. 6 A is the equivalent circuit diagram of the level shift circuit 200 of second embodiment of the invention, and Fig. 7 is the signal waveforms of the level shift circuit 200 of Fig. 6 A.The bleeder circuit 202 of level shift circuit 200 comprises first load and second load, first load is a P-type mos element (P-type metal oxide semiconductor, PMOS) 206, second load is a N type metal oxide semiconductor element (N-type metal oxide semiconductor, NMOS) 208.The source electrode of PMOS 206 is coupled to supply voltage V
DD, grid is coupled to anti-phase input signal I, and drain electrode is coupled to node P.The drain electrode of NMOS 208 is coupled to node P, and grid is coupled to supply voltage V
DD, source electrode is coupled to input signal I.Buffer circuits 204 comprises two reverser INV, and the maximum of each reverser INV and minimum operation voltage are respectively supply voltage V
DDAnd earthed voltage GND.Because two loads 206,208 of bleeder circuit 202 all are active loads, the resistance value of PMOS element 206
μ wherein
PBe hole mobility, W
PBe grid width, the L of PMOS 206
PBe the grid length of PMOS 206, and C
OxPThen be the specific capacitance size of the grid oxic horizon of PMOS 206, V
SGBe the pressure reduction between source electrode and grid, V
THpIt is the critical voltage of PMOS 206.Relatively, the resistance value of NMOS element 208
μ wherein
NBe electron mobility, W
NBe grid width, the L of NMOS 208
NBe the grid length of NMOS 208, and C
OxNThen be the specific capacitance size of the grid oxic horizon of NMOS 208, V
GSBe the pressure reduction between grid and source electrode, V
THnIt is the critical voltage of NMOS 208.That is to say, work as μ
P, W
P, L
P, C
OxP, V
THp, μ
N, W
N, L
N, C
OxN, V
THnDuring for constant, the resistance value R of PMOS element 206 and NMOS element 208
P, R
NCan change along with the variation of operating voltage (pressure reduction between grid and source electrode just).For instance, when output signal I was in high-voltage level Vcc, then anti-phase input signal I was in low voltage level, so the resistance value R of PMOS element 206
PHBe
The resistance value P of NMOS element 208
NHBe
Relatively, when output signal I was in low voltage level GND, then anti-phase input signal I was in high-voltage level Vcc, so the resistance value R of PMOS element 206
PLBe
The resistance value R of NMOS element 208
NLBe
That is to say the first voltage signal V
PHigh-voltage level equal
Low voltage level equals
Utilize buffer circuit 204 with the first voltage signal V at last
PHigh and low voltage level be adjusted to V
DD, GND.
In design, need be with the first voltage signal V of node P
PAverage center voltage level be adjusted to
, just can make buffer circuit 204 last high and low voltage levels be adjusted to V
DD, GND output.Because V
PHigh-voltage level-V
PCenter voltage level=V
PCenter voltage level-V
PLow voltage level, so
Wherein
Therefore
Equation 2
In addition: a
H=κ a
L, wherein
Equation 3
At last, as long as suitably adjust to satisfy equation 2 and equation 3, the PMOS element 206 that can choose suitable grid length-width ratio and NMOS element 208 are to form bleeder circuit 202.
See also Fig. 6 B, Fig. 6 B is the equivalent circuit diagram of the level shift circuit of third embodiment of the invention.The level shift circuit 200 ' of Fig. 6 B and the level shift circuit 200 of Fig. 6 A have the element of same numeral, and its function unanimity is so repeat no more.In the third embodiment of the present invention, the grid of the PMOS element 206 of level shift circuit 200 ' also can be coupled to earthed voltage GND, and noninverting input signal I also can reach level shift circuit 200 similar effects with second embodiment shown in Fig. 6 A.But its design also need be satisfied the condition of equation 2 and equation 3.
See also Fig. 8 and Fig. 9, Fig. 8 is the equivalent circuit diagram of the level shift circuit 300 of fourth embodiment of the invention, and Fig. 9 is the signal waveforms of the level shift circuit 300 of Fig. 8.The first inverter INV1 of level shift circuit 300 is coupled to input signal I, is used for according to the anti-phase input signal I (i.e. first voltage signal) of input signal I output.First level adjusting circuit 306 couples the first inverter INV1, be used for adjusting average voltage level to one first level of the first voltage signal I, and second level adjusting circuit 308 couples the first inverter INV1, is used for adjusting average voltage level to one second level of the first voltage signal I.The grid of the first transistor T1 is coupled to first level adjusting circuit 306, and source electrode is coupled to the first supply voltage V
DD(can be 2Vcc) at present embodiment.The grid of transistor seconds T2 is coupled to second level adjusting circuit 308, and the source electrode of transistor seconds T2 is coupled to second source voltage V
SS(can be at present embodiment-Vcc).The second inverter INV2 is coupled to the drain electrode of the first transistor T1 and the drain electrode of transistor seconds T2.
First level adjusting circuit 306 comprises one the 3rd transistor T 3 and one the 4th transistor T, 4, the three transistor Ts 3 are P-type mos elements, and the 4th transistor T 4 is N type metal oxide semiconductor elements.The grid of transistor T 3 is coupled to the first voltage signal I, and the source electrode of transistor T 3 is coupled to the first supply voltage V
DD, the drain electrode of transistor T 3 is coupled to the grid of transistor T 1, and the grid of transistor T 4 is coupled to supply voltage V
DD, the source electrode of transistor T 4 is coupled to input signal I, and the drain electrode of transistor T 4 is coupled to the grid of the first transistor T1.Second level adjusting circuit 308 comprises one the 5th transistor T 5 and one the 6th transistor T, 6, the five transistor Ts 5 are P-type mos elements, and the 6th transistor T 6 is N type metal oxide semiconductor elements.The grid of transistor T 5 is coupled to second source voltage V
SS, the source electrode of transistor T 5 is coupled to input signal I, and the drain electrode of transistor T 5 is coupled to the grid of transistor seconds T2.The grid of transistor T 6 is coupled to the first voltage signal I, and the source electrode of transistor T 6 is coupled to second source voltage V
SS, the drain electrode of transistor T 6 is coupled to the grid of transistor seconds T2.
The level shift circuit 200 of the operation principles of level shift circuit 300 and Fig. 6 A and the level shift circuit 200 ' of Fig. 6 B are similar.For instance, first level adjusting circuit 306 and the first inverter INV1 are equivalent to the bleeder circuit 202 of the level shift circuit 200 of Fig. 6 A, are used for the average voltage level of the first voltage signal I is pulled up to the first level Vcc (as the node P of Fig. 9
UWaveform shown in).Relatively, second level adjusting circuit 308 and the first inverter INV1 are equivalent to the bleeder circuit 202 of the level shift circuit 200 ' of Fig. 6 B, are used for the average voltage level of the first voltage signal I is adjusted downward to second level (as the node P of Fig. 9
DWaveform shown in).Next utilize the first transistor T1, transistor seconds T2 and the second inverter INV2 waveform adder with first level adjusting circuit 306 and 308 outputs of second level adjusting circuit, so the amplitude of wave form by second inverter INV2 output is approximately 3Vcc at last, the amplitude of wave form of exporting than the level shift circuit of previous embodiment (2Vcc) is big.
See also Figure 10, Figure 10 is the equivalent circuit diagram of the level shift circuit 300 ' of fifth embodiment of the invention.Level shift circuit 300 ' and level shift circuit 300 have the element of same numeral, and its function unanimity is so repeat no more.Both difference are that level shift circuit 300 ' also comprises a voltage stabilizing circuit 310, and voltage stabilizing circuit 310 is coupled between the input signal I and the first inverter INV1, are used for fixing the voltage level of input signal I.Voltage stabilizing circuit 310 comprises an electric capacity 316, one first resistive element 312 and one second resistive element 314, first resistive element 312 is coupled between the first supply voltage VDD and the first inverter INV1, second resistive element 314 is coupled between the second source voltage VSS and the first inverter INV, and electric capacity 316 is coupled between the first inverter INV1 and the input signal I.
Compared to prior art, traditional level shift circuit adopts the switch switching operation modes, and therefore whether transistorized conducting depends on the size of critical voltage.When critical voltage is higher, the normal running that circuit is increased even jeopardizes in switch internal resistance meeting.But level shift circuit of the present invention adopts active load to operate, because active load can reduce critical voltage (V
TH) demand.Therefore level shift circuit of the present invention can improve circuit operation stability, can increase circuit operation speed simultaneously.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; any general technical staff of the technical field of the invention; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the claim scope person of defining who encloses.
Claims (16)
1. level shift circuit is used for promoting the voltage level of input signal, and it comprises:
Bleeder circuit is coupled to this input signal, is used for exporting first voltage signal according to this input signal, and it comprises:
First load is coupled between first supply voltage and the first node; And
Second load is coupled between this input and this first node; And
Buffer circuit is coupled to this first node, and the voltage level that is used for promoting this first voltage signal to be forming second voltage signal, and exports this second voltage signal.
2. level shift circuit as claimed in claim 1, wherein this first load is a resistive element.
3. level shift circuit as claimed in claim 1, wherein this second load is a resistive element.
4. level shift circuit as claimed in claim 1, wherein this first load is the P-type mos element.
5. level shift circuit as claimed in claim 4, wherein the grid of this P-type mos element is coupled to second source voltage.
6. level shift circuit as claimed in claim 4, wherein the grid of this P-type mos element is coupled to this anti-phase input signal.
7. level shift circuit as claimed in claim 1, wherein this second load is a N type metal oxide semiconductor element.
8. level shift circuit as claimed in claim 7, wherein the grid of this N type metal oxide semiconductor element is coupled to this first supply voltage.
9. level shift circuit as claimed in claim 1, wherein this buffer circuit comprises two inverters.
10. level shift circuit is used for promoting the voltage level of input signal, and it comprises:
First inverter is coupled to this input signal, is used for exporting first voltage signal according to this input signal;
First level adjusting circuit couples this first inverter, is used for adjusting average voltage level to the first level of this first voltage signal;
Second level adjusting circuit couples this first inverter, is used for promoting average voltage level to the second level of this first voltage signal;
The first transistor, it comprises grid and source electrode, and the grid of this first transistor is coupled to this first level adjusting circuit, and the source electrode of this first transistor is coupled to first supply voltage;
Transistor seconds, it comprises grid and source electrode, and the grid of this transistor seconds is coupled to this second level adjusting circuit, and the source electrode of this transistor seconds is coupled to second source voltage; And
Second inverter is coupled to the drain electrode of this first transistor and the drain electrode of this transistor seconds.
11. level shift circuit as claimed in claim 10, wherein this first level adjusting circuit comprises the 3rd transistor and the 4th transistor, the 3rd transistor is the P-type mos element, and the 4th transistor is a N type metal oxide semiconductor element.
12. level shift circuit as claimed in claim 10, wherein the 3rd transistorized grid is coupled to this first voltage signal, the 3rd transistorized source electrode is coupled to this first supply voltage, the 3rd transistor drain is coupled to the grid of this first transistor, the 4th transistorized grid is coupled to this first supply voltage, the 4th transistorized source electrode is coupled to this input signal, and the 4th transistor drain is coupled to the grid of this first transistor.
13. level shift circuit as claimed in claim 10, wherein this second level adjusting circuit comprises the 5th transistor and the 6th transistor, the 5th transistor is the P-type mos element, and the 6th transistor is a N type metal oxide semiconductor element.
14. level shift circuit as claimed in claim 13, wherein the 5th transistorized grid is coupled to this second source voltage, the 5th transistorized source electrode is coupled to this input signal, the 5th transistor drain is coupled to the grid of this transistor seconds, the 6th transistorized grid is coupled to this first voltage signal, the 6th transistorized source electrode is coupled to this second source voltage, and the 6th transistor drain is coupled to the grid of this transistor seconds.
15. level shift circuit as claimed in claim 10, it also comprises voltage stabilizing circuit, and this voltage stabilizing circuit is coupled between this input signal and this first inverter, is used for fixing the voltage level of this input signal.
16. level shift circuit as claimed in claim 15, wherein this voltage stabilizing circuit comprises electric capacity, first resistive element and second resistive element, this first resistive element is coupled between this first supply voltage and this first inverter, this second resistive element is coupled between this second source voltage and this first inverter, and this electric capacity is coupled between this first inverter and this input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810107903A CN100594677C (en) | 2008-05-21 | 2008-05-21 | Power level shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810107903A CN100594677C (en) | 2008-05-21 | 2008-05-21 | Power level shift circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101277108A CN101277108A (en) | 2008-10-01 |
| CN100594677C true CN100594677C (en) | 2010-03-17 |
Family
ID=39996171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810107903A Active CN100594677C (en) | 2008-05-21 | 2008-05-21 | Power level shift circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100594677C (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102859877B (en) * | 2010-05-24 | 2015-01-07 | 松下电器产业株式会社 | Level shifter and semiconductor integrated circuit provided with same |
| JP2013115621A (en) * | 2011-11-29 | 2013-06-10 | Seiko Epson Corp | Level shifter circuit, integrated circuit device, and electronic clock |
| CN105609069B (en) * | 2016-01-04 | 2018-07-06 | 京东方科技集团股份有限公司 | Level shifting circuit, driving circuit and display device |
| CN108932006B (en) * | 2017-05-26 | 2020-04-10 | 新唐科技股份有限公司 | Level conversion circuit |
| CN107896103B (en) * | 2017-12-21 | 2021-12-03 | 广东美的制冷设备有限公司 | Level switching circuit and integrated circuit chip and air conditioner comprising same |
| US10411678B2 (en) * | 2018-02-12 | 2019-09-10 | Semiconductor Components Industries, Llc | Level-shifting circuit configured to limit leakage current |
| KR20210074846A (en) * | 2019-12-12 | 2021-06-22 | 에스케이하이닉스 주식회사 | Memory device and memory system having input circuit |
-
2008
- 2008-05-21 CN CN200810107903A patent/CN100594677C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101277108A (en) | 2008-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100594677C (en) | Power level shift circuit | |
| TWI439051B (en) | Level converting flip-flop and method of operating the same | |
| US7006068B2 (en) | Sampling level converter circuit, 2-phase and multiphase expanding circuit, and display device | |
| US8102357B2 (en) | Display device | |
| TWI469150B (en) | Shift register circuit | |
| US7710182B2 (en) | Reliable level shifter of ultra-high voltage device used in low power application | |
| KR101989721B1 (en) | Liquid crystal display device and gate driver thereof | |
| JP2018511071A (en) | GOA circuit and liquid crystal display | |
| CN101154941B (en) | Level shifter with reduced power consumption | |
| US8648849B2 (en) | Buffer circuit | |
| US9928793B2 (en) | Scanning driving circuit | |
| KR20170005291A (en) | Output buffer circuit controling selw slope and source driver comprising the same and method of generating the source drive signal thereof | |
| JPWO2009081619A1 (en) | Buffer and display device | |
| US9721526B2 (en) | Display driver with small-area level shift circuit | |
| CN109658888B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| US9171641B2 (en) | Shift register circuit and driving method thereof | |
| US7791398B2 (en) | Level shift circuit | |
| Chen et al. | An 18.6-μm-pitch gate driver using a-IGZO TFTs for ultrahigh-definition AR/VR displays | |
| KR101532271B1 (en) | Low power and high speed level shifter | |
| EP2011236B1 (en) | Electronic circuit | |
| US9454945B2 (en) | Scanning circuit and display device | |
| US20170264296A1 (en) | Pre-driver for driving low voltage differential signaling (lvds) driving circuit | |
| CN108781071B (en) | Square wave generating method and square wave generating circuit | |
| CN101986379B (en) | Pulse output circuit | |
| JP6730213B2 (en) | Semiconductor circuit and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |