CN100594558C - Displacement register and control method thereof - Google Patents

Displacement register and control method thereof Download PDF

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CN100594558C
CN100594558C CN200810090975A CN200810090975A CN100594558C CN 100594558 C CN100594558 C CN 100594558C CN 200810090975 A CN200810090975 A CN 200810090975A CN 200810090975 A CN200810090975 A CN 200810090975A CN 100594558 C CN100594558 C CN 100594558C
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signal
shifting deposit
deposit unit
clock pulse
output signal
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CN101252022A (en
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郑国兴
谢曜任
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AU Optronics Corp
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AU Optronics Corp
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Abstract

The present invention discloses a shift register and a control method thereof, wherein the shift register comprises continuously and serially connected shift registering units. Each shift registeringunit is controlled by a first clock pulse signal and a second clock pulse signal to generate an output signal. In each shift registering unit, a first driving device drives, during a valid period andaccording to a first input signal, a first switch device to activate an output signal. A second driving device drives, during the valid period and according the first clock pulse signal, the first switch device by a voltage signal to inactivate the output signal. When the first switch device inactivates the output signal, a second switch device outputs the voltage signal as an output signal according to the second clock pulse signal. During the valid period, the voltage signal has low level, while the first clock pulse signal and the second clock pulse signal are opposite phase alternating current signals mutually. During a blanking period, the voltage signal has high level, while the first clock pulse signal and the second clock pulse signal are direct current signals.

Description

Shift register and control method thereof
Technical field
The present invention relates to a kind of shift register, particularly a kind of control method of shift register is offset in order to bucking voltage.
Background technology
In the present display panels design, produce sweep signal and data-signal with gate drivers and source electrode driver.In order to reduce cost, the circuit effect shift register identical with gate drivers is set on glass substrate then.But, therefore, after display panel is lighted,, transistor cause panel to show that generation is unusual because being subjected to stress (stress) influence because mostly shift register is to adopt the technology of amorphous silicon membrane technology.
Fig. 1 represents the shifting deposit unit of known shift register.Fig. 2 represents the signal timing diagram of known shifting deposit unit.Consult Fig. 1 and Fig. 2, shifting deposit unit 1 is controlled by anti-phase each other clock pulse signal CK and XCK, and couples low-voltage source Vss.Shifting deposit unit 1 receives the output signal S of previous stage N-1And the output signal S of back one-level N+1, and produce output signal S NIn time point P10, output signal S N-1(promptly being in high level) and transistor T 10 conductings are activated (activated).The voltage V of node N10 N10According to output signal S N-1And become high level, with turn-on transistor T11 and transistor T 12.At this moment, because clock pulse signal CK is in low level and transistor T 12 conductings, so the voltage V of node N11 N11For low level to close transistor T 13.In addition, the clock pulse signal XCK of high level then turn-on transistor T15 so that output signal S N(promptly being in low level) is not activated (de-activate).
In time point P11, output signal S N-1Be not activated, therefore transistor T 10 closes.Clock pulse signal CK becomes high level.During time point P11 to P12, the clock pulse signal CK of high level is coupled to node N10 by capacitor C10 and transistor T 13, makes the voltage V of node N10 N10Be changed to higher level along with the level of clock pulse signal CK, with turn-on transistor T11 and transistor T 12.The transistor T 12 of voltage source V ss by conducting is so that the voltage V of node N11 N11Be in low level, and close transistor T 13.The clock pulse signal CK of high level then is sent to output node N12 with as output signal S by transistor T 11 NIn other words, output signal S NBe activated.The low level voltage of voltage source V ss is sent to node N11 by transistor T 12, makes voltage V N11Still be in low level.In addition, because low level clock pulse signal XCK closes transistor T 15 and low level voltage V N11Close transistor T 16, can keep output signal S thus NState of activation.
In time point P12, clock pulse signal CK becomes low level, and output signal S N+1Be activated with turn-on transistor T14.The voltage V of node N10 N10Descend gradually according to low-voltage source Vss, to close transistor T 11 and transistor T 12.At this moment, the clock pulse signal XCK turn-on transistor T15 of high level, make the voltage of low-voltage source Vss provide to output node N12 with as output signal S NIn other words, output signal S NBecome the state that is not activated.
In time point P13, clock pulse signal CK becomes high level, makes the voltage V of node N11 N11Become high level, with turn-on transistor T13.Therefore, the voltage V of node N10 N10Maintain low level.In addition, the voltage V of high level N11Turn-on transistor T16 is so that output signal S NMaintain the state that is not activated.After time point P13,1 of shifting deposit unit is according to clock pulse signal CK and XCK and operate.The voltage V of node N11 N11Between high level and low level, switch.
The high level of supposing clock pulse signal CK is 15V, and low level is-9V, and the voltage that voltage source V ss provides is-7V.When time clock signal CK was in high level with turn-on transistor T13, the grid of transistor T 13 and the voltage difference of source electrode were 22V.When the gate source voltage (Vgs) of transistor T 13 was in this positive bias stress for a long time, the critical voltage of transistor T 13 was offset, and made voltage V N10And voltage V N11Unusually, shown in the dotted lines of Fig. 2.Similarly, the gate source voltage of transistor T 11, T12, T14, T15, T16 also has the problem of the critical voltage skew that produces because be in this positive bias stress for a long time.When skew took place the transistorized critical voltage of shifting deposit unit 1,1 of shifting deposit unit can't normal operation, and then causes exporting incorrect output signal S N
Summary of the invention
The invention provides a kind of shift register, its operate in the valid period and hide from view during and comprise a plurality of shifting deposit units of continuous serial connection.Each shifting deposit unit is subjected to first clock pulse signal and the control of second clock pulse signal to produce output signal, and this output signal periodically be activated (activated), wherein, each shifting deposit unit comprises first and second switchgear and first and second drive unit.First switchgear provides output signal by output node.First drive unit the valid period according to first input signal, to drive the first switchgear sense activation signal.Second drive unit couples a voltage signal, in order to the valid period according to first clock pulse signal, do not activate (de-activated) output signal to drive first switchgear by voltage signal.The second switch device couples voltage signal, when first switchgear not during sense activation signal, according to the second clock pulse signal so that voltage signal is provided to output node.In the valid period, voltage signal has a low level, and first and second clock pulse signal is two anti-phase each other AC signal.During hiding from view, voltage signal has a high level, and each signal of first and second clock pulse signal is a direct current signal.
The present invention also provides a kind of shift register, comprises a plurality of shifting deposit units of continuous serial connection.Each shifting deposit unit is subjected to the control of the first anti-phase each other clock pulse signal and second clock pulse signal producing output signal, and output signal periodically be activated (activated).Each shifting deposit unit comprises first and second switchgear and first and second drive unit.First switchgear provides output signal by output node.First drive unit is according to first input signal, to drive the first switchgear sense activation signal.Second drive unit couples the second clock pulse signal, and according to first clock pulse signal, transmission second clock pulse signal drives first switchgear makes first switchgear not activate (de-activated) this output signal.The second switch device couples voltage signal, when first switchgear not during sense activation signal, according to the second clock pulse signal voltage signal is provided to output node.
The present invention provides a kind of control method of shift register again, is applicable to shift register.This shift register operate in the valid period and hide from view during and comprise a plurality of shifting deposit units of continuous serial connection.Each shifting deposit unit is subjected to the control of first and second clock pulse signal producing an output signal, and output signal periodically be activated (activated).Each shifting deposit unit comprises first and second switchgear and first and second drive unit.First switchgear provides output signal by output node.Second drive unit and second switch device couple voltage signal.The method comprises: in the valid period: voltage signal is switched to a low voltage level, and first and second clock pulse signal is set at two anti-phase each other AC signal; By first drive unit according to first input signal to drive the first switchgear sense activation signal; According to first clock pulse signal, do not activate (de-activated) output signal by second drive unit to drive first switchgear by voltage signal; When first switchgear not during sense activation signal, by the second switch device according to the second clock pulse signal, so that voltage signal is provided to output node; And during this hides from view: voltage signal is switched to high level, and be a direct current signal with each signal sets of first and second clock pulse signal.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Fig. 1 represents the shifting deposit unit of known shift register;
Fig. 2 represents the signal timing diagram of known shifting deposit unit;
Fig. 3 represents according to shift register of the present invention;
Fig. 4 represents the shifting deposit unit according to first embodiment of the invention;
Fig. 5 represents the signal timing diagram of shifting deposit unit among first embodiment;
Fig. 6 represents the control method process flow diagram according to the shift register of first embodiment of the invention; And
Fig. 7 represents the shifting deposit unit according to second embodiment of the invention.
And the description of reference numerals in the above-mentioned accompanying drawing is as follows:
1 shifting deposit unit;
The C10 capacitor:
CK, CLK clock pulse signal;
The N10...N12 node;
The T10...T16 transistor;
The Vss voltage source;
3 shift registers;
30 1-31 MShifting deposit unit;
The 40-42 drive unit;
The 43-47 switchgear;
The C40 capacitor;
The N40...N42 node;
The T40...T47 transistor.
Embodiment
Fig. 3 represents shift register according to an embodiment of the invention, is applicable to display panels, and during operating in the valid period and hiding from view.Consult Fig. 3, shift register 3 comprises a plurality of shifting deposit units 30 of continuous serial connection 1-30 MEach shifting deposit unit is controlled by clock pulse signal CK and XCK, and couples voltage source V ss.Each shifting deposit unit receives first input signal and second input signal, and according to clock pulse signal CK and XCK to produce an output signal.Shifting deposit unit 30 1-31 MThe output signal S that is produced 1-S MBe activated in order (activated), and each output signal is periodically to be activated.
Shifting deposit unit 30 2-30 MEach 30 N(1＜N＜M, and N is an integer) receives the shifting deposit unit 30 of previous stage N-1The output signal S that is produced N-1With as first input signal, and receive the shifting deposit unit 30 of back one-level N+1The output signal S that is produced N+1With as second input signal, wherein, output signal S N-1, S N, S N+1Be activated in order.For instance, shifting deposit unit 30 2Reception is from previous stage shifting deposit unit 30 1Output signal S 1With from back one-level shifting deposit unit 30 3Output signal S 3, and produce output signal S 2Shifting deposit unit 30 2The output signal S that produces 2Then by back one-level shifting deposit unit 30 3Receive.
Shifting deposit unit 30 1Be the first order, it is except receiving shifting deposit unit 30 2The output signal S that produces 2Receive the drive signal S that is produced by external circuit or inner other circuit in addition outward, DWith as first input signal, wherein, drive signal S D, output signal S 1, and output signal S 2Be activated in order.Similarly, shifting deposit unit 30 MBe afterbody, it is except receiving shifting deposit unit 30 M-1The output signal S that produces M-1Receive the control signal S that is produced by external circuit or inner other circuit in addition outward, CWith as second input signal, wherein, drive signal S M-1, output signal S M, and output signal S CBe activated in order.
First embodiment:
Fig. 4 represents the shifting deposit unit according to first embodiment of the invention.In Fig. 4, with the shifting deposit unit 30 of shift register 3 2For example illustrates, other shifting deposit unit 30 1And 30 3-30 MHas identical circuit.Shifting deposit unit 30 2Reception is from previous stage shifting deposit unit 30 1Output signal S 1With as first input signal, and receive from back one-level shifting deposit unit 30 3Output signal S 3With as second input signal.
Shifting deposit unit 30 2Comprise drive unit 40-42, switchgear 43-47, reach capacitor C40.In this embodiment, drive unit 40-42 and switchgear 43-47 realize with nmos pass transistor T40-T42 and T43-T47 respectively.Transistor T 41, T42, and the source electrode of T44-T47 all couple voltage source V ss.In addition, in the following description, when output signal is in high level, then represent its be activated (activated); When output signal is in low level, then represent its be not activated (de-activated).Fig. 5 represents the signal timing diagram of shifting deposit unit among first embodiment.Shifting deposit unit 30 2Operate in valid period PA and hide from view period P B.In valid period PA, voltage source V ss provides low level voltage signal, and clock pulse signal CK and XCK are anti-phase each other AC signal; And in hiding from view period P B, voltage source V ss becomes the voltage signal that high level is provided, and clock pulse signal CK and XCK become low level direct current signal.Shifting deposit unit 30 2Detail operations will illustrate by following.
In the time point P50 of valid period PA, output signal S 1Become high level, and transistor T 40 conductings.The voltage V of node N40 N40According to output signal S 1And become high level, with turn-on transistor T43 and T45.At this moment, because clock pulse signal CK is in low level and transistor T 45 conductings, so the voltage V of node N41 N41For low level to close transistor T 41.In addition, the clock pulse signal XCK of high level then turn-on transistor T46 so that output signal S 2Be in low level, i.e. output signal S 2Be not activated.
In the time point P51 of valid period PA, output signal S 1Become low level, therefore transistor T 40 closes.Clock pulse signal CK becomes high level.During time point P51 to P52, the clock pulse signal CK of high level is coupled to node N40 by capacitor C40 and transistor T 41, makes the voltage V of node N40 N40Be changed to higher level along with the level of clock pulse signal CK, with turn-on transistor T43 and transistor T 45.The low level voltage signal of voltage source V ss provides to node N41, to close transistor T 41, makes transistor T 41 ineffective (disabled).The clock pulse signal CK of high level is sent to node N42 by transistor T 43, and makes output node N42 become high level, with sense activation signal S 2The low level voltage signal of voltage source V ss is sent to node N41 by transistor T 45, makes voltage V N41Still be in low level.In addition, because low level clock pulse signal XCK closes transistor T 46 and low level voltage V N41 Close transistor T 47, can keep output signal S thus 2State of activation.
In the time point P52 of valid period PA, clock pulse signal CK becomes low level, and output signal S 3Be activated with turn-on transistor T42.The voltage V of node N40 N40Descend gradually according to the low level voltage signal of voltage source V ss,, make not sense activation signal S of transistor T 43 to close transistor T 43 and transistor T 45 2At this moment, the clock pulse signal XCK turn-on transistor T46 of high level, make the low level voltage signal of voltage source V ss provide to output node N42 with as output signal S 2In other words, output signal S 2Become low level, promptly become the state that is not activated.
In the time point P53 of valid period PA, clock pulse signal CK becomes high level, makes the voltage V of node N41 N41Become high level, with turn-on transistor T41.The low level voltage signal of voltage source V ss provides to node N40 by the transistor T 41 of conducting.Therefore, the voltage V of node N40 N40Maintain low level to close transistor T 43, make its not sense activation signal S 2In addition, the voltage V of high level N41Turn-on transistor T47, make the low level voltage signal of voltage source V ss provide to output node N42 with as output signal S 2So output signal S 2Maintain the state that is not activated.During after time point P53 in valid period PA, shifting deposit unit 30 2Then according to clock pulse signal CK and XCK and operate.The voltage V of node N41 N41Between high level and low level, switch.
The high level of supposing clock pulse signal CK is 15V, and low level is-9V, and the voltage signal that voltage source V ss provides is-7V.In above-mentioned valid period PA, when time clock signal CK was in high level with turn-on transistor T41, the grid of transistor T 41 and the voltage difference of source electrode were 22V, and promptly the gate source voltage of transistor T 41 (Vgs) is in big positive bias stress.Similarly, the gate source voltage of transistor T 43, T42, T45, T46, T47 also can be in big positive bias stress.And this positive bias stress can make transistorized critical voltage (Vth) be offset.
In hiding from view period P B, output signal S 1-S 3Be in low level, and clock pulse signal CK and XCK become low level direct current signal, specifically, voltage source V ss becomes the voltage signal that provides identical with the high level of clock pulse signal CK.Therefore, in hiding from view period P B, the gate source voltage of transistor T 41 then is in negative bias stress, and then it is offset balanced effect to critical voltage.Similarly, the gate source voltage of transistor T 42, T43, T45, T46, T47 also is in negative bias stress in hiding from view period P B, to compensate its critical voltage skew.
In this embodiment, the grid of transistor T 44 and source electrode are coupled to voltage source V ss.In hiding from view period P B, the high level voltage signal conduction transistor T 44 of voltage source V ss makes output node N42 be in high level, makes the gate source voltage of transistor T 43 be in negative bias stress thus, to compensate its critical voltage skew.
Fig. 6 represents the control method process flow diagram according to the shift register of first embodiment of the invention.Below will consult Fig. 4-Fig. 6 illustrates.In valid period AP, the voltage signal of voltage source V ss is switched to low level, and clock pulse signal CK and XCK are set AC signal (step S60).Then, by drive unit 40 according to input signal S 1With driving switch device 43 sense activation signal S 2(step S61).According to clock pulse signal CK, come not sense activation signal S of driving switch device 43 by drive unit 41 with low level voltage signal by voltage source V ss 2(step S62).As switchgear 43 sense activation signal S not 2The time,, provide to output node N42 according to clock pulse signal XCK by switchgear 46, with as output signal S with low level voltage signal with voltage source V ss 2(step S63).Hiding from view period P B, the voltage signal of voltage source V ss is being switched to high level, and clock pulse signal CK and XCK are set at direct current signal (step S64).
Second embodiment:
Fig. 7 represents the shifting deposit unit according to second embodiment of the invention, illustrates with the shifting deposit unit 302 of shift register 3.In Fig. 4 and Fig. 7, identical symbolic representation components identical or signal.Consult Fig. 4 and Fig. 7, the circuit connection and the signal sequence of element are roughly the same, difference is, the shifting deposit unit of second embodiment does not comprise switchgear 44, in addition, and among first embodiment of Fig. 4, transistor T 41, T42, and the source electrode of T45-T47 all couple voltage source V ss, and among the embodiment of Fig. 7, the source electrode of transistor T 41 is not to couple voltage source V ss, but couples clock pulse signal XCK.In a second embodiment, the voltage signal that voltage source V ss provided maintains low level always and can not change high level into.Transistor T 41 to close transistor T 43, makes not sense activation signal S of transistor T 43 according to clock pulse signal CK and during conducting, clock pulse signal XCK is sent to node N40 2
Because the source electrode of transistor T 41 couples clock pulse signal XCK and its grid is coupled to clock pulse signal CK by capacitor C40, therefore grid-the source voltage of transistor T 41 can alternatively operate in the valid period under positive bias stress and the negative bias stress, and this can make the situation of the critical voltage skew of transistor T 41 alleviate.
According to the shift register of the embodiment of the invention, suffer negative bias stress by making transistor gate-source voltage, make because the critical voltage skew that positive bias stress is caused can obtain to slow down.
Though the present invention with preferred embodiment openly as above; yet it is not in order to limit scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that accompanying Claim defines.

Claims (15)

1. shift register operates in during a valid period and one hides from view, and comprising:
A plurality of shifting deposit units, described shifting deposit unit is connected in series continuously, each this shifting deposit unit is subjected to the control of one first clock pulse signal and a second clock pulse signal to produce an output signal and this output signal periodically is activated, and wherein, each this shifting deposit unit comprises:
One first switchgear is in order to provide this output signal by an output node;
One first drive unit, in order to this valid period according to one first input signal, activate this output signal to drive this first switchgear;
One second drive unit couples a voltage signal, in order to this valid period according to this first clock pulse signal, do not activate this output signal to drive this first switchgear by this voltage signal; And
One second switch device couples this voltage signal, when this first switchgear does not activate this output signal, in order to according to this second clock pulse signal so that this voltage signal is provided to this output node;
Wherein, in this valid period, this voltage signal has a low level, and this first and second clock pulse signal is two anti-phase each other AC signal; And
Wherein, during this hid from view, this voltage signal had a high level, and each signal of this first and second clock pulse signal is a direct current signal.
2. shift register as claimed in claim 1, wherein, each this shifting deposit unit also comprises:
One the 3rd drive unit couples this voltage signal, in order to according to one second input signal, does not activate this output signal to drive this first switchgear by this voltage signal; And
Wherein, be activated to each signal period property of this first and second input signal, and this first input signal, this output signal, this second input signal are activated in order.
3. shift register as claimed in claim 2, wherein, described shifting deposit unit comprise at least continuous serial connection first, second, and the 3rd shifting deposit unit, this output signal of this first shifting deposit unit is as this first input signal of this second shifting deposit unit, this output signal of this second shifting deposit unit is as this first input signal of the 3rd shifting deposit unit and this second input signal of this first shifting deposit unit, and this output signal of the 3rd shifting deposit unit is as this second input signal of this second shifting deposit unit.
4. shift register as claimed in claim 1, wherein, each this shifting deposit unit also comprises:
One the 3rd switchgear couples this voltage signal, when this first switchgear does not activate this output signal, in order to according to this first clock pulse signal so that this voltage signal is provided to this output node.
5. shift register as claimed in claim 1, wherein, each this shifting deposit unit also comprises:
One the 4th switchgear couples this voltage signal, and is when this first drive unit drives this first switchgear and activates this output signal, ineffective in order to make this second drive unit by this voltage signal.
6. shift register as claimed in claim 1, wherein, each this shifting deposit unit also comprises:
One the 5th switchgear couples this voltage signal, in order to during hiding from view at this this voltage signal is provided to this output node.
7. shift register as claimed in claim 1, wherein, described shifting deposit unit comprise at least continuous serial connection first, second, and the 3rd shifting deposit unit, this output signal of this first shifting deposit unit is as this first input signal of this second shifting deposit unit, and this output signal of this second shifting deposit unit is as this first input signal of the 3rd shifting deposit unit.
8. shift register comprises:
A plurality of shifting deposit units, described shifting deposit unit is connected in series continuously, each this shifting deposit unit is subjected to one first anti-phase each other clock pulse signal and second clock pulse signal control to produce an output signal, and this output signal periodically is activated, wherein, each this shifting deposit unit comprises:
One first switchgear is in order to provide this output signal by an output node;
One first drive unit in order to according to one first input signal, activates this output signal to drive this first switchgear;
One second drive unit couples this second clock pulse signal, in order to according to this first clock pulse signal, transmits this second clock pulse signal and drives this first switchgear and make this first switchgear not activate this output signal; And
One second switch device couples this voltage signal, in order to when this first switchgear does not activate this output signal, according to this second clock pulse signal this voltage signal is provided to this output node.
9. shift register as claimed in claim 8, wherein, each this shifting deposit unit also comprises:
One the 3rd drive unit couples this voltage signal, in order to according to one second input signal, does not activate this output signal to drive this first switchgear by this voltage signal; And
Wherein, be activated to this first and second input signal cycle, and this first input signal, this output signal, this second input signal are activated in order.
10. shift register as claimed in claim 9, wherein, described shifting deposit unit comprise at least continuous serial connection first, second, and the 3rd shifting deposit unit, this output signal of this first shifting deposit unit is as this first input signal of this second shifting deposit unit, this output signal of this second shifting deposit unit is as this first input signal of the 3rd shifting deposit unit and this second input signal of this first shifting deposit unit, and this output signal of the 3rd shifting deposit unit is as this second input signal of this second shifting deposit unit.
11. shift register as claimed in claim 8, wherein, each this shifting deposit unit also comprises:
One the 3rd switchgear couples this voltage signal, when this first switchgear does not activate this output signal, in order to according to this first clock pulse signal so that this voltage signal is provided to this output node.
12. shift register as claimed in claim 8, wherein, each this shifting deposit unit also comprises:
One the 4th switchgear couples this voltage signal, and is when this first drive unit drives this first switchgear and activates this output signal, ineffective in order to make this second drive unit by this voltage signal.
13. shift register as claimed in claim 8, wherein, described shifting deposit unit comprise at least continuous serial connection first, second, and the 3rd shifting deposit unit, this output signal of this first shifting deposit unit is as this first input signal of this second shifting deposit unit, and this output signal of this second shifting deposit unit is as this first input signal of the 3rd shifting deposit unit.
14. shift register as claimed in claim 8, wherein, this voltage signal has a low voltage level.
15. the control method of a shift register, be applicable to a shift register, this shift register operate in a valid period and one hide from view during and comprise a plurality of shifting deposit units of continuous serial connection, each this shifting deposit unit is subjected to first and second clock pulse signal control to produce an output signal, and this output signal periodically is activated, each this shifting deposit unit comprises one first switchgear, one first drive unit, one second drive unit, an and second switch device, this first switchgear provides this output signal by an output node, this second drive unit and this second switch device couple a voltage signal, and this method comprises:
In this valid period:
This voltage signal is switched to a low voltage level, and this first and second clock pulse signal is set at two anti-phase each other AC signal;
Activate this output signal according to one first input signal to drive this first switchgear by this first drive unit;
According to this first clock pulse signal, do not activate this output signal by this second drive unit to drive this first switchgear by this voltage signal;
When this first switchgear does not activate this output signal, by this second switch device according to this second clock pulse signal, so that this voltage signal is provided to this output node; And
During this hides from view:
This voltage signal is switched to a high level, and be a direct current signal each signal sets of this first and second clock pulse signal.
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US7872506B2 (en) 2008-11-04 2011-01-18 Au Optronics Corporation Gate driver and method for making same
CN103295642B (en) * 2012-09-19 2016-02-17 上海中航光电子有限公司 Shift register and panel display apparatus
CN104715734B (en) * 2015-04-14 2017-08-08 京东方科技集团股份有限公司 Shift register, gate driving circuit and display device
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US20200211668A1 (en) * 2018-12-28 2020-07-02 Int Tech Co., Ltd. Shift register and method thereof
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